1 # SPDX-License-Identifier: GPL-2.0
3 # For a description of the syntax of this configuration file,
4 # see Documentation/kbuild/kconfig-language.rst.
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_DMA_SET_UNCACHED
11 select ARCH_HAS_DMA_CLEAR_UNCACHED
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
14 select OF_EARLY_FLATTREE
16 select HANDLE_DOMAIN_IRQ
18 select HAVE_ARCH_TRACEHOOK
20 select GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
24 select GENERIC_CPU_DEVICES
26 select GENERIC_ATOMIC64
27 select GENERIC_CLOCKEVENTS_BROADCAST
28 select GENERIC_STRNCPY_FROM_USER
29 select GENERIC_STRNLEN_USER
30 select GENERIC_SMP_IDLE_THREAD
31 select MODULES_USE_ELF_RELA
32 select HAVE_DEBUG_STACKOVERFLOW
34 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
35 select ARCH_USE_QUEUED_SPINLOCKS
36 select ARCH_USE_QUEUED_RWLOCKS
38 select ARCH_WANT_FRAME_POINTERS
39 select GENERIC_IRQ_MULTI_HANDLER
40 select MMU_GATHER_NO_RANGE if MMU
49 config GENERIC_HWEIGHT
55 config TRACE_IRQFLAGS_SUPPORT
58 # For now, use generic checksum functions
59 #These can be reimplemented in assembly later if so inclined
63 config STACKTRACE_SUPPORT
66 config LOCKDEP_SUPPORT
69 menu "Processor type and features"
72 prompt "Subarchitecture"
78 Generic OpenRISC 1200 architecture
82 config DCACHE_WRITETHROUGH
83 bool "Have write through data caches"
86 Select this if your implementation features write through data caches.
87 Selecting 'N' here will allow the kernel to force flushing of data
88 caches at relevant times. Most OpenRISC implementations support write-
93 config OPENRISC_BUILTIN_DTB
97 menu "Class II Instructions"
99 config OPENRISC_HAVE_INST_FF1
100 bool "Have instruction l.ff1"
103 Select this if your implementation has the Class II instruction l.ff1
105 config OPENRISC_HAVE_INST_FL1
106 bool "Have instruction l.fl1"
109 Select this if your implementation has the Class II instruction l.fl1
111 config OPENRISC_HAVE_INST_MUL
112 bool "Have instruction l.mul for hardware multiply"
115 Select this if your implementation has a hardware multiply instruction
117 config OPENRISC_HAVE_INST_DIV
118 bool "Have instruction l.div for hardware divide"
121 Select this if your implementation has a hardware divide instruction
125 int "Maximum number of CPUs (2-32)"
131 bool "Symmetric Multi-Processing support"
133 This enables support for systems with more than one CPU. If you have
134 a system with only one CPU, say N. If you have a system with more
137 If you don't know what to do here, say N.
139 source "kernel/Kconfig.hz"
141 config OPENRISC_NO_SPR_SR_DSX
142 bool "use SPR_SR_DSX software emulation" if OR1K_1200
145 SPR_SR_DSX bit is status register bit indicating whether
146 the last exception has happened in delay slot.
148 OpenRISC architecture makes it optional to have it implemented
149 in hardware and the OR1200 does not have it.
151 Say N here if you know that your OpenRISC processor has
152 SPR_SR_DSX bit implemented. Say Y if you are unsure.
154 config OPENRISC_HAVE_SHADOW_GPRS
155 bool "Support for shadow gpr files" if !SMP
158 Say Y here if your OpenRISC processor features shadowed
159 register files. They will in such case be used as a
160 scratch reg storage on exception entry.
162 On SMP systems, this feature is mandatory.
163 On a unicore system it's safe to say N here if you are unsure.
166 string "Default kernel command string"
169 On some architectures there is currently no way for the boot loader
170 to pass arguments to the kernel. For these architectures, you should
171 supply some command-line options at build time by entering them
174 menu "Debugging options"
176 config JUMP_UPON_UNHANDLED_EXCEPTION
177 bool "Try to die gracefully"
180 Now this puts kernel into infinite loop after first oops. Till
181 your kernel crashes this doesn't have any influence.
183 Say Y if you are unsure.
185 config OPENRISC_ESR_EXCEPTION_BUG_CHECK
186 bool "Check for possible ESR exception bug"
189 This option enables some checks that might expose some problems
192 Say N if you are unsure.