arch/parisc/include/asm/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASM_PARISC_PCI_H
   3 #define __ASM_PARISC_PCI_H
   4
   5 #include <linux/scatterlist.h>
   6
   7
   8
   9 /*
  10 ** HP PCI platforms generally support multiple bus adapters.
  11 **    (workstations 1-~4, servers 2-~32)
  12 **
  13 ** Newer platforms number the busses across PCI bus adapters *sparsely*.
  14 ** E.g. 0, 8, 16, ...
  15 **
  16 ** Under a PCI bus, most HP platforms support PPBs up to two or three
  17 ** levels deep. See "Bit3" product line.
  18 */
  19 #define PCI_MAX_BUSSES  256
  20
  21
  22 /* To be used as: mdelay(pci_post_reset_delay);
  23  *
  24  * post_reset is the time the kernel should stall to prevent anyone from
  25  * accessing the PCI bus once #RESET is de-asserted.
  26  * PCI spec somewhere says 1 second but with multi-PCI bus systems,
  27  * this makes the boot time much longer than necessary.
  28  * 20ms seems to work for all the HP PCI implementations to date.
  29  */
  30 #define pci_post_reset_delay 50
  31
  32
  33 /*
  34 ** pci_hba_data (aka H2P_OBJECT in HP/UX)
  35 **
  36 ** This is the "common" or "base" data structure which HBA drivers
  37 ** (eg Dino or LBA) are required to place at the top of their own
  38 ** platform_data structure.  I've heard this called "C inheritance" too.
  39 **
  40 ** Data needed by pcibios layer belongs here.
  41 */
  42 struct pci_hba_data {
  43         void __iomem   *base_addr;      /* aka Host Physical Address */
  44         const struct parisc_device *dev; /* device from PA bus walk */
  45         struct pci_bus *hba_bus;        /* primary PCI bus below HBA */
  46         int             hba_num;        /* I/O port space access "key" */
  47         struct resource bus_num;        /* PCI bus numbers */
  48         struct resource io_space;       /* PIOP */
  49         struct resource lmmio_space;    /* bus addresses < 4Gb */
  50         struct resource elmmio_space;   /* additional bus addresses < 4Gb */
  51         struct resource gmmio_space;    /* bus addresses > 4Gb */
  52
  53         /* NOTE: Dino code assumes it can use *all* of the lmmio_space,
  54          * elmmio_space and gmmio_space as a contiguous array of
  55          * resources.  This #define represents the array size */
  56         #define DINO_MAX_LMMIO_RESOURCES        3
  57
  58         unsigned long   lmmio_space_offset;  /* CPU view - PCI view */
  59         struct ioc      *iommu;         /* IOMMU this device is under */
  60         /* REVISIT - spinlock to protect resources? */
  61
  62         #define HBA_NAME_SIZE 16
  63         char io_name[HBA_NAME_SIZE];
  64         char lmmio_name[HBA_NAME_SIZE];
  65         char elmmio_name[HBA_NAME_SIZE];
  66         char gmmio_name[HBA_NAME_SIZE];
  67 };
  68
  69 /*
  70 ** We support 2^16 I/O ports per HBA.  These are set up in the form
  71 ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
  72 ** space address.
  73 */
  74 #define HBA_PORT_SPACE_BITS     16
  75
  76 #define HBA_PORT_BASE(h)        ((h) << HBA_PORT_SPACE_BITS)
  77 #define HBA_PORT_SPACE_SIZE     (1UL << HBA_PORT_SPACE_BITS)
  78
  79 #define PCI_PORT_HBA(a)         ((a) >> HBA_PORT_SPACE_BITS)
  80 #define PCI_PORT_ADDR(a)        ((a) & (HBA_PORT_SPACE_SIZE - 1))
  81
  82 #ifdef CONFIG_64BIT
  83 #define PCI_F_EXTEND            0xffffffff00000000UL
  84 #else   /* !CONFIG_64BIT */
  85 #define PCI_F_EXTEND            0UL
  86 #endif /* !CONFIG_64BIT */
  87
  88 /*
  89 ** Most PCI devices (eg Tulip, NCR720) also export the same registers
  90 ** to both MMIO and I/O port space.  Due to poor performance of I/O Port
  91 ** access under HP PCI bus adapters, strongly recommend the use of MMIO
  92 ** address space.
  93 **
  94 ** While I'm at it more PA programming notes:
  95 **
  96 ** 1) MMIO stores (writes) are posted operations. This means the processor
  97 **    gets an "ACK" before the write actually gets to the device. A read
  98 **    to the same device (or typically the bus adapter above it) will
  99 **    force in-flight write transaction(s) out to the targeted device
 100 **    before the read can complete.
 101 **
 102 ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
 103 **    respect to DMA on all platforms. Ie PIO data can reach the processor
 104 **    before in-flight DMA reaches memory. Since most SMP PA platforms
 105 **    are I/O coherent, it generally doesn't matter...but sometimes
 106 **    it does.
 107 **
 108 ** I've helped device driver writers debug both types of problems.
 109 */
 110 struct pci_port_ops {
 111           u8 (*inb)  (struct pci_hba_data *hba, u16 port);
 112          u16 (*inw)  (struct pci_hba_data *hba, u16 port);
 113          u32 (*inl)  (struct pci_hba_data *hba, u16 port);
 114         void (*outb) (struct pci_hba_data *hba, u16 port,  u8 data);
 115         void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
 116         void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
 117 };
 118
 119
 120 struct pci_bios_ops {
 121         void (*init)(void);
 122         void (*fixup_bus)(struct pci_bus *bus);
 123 };
 124
 125 /*
 126 ** Stuff declared in arch/parisc/kernel/pci.c
 127 */
 128 extern struct pci_port_ops *pci_port;
 129 extern struct pci_bios_ops *pci_bios;
 130
 131 #ifdef CONFIG_PCI
 132 extern void pcibios_register_hba(struct pci_hba_data *);
 133 #else
 134 static inline void pcibios_register_hba(struct pci_hba_data *x)
 135 {
 136 }
 137 #endif
 138 extern void pcibios_init_bridge(struct pci_dev *);
 139
 140 /*
 141  * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
 142  *   0 == check if bridge is numbered before re-numbering.
 143  *   1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
 144  *
 145  *   We *should* set this to zero for "legacy" platforms and one
 146  *   for PAT platforms.
 147  *
 148  *   But legacy platforms also need to renumber the busses below a Host
 149  *   Bus controller.  Adding a 4-port Tulip card on the first PCI root
 150  *   bus of a C200 resulted in the secondary bus being numbered as 1.
 151  *   The second PCI host bus controller's root bus had already been
 152  *   assigned bus number 1 by firmware and sysfs complained.
 153  *
 154  *   Firmware isn't doing anything wrong here since each controller
 155  *   is its own PCI domain.  It's simpler and easier for us to renumber
 156  *   the busses rather than treat each Dino as a separate PCI domain.
 157  *   Eventually, we may want to introduce PCI domains for Superdome or
 158  *   rp7420/8420 boxes and then revisit this issue.
 159  */
 160 #define pcibios_assign_all_busses()     (1)
 161
 162 #define PCIBIOS_MIN_IO          0x10
 163 #define PCIBIOS_MIN_MEM         0x1000 /* NBPG - but pci/setup-res.c dies */
 164
 165 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 166 {
 167         return channel ? 15 : 14;
 168 }
 169
 170 #define HAVE_PCI_MMAP
 171 #define ARCH_GENERIC_PCI_MMAP_RESOURCE
 172
 173 #endif /* __ASM_PARISC_PCI_H */