drivers/clk/at91/clk-plldiv.c

   1 /*
   2  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk/at91_pmc.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/io.h>
  17
  18 #include "pmc.h"
  19
  20 #define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
  21
  22 struct clk_plldiv {
  23         struct clk_hw hw;
  24         struct at91_pmc *pmc;
  25 };
  26
  27 static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
  28                                             unsigned long parent_rate)
  29 {
  30         struct clk_plldiv *plldiv = to_clk_plldiv(hw);
  31         struct at91_pmc *pmc = plldiv->pmc;
  32
  33         if (pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_PLLADIV2)
  34                 return parent_rate / 2;
  35
  36         return parent_rate;
  37 }
  38
  39 static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
  40                                         unsigned long *parent_rate)
  41 {
  42         unsigned long div;
  43
  44         if (rate > *parent_rate)
  45                 return *parent_rate;
  46         div = *parent_rate / 2;
  47         if (rate < div)
  48                 return div;
  49
  50         if (rate - div < *parent_rate - rate)
  51                 return div;
  52
  53         return *parent_rate;
  54 }
  55
  56 static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
  57                                unsigned long parent_rate)
  58 {
  59         struct clk_plldiv *plldiv = to_clk_plldiv(hw);
  60         struct at91_pmc *pmc = plldiv->pmc;
  61         u32 tmp;
  62
  63         if (parent_rate != rate && (parent_rate / 2) != rate)
  64                 return -EINVAL;
  65
  66         pmc_lock(pmc);
  67         tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2;
  68         if ((parent_rate / 2) == rate)
  69                 tmp |= AT91_PMC_PLLADIV2;
  70         pmc_write(pmc, AT91_PMC_MCKR, tmp);
  71         pmc_unlock(pmc);
  72
  73         return 0;
  74 }
  75
  76 static const struct clk_ops plldiv_ops = {
  77         .recalc_rate = clk_plldiv_recalc_rate,
  78         .round_rate = clk_plldiv_round_rate,
  79         .set_rate = clk_plldiv_set_rate,
  80 };
  81
  82 static struct clk * __init
  83 at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name,
  84                          const char *parent_name)
  85 {
  86         struct clk_plldiv *plldiv;
  87         struct clk *clk = NULL;
  88         struct clk_init_data init;
  89
  90         plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
  91         if (!plldiv)
  92                 return ERR_PTR(-ENOMEM);
  93
  94         init.name = name;
  95         init.ops = &plldiv_ops;
  96         init.parent_names = parent_name ? &parent_name : NULL;
  97         init.num_parents = parent_name ? 1 : 0;
  98         init.flags = CLK_SET_RATE_GATE;
  99
 100         plldiv->hw.init = &init;
 101         plldiv->pmc = pmc;
 102
 103         clk = clk_register(NULL, &plldiv->hw);
 104
 105         if (IS_ERR(clk))
 106                 kfree(plldiv);
 107
 108         return clk;
 109 }
 110
 111 static void __init
 112 of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc)
 113 {
 114         struct clk *clk;
 115         const char *parent_name;
 116         const char *name = np->name;
 117
 118         parent_name = of_clk_get_parent_name(np, 0);
 119
 120         of_property_read_string(np, "clock-output-names", &name);
 121
 122         clk = at91_clk_register_plldiv(pmc, name, parent_name);
 123
 124         if (IS_ERR(clk))
 125                 return;
 126
 127         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 128         return;
 129 }
 130
 131 void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np,
 132                                            struct at91_pmc *pmc)
 133 {
 134         of_at91_clk_plldiv_setup(np, pmc);
 135 }