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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / clk / qcom / gcc-msm8960.c
blobfd446ab2fd98b996b164c8b0687d235284349a56
1 /*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
24
25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
27
28 #include "clk-regmap.h"
29 #include "clk-pll.h"
30 #include "clk-rcg.h"
31 #include "clk-branch.h"
32 #include "reset.h"
33
34 static struct clk_pll pll3 = {
35 .l_reg = 0x3164,
36 .m_reg = 0x3168,
37 .n_reg = 0x316c,
38 .config_reg = 0x3174,
39 .mode_reg = 0x3160,
40 .status_reg = 0x3178,
41 .status_bit = 16,
42 .clkr.hw.init = &(struct clk_init_data){
43 .name = "pll3",
44 .parent_names = (const char *[]){ "pxo" },
45 .num_parents = 1,
46 .ops = &clk_pll_ops,
47 },
48 };
49
50 static struct clk_pll pll8 = {
51 .l_reg = 0x3144,
52 .m_reg = 0x3148,
53 .n_reg = 0x314c,
54 .config_reg = 0x3154,
55 .mode_reg = 0x3140,
56 .status_reg = 0x3158,
57 .status_bit = 16,
58 .clkr.hw.init = &(struct clk_init_data){
59 .name = "pll8",
60 .parent_names = (const char *[]){ "pxo" },
61 .num_parents = 1,
62 .ops = &clk_pll_ops,
63 },
64 };
65
66 static struct clk_regmap pll8_vote = {
67 .enable_reg = 0x34c0,
68 .enable_mask = BIT(8),
69 .hw.init = &(struct clk_init_data){
70 .name = "pll8_vote",
71 .parent_names = (const char *[]){ "pll8" },
72 .num_parents = 1,
73 .ops = &clk_pll_vote_ops,
74 },
75 };
76
77 static struct clk_pll pll14 = {
78 .l_reg = 0x31c4,
79 .m_reg = 0x31c8,
80 .n_reg = 0x31cc,
81 .config_reg = 0x31d4,
82 .mode_reg = 0x31c0,
83 .status_reg = 0x31d8,
84 .status_bit = 16,
85 .clkr.hw.init = &(struct clk_init_data){
86 .name = "pll14",
87 .parent_names = (const char *[]){ "pxo" },
88 .num_parents = 1,
89 .ops = &clk_pll_ops,
90 },
91 };
92
93 static struct clk_regmap pll14_vote = {
94 .enable_reg = 0x34c0,
95 .enable_mask = BIT(14),
96 .hw.init = &(struct clk_init_data){
97 .name = "pll14_vote",
98 .parent_names = (const char *[]){ "pll14" },
99 .num_parents = 1,
100 .ops = &clk_pll_vote_ops,
101 },
102 };
103
104 #define P_PXO 0
105 #define P_PLL8 1
106 #define P_CXO 2
107
108 static const u8 gcc_pxo_pll8_map[] = {
109 [P_PXO] = 0,
110 [P_PLL8] = 3,
111 };
112
113 static const char *gcc_pxo_pll8[] = {
114 "pxo",
115 "pll8_vote",
116 };
117
118 static const u8 gcc_pxo_pll8_cxo_map[] = {
119 [P_PXO] = 0,
120 [P_PLL8] = 3,
121 [P_CXO] = 5,
122 };
123
124 static const char *gcc_pxo_pll8_cxo[] = {
125 "pxo",
126 "pll8_vote",
127 "cxo",
128 };
129
130 static struct freq_tbl clk_tbl_gsbi_uart[] = {
131 { 1843200, P_PLL8, 2, 6, 625 },
132 { 3686400, P_PLL8, 2, 12, 625 },
133 { 7372800, P_PLL8, 2, 24, 625 },
134 { 14745600, P_PLL8, 2, 48, 625 },
135 { 16000000, P_PLL8, 4, 1, 6 },
136 { 24000000, P_PLL8, 4, 1, 4 },
137 { 32000000, P_PLL8, 4, 1, 3 },
138 { 40000000, P_PLL8, 1, 5, 48 },
139 { 46400000, P_PLL8, 1, 29, 240 },
140 { 48000000, P_PLL8, 4, 1, 2 },
141 { 51200000, P_PLL8, 1, 2, 15 },
142 { 56000000, P_PLL8, 1, 7, 48 },
143 { 58982400, P_PLL8, 1, 96, 625 },
144 { 64000000, P_PLL8, 2, 1, 3 },
145 { }
146 };
147
148 static struct clk_rcg gsbi1_uart_src = {
149 .ns_reg = 0x29d4,
150 .md_reg = 0x29d0,
151 .mn = {
152 .mnctr_en_bit = 8,
153 .mnctr_reset_bit = 7,
154 .mnctr_mode_shift = 5,
155 .n_val_shift = 16,
156 .m_val_shift = 16,
157 .width = 16,
158 },
159 .p = {
160 .pre_div_shift = 3,
161 .pre_div_width = 2,
162 },
163 .s = {
164 .src_sel_shift = 0,
165 .parent_map = gcc_pxo_pll8_map,
166 },
167 .freq_tbl = clk_tbl_gsbi_uart,
168 .clkr = {
169 .enable_reg = 0x29d4,
170 .enable_mask = BIT(11),
171 .hw.init = &(struct clk_init_data){
172 .name = "gsbi1_uart_src",
173 .parent_names = gcc_pxo_pll8,
174 .num_parents = 2,
175 .ops = &clk_rcg_ops,
176 .flags = CLK_SET_PARENT_GATE,
177 },
178 },
179 };
180
181 static struct clk_branch gsbi1_uart_clk = {
182 .halt_reg = 0x2fcc,
183 .halt_bit = 10,
184 .clkr = {
185 .enable_reg = 0x29d4,
186 .enable_mask = BIT(9),
187 .hw.init = &(struct clk_init_data){
188 .name = "gsbi1_uart_clk",
189 .parent_names = (const char *[]){
190 "gsbi1_uart_src",
191 },
192 .num_parents = 1,
193 .ops = &clk_branch_ops,
194 .flags = CLK_SET_RATE_PARENT,
195 },
196 },
197 };
198
199 static struct clk_rcg gsbi2_uart_src = {
200 .ns_reg = 0x29f4,
201 .md_reg = 0x29f0,
202 .mn = {
203 .mnctr_en_bit = 8,
204 .mnctr_reset_bit = 7,
205 .mnctr_mode_shift = 5,
206 .n_val_shift = 16,
207 .m_val_shift = 16,
208 .width = 16,
209 },
210 .p = {
211 .pre_div_shift = 3,
212 .pre_div_width = 2,
213 },
214 .s = {
215 .src_sel_shift = 0,
216 .parent_map = gcc_pxo_pll8_map,
217 },
218 .freq_tbl = clk_tbl_gsbi_uart,
219 .clkr = {
220 .enable_reg = 0x29f4,
221 .enable_mask = BIT(11),
222 .hw.init = &(struct clk_init_data){
223 .name = "gsbi2_uart_src",
224 .parent_names = gcc_pxo_pll8,
225 .num_parents = 2,
226 .ops = &clk_rcg_ops,
227 .flags = CLK_SET_PARENT_GATE,
228 },
229 },
230 };
231
232 static struct clk_branch gsbi2_uart_clk = {
233 .halt_reg = 0x2fcc,
234 .halt_bit = 6,
235 .clkr = {
236 .enable_reg = 0x29f4,
237 .enable_mask = BIT(9),
238 .hw.init = &(struct clk_init_data){
239 .name = "gsbi2_uart_clk",
240 .parent_names = (const char *[]){
241 "gsbi2_uart_src",
242 },
243 .num_parents = 1,
244 .ops = &clk_branch_ops,
245 .flags = CLK_SET_RATE_PARENT,
246 },
247 },
248 };
249
250 static struct clk_rcg gsbi3_uart_src = {
251 .ns_reg = 0x2a14,
252 .md_reg = 0x2a10,
253 .mn = {
254 .mnctr_en_bit = 8,
255 .mnctr_reset_bit = 7,
256 .mnctr_mode_shift = 5,
257 .n_val_shift = 16,
258 .m_val_shift = 16,
259 .width = 16,
260 },
261 .p = {
262 .pre_div_shift = 3,
263 .pre_div_width = 2,
264 },
265 .s = {
266 .src_sel_shift = 0,
267 .parent_map = gcc_pxo_pll8_map,
268 },
269 .freq_tbl = clk_tbl_gsbi_uart,
270 .clkr = {
271 .enable_reg = 0x2a14,
272 .enable_mask = BIT(11),
273 .hw.init = &(struct clk_init_data){
274 .name = "gsbi3_uart_src",
275 .parent_names = gcc_pxo_pll8,
276 .num_parents = 2,
277 .ops = &clk_rcg_ops,
278 .flags = CLK_SET_PARENT_GATE,
279 },
280 },
281 };
282
283 static struct clk_branch gsbi3_uart_clk = {
284 .halt_reg = 0x2fcc,
285 .halt_bit = 2,
286 .clkr = {
287 .enable_reg = 0x2a14,
288 .enable_mask = BIT(9),
289 .hw.init = &(struct clk_init_data){
290 .name = "gsbi3_uart_clk",
291 .parent_names = (const char *[]){
292 "gsbi3_uart_src",
293 },
294 .num_parents = 1,
295 .ops = &clk_branch_ops,
296 .flags = CLK_SET_RATE_PARENT,
297 },
298 },
299 };
300
301 static struct clk_rcg gsbi4_uart_src = {
302 .ns_reg = 0x2a34,
303 .md_reg = 0x2a30,
304 .mn = {
305 .mnctr_en_bit = 8,
306 .mnctr_reset_bit = 7,
307 .mnctr_mode_shift = 5,
308 .n_val_shift = 16,
309 .m_val_shift = 16,
310 .width = 16,
311 },
312 .p = {
313 .pre_div_shift = 3,
314 .pre_div_width = 2,
315 },
316 .s = {
317 .src_sel_shift = 0,
318 .parent_map = gcc_pxo_pll8_map,
319 },
320 .freq_tbl = clk_tbl_gsbi_uart,
321 .clkr = {
322 .enable_reg = 0x2a34,
323 .enable_mask = BIT(11),
324 .hw.init = &(struct clk_init_data){
325 .name = "gsbi4_uart_src",
326 .parent_names = gcc_pxo_pll8,
327 .num_parents = 2,
328 .ops = &clk_rcg_ops,
329 .flags = CLK_SET_PARENT_GATE,
330 },
331 },
332 };
333
334 static struct clk_branch gsbi4_uart_clk = {
335 .halt_reg = 0x2fd0,
336 .halt_bit = 26,
337 .clkr = {
338 .enable_reg = 0x2a34,
339 .enable_mask = BIT(9),
340 .hw.init = &(struct clk_init_data){
341 .name = "gsbi4_uart_clk",
342 .parent_names = (const char *[]){
343 "gsbi4_uart_src",
344 },
345 .num_parents = 1,
346 .ops = &clk_branch_ops,
347 .flags = CLK_SET_RATE_PARENT,
348 },
349 },
350 };
351
352 static struct clk_rcg gsbi5_uart_src = {
353 .ns_reg = 0x2a54,
354 .md_reg = 0x2a50,
355 .mn = {
356 .mnctr_en_bit = 8,
357 .mnctr_reset_bit = 7,
358 .mnctr_mode_shift = 5,
359 .n_val_shift = 16,
360 .m_val_shift = 16,
361 .width = 16,
362 },
363 .p = {
364 .pre_div_shift = 3,
365 .pre_div_width = 2,
366 },
367 .s = {
368 .src_sel_shift = 0,
369 .parent_map = gcc_pxo_pll8_map,
370 },
371 .freq_tbl = clk_tbl_gsbi_uart,
372 .clkr = {
373 .enable_reg = 0x2a54,
374 .enable_mask = BIT(11),
375 .hw.init = &(struct clk_init_data){
376 .name = "gsbi5_uart_src",
377 .parent_names = gcc_pxo_pll8,
378 .num_parents = 2,
379 .ops = &clk_rcg_ops,
380 .flags = CLK_SET_PARENT_GATE,
381 },
382 },
383 };
384
385 static struct clk_branch gsbi5_uart_clk = {
386 .halt_reg = 0x2fd0,
387 .halt_bit = 22,
388 .clkr = {
389 .enable_reg = 0x2a54,
390 .enable_mask = BIT(9),
391 .hw.init = &(struct clk_init_data){
392 .name = "gsbi5_uart_clk",
393 .parent_names = (const char *[]){
394 "gsbi5_uart_src",
395 },
396 .num_parents = 1,
397 .ops = &clk_branch_ops,
398 .flags = CLK_SET_RATE_PARENT,
399 },
400 },
401 };
402
403 static struct clk_rcg gsbi6_uart_src = {
404 .ns_reg = 0x2a74,
405 .md_reg = 0x2a70,
406 .mn = {
407 .mnctr_en_bit = 8,
408 .mnctr_reset_bit = 7,
409 .mnctr_mode_shift = 5,
410 .n_val_shift = 16,
411 .m_val_shift = 16,
412 .width = 16,
413 },
414 .p = {
415 .pre_div_shift = 3,
416 .pre_div_width = 2,
417 },
418 .s = {
419 .src_sel_shift = 0,
420 .parent_map = gcc_pxo_pll8_map,
421 },
422 .freq_tbl = clk_tbl_gsbi_uart,
423 .clkr = {
424 .enable_reg = 0x2a74,
425 .enable_mask = BIT(11),
426 .hw.init = &(struct clk_init_data){
427 .name = "gsbi6_uart_src",
428 .parent_names = gcc_pxo_pll8,
429 .num_parents = 2,
430 .ops = &clk_rcg_ops,
431 .flags = CLK_SET_PARENT_GATE,
432 },
433 },
434 };
435
436 static struct clk_branch gsbi6_uart_clk = {
437 .halt_reg = 0x2fd0,
438 .halt_bit = 18,
439 .clkr = {
440 .enable_reg = 0x2a74,
441 .enable_mask = BIT(9),
442 .hw.init = &(struct clk_init_data){
443 .name = "gsbi6_uart_clk",
444 .parent_names = (const char *[]){
445 "gsbi6_uart_src",
446 },
447 .num_parents = 1,
448 .ops = &clk_branch_ops,
449 .flags = CLK_SET_RATE_PARENT,
450 },
451 },
452 };
453
454 static struct clk_rcg gsbi7_uart_src = {
455 .ns_reg = 0x2a94,
456 .md_reg = 0x2a90,
457 .mn = {
458 .mnctr_en_bit = 8,
459 .mnctr_reset_bit = 7,
460 .mnctr_mode_shift = 5,
461 .n_val_shift = 16,
462 .m_val_shift = 16,
463 .width = 16,
464 },
465 .p = {
466 .pre_div_shift = 3,
467 .pre_div_width = 2,
468 },
469 .s = {
470 .src_sel_shift = 0,
471 .parent_map = gcc_pxo_pll8_map,
472 },
473 .freq_tbl = clk_tbl_gsbi_uart,
474 .clkr = {
475 .enable_reg = 0x2a94,
476 .enable_mask = BIT(11),
477 .hw.init = &(struct clk_init_data){
478 .name = "gsbi7_uart_src",
479 .parent_names = gcc_pxo_pll8,
480 .num_parents = 2,
481 .ops = &clk_rcg_ops,
482 .flags = CLK_SET_PARENT_GATE,
483 },
484 },
485 };
486
487 static struct clk_branch gsbi7_uart_clk = {
488 .halt_reg = 0x2fd0,
489 .halt_bit = 14,
490 .clkr = {
491 .enable_reg = 0x2a94,
492 .enable_mask = BIT(9),
493 .hw.init = &(struct clk_init_data){
494 .name = "gsbi7_uart_clk",
495 .parent_names = (const char *[]){
496 "gsbi7_uart_src",
497 },
498 .num_parents = 1,
499 .ops = &clk_branch_ops,
500 .flags = CLK_SET_RATE_PARENT,
501 },
502 },
503 };
504
505 static struct clk_rcg gsbi8_uart_src = {
506 .ns_reg = 0x2ab4,
507 .md_reg = 0x2ab0,
508 .mn = {
509 .mnctr_en_bit = 8,
510 .mnctr_reset_bit = 7,
511 .mnctr_mode_shift = 5,
512 .n_val_shift = 16,
513 .m_val_shift = 16,
514 .width = 16,
515 },
516 .p = {
517 .pre_div_shift = 3,
518 .pre_div_width = 2,
519 },
520 .s = {
521 .src_sel_shift = 0,
522 .parent_map = gcc_pxo_pll8_map,
523 },
524 .freq_tbl = clk_tbl_gsbi_uart,
525 .clkr = {
526 .enable_reg = 0x2ab4,
527 .enable_mask = BIT(11),
528 .hw.init = &(struct clk_init_data){
529 .name = "gsbi8_uart_src",
530 .parent_names = gcc_pxo_pll8,
531 .num_parents = 2,
532 .ops = &clk_rcg_ops,
533 .flags = CLK_SET_PARENT_GATE,
534 },
535 },
536 };
537
538 static struct clk_branch gsbi8_uart_clk = {
539 .halt_reg = 0x2fd0,
540 .halt_bit = 10,
541 .clkr = {
542 .enable_reg = 0x2ab4,
543 .enable_mask = BIT(9),
544 .hw.init = &(struct clk_init_data){
545 .name = "gsbi8_uart_clk",
546 .parent_names = (const char *[]){ "gsbi8_uart_src" },
547 .num_parents = 1,
548 .ops = &clk_branch_ops,
549 .flags = CLK_SET_RATE_PARENT,
550 },
551 },
552 };
553
554 static struct clk_rcg gsbi9_uart_src = {
555 .ns_reg = 0x2ad4,
556 .md_reg = 0x2ad0,
557 .mn = {
558 .mnctr_en_bit = 8,
559 .mnctr_reset_bit = 7,
560 .mnctr_mode_shift = 5,
561 .n_val_shift = 16,
562 .m_val_shift = 16,
563 .width = 16,
564 },
565 .p = {
566 .pre_div_shift = 3,
567 .pre_div_width = 2,
568 },
569 .s = {
570 .src_sel_shift = 0,
571 .parent_map = gcc_pxo_pll8_map,
572 },
573 .freq_tbl = clk_tbl_gsbi_uart,
574 .clkr = {
575 .enable_reg = 0x2ad4,
576 .enable_mask = BIT(11),
577 .hw.init = &(struct clk_init_data){
578 .name = "gsbi9_uart_src",
579 .parent_names = gcc_pxo_pll8,
580 .num_parents = 2,
581 .ops = &clk_rcg_ops,
582 .flags = CLK_SET_PARENT_GATE,
583 },
584 },
585 };
586
587 static struct clk_branch gsbi9_uart_clk = {
588 .halt_reg = 0x2fd0,
589 .halt_bit = 6,
590 .clkr = {
591 .enable_reg = 0x2ad4,
592 .enable_mask = BIT(9),
593 .hw.init = &(struct clk_init_data){
594 .name = "gsbi9_uart_clk",
595 .parent_names = (const char *[]){ "gsbi9_uart_src" },
596 .num_parents = 1,
597 .ops = &clk_branch_ops,
598 .flags = CLK_SET_RATE_PARENT,
599 },
600 },
601 };
602
603 static struct clk_rcg gsbi10_uart_src = {
604 .ns_reg = 0x2af4,
605 .md_reg = 0x2af0,
606 .mn = {
607 .mnctr_en_bit = 8,
608 .mnctr_reset_bit = 7,
609 .mnctr_mode_shift = 5,
610 .n_val_shift = 16,
611 .m_val_shift = 16,
612 .width = 16,
613 },
614 .p = {
615 .pre_div_shift = 3,
616 .pre_div_width = 2,
617 },
618 .s = {
619 .src_sel_shift = 0,
620 .parent_map = gcc_pxo_pll8_map,
621 },
622 .freq_tbl = clk_tbl_gsbi_uart,
623 .clkr = {
624 .enable_reg = 0x2af4,
625 .enable_mask = BIT(11),
626 .hw.init = &(struct clk_init_data){
627 .name = "gsbi10_uart_src",
628 .parent_names = gcc_pxo_pll8,
629 .num_parents = 2,
630 .ops = &clk_rcg_ops,
631 .flags = CLK_SET_PARENT_GATE,
632 },
633 },
634 };
635
636 static struct clk_branch gsbi10_uart_clk = {
637 .halt_reg = 0x2fd0,
638 .halt_bit = 2,
639 .clkr = {
640 .enable_reg = 0x2af4,
641 .enable_mask = BIT(9),
642 .hw.init = &(struct clk_init_data){
643 .name = "gsbi10_uart_clk",
644 .parent_names = (const char *[]){ "gsbi10_uart_src" },
645 .num_parents = 1,
646 .ops = &clk_branch_ops,
647 .flags = CLK_SET_RATE_PARENT,
648 },
649 },
650 };
651
652 static struct clk_rcg gsbi11_uart_src = {
653 .ns_reg = 0x2b14,
654 .md_reg = 0x2b10,
655 .mn = {
656 .mnctr_en_bit = 8,
657 .mnctr_reset_bit = 7,
658 .mnctr_mode_shift = 5,
659 .n_val_shift = 16,
660 .m_val_shift = 16,
661 .width = 16,
662 },
663 .p = {
664 .pre_div_shift = 3,
665 .pre_div_width = 2,
666 },
667 .s = {
668 .src_sel_shift = 0,
669 .parent_map = gcc_pxo_pll8_map,
670 },
671 .freq_tbl = clk_tbl_gsbi_uart,
672 .clkr = {
673 .enable_reg = 0x2b14,
674 .enable_mask = BIT(11),
675 .hw.init = &(struct clk_init_data){
676 .name = "gsbi11_uart_src",
677 .parent_names = gcc_pxo_pll8,
678 .num_parents = 2,
679 .ops = &clk_rcg_ops,
680 .flags = CLK_SET_PARENT_GATE,
681 },
682 },
683 };
684
685 static struct clk_branch gsbi11_uart_clk = {
686 .halt_reg = 0x2fd4,
687 .halt_bit = 17,
688 .clkr = {
689 .enable_reg = 0x2b14,
690 .enable_mask = BIT(9),
691 .hw.init = &(struct clk_init_data){
692 .name = "gsbi11_uart_clk",
693 .parent_names = (const char *[]){ "gsbi11_uart_src" },
694 .num_parents = 1,
695 .ops = &clk_branch_ops,
696 .flags = CLK_SET_RATE_PARENT,
697 },
698 },
699 };
700
701 static struct clk_rcg gsbi12_uart_src = {
702 .ns_reg = 0x2b34,
703 .md_reg = 0x2b30,
704 .mn = {
705 .mnctr_en_bit = 8,
706 .mnctr_reset_bit = 7,
707 .mnctr_mode_shift = 5,
708 .n_val_shift = 16,
709 .m_val_shift = 16,
710 .width = 16,
711 },
712 .p = {
713 .pre_div_shift = 3,
714 .pre_div_width = 2,
715 },
716 .s = {
717 .src_sel_shift = 0,
718 .parent_map = gcc_pxo_pll8_map,
719 },
720 .freq_tbl = clk_tbl_gsbi_uart,
721 .clkr = {
722 .enable_reg = 0x2b34,
723 .enable_mask = BIT(11),
724 .hw.init = &(struct clk_init_data){
725 .name = "gsbi12_uart_src",
726 .parent_names = gcc_pxo_pll8,
727 .num_parents = 2,
728 .ops = &clk_rcg_ops,
729 .flags = CLK_SET_PARENT_GATE,
730 },
731 },
732 };
733
734 static struct clk_branch gsbi12_uart_clk = {
735 .halt_reg = 0x2fd4,
736 .halt_bit = 13,
737 .clkr = {
738 .enable_reg = 0x2b34,
739 .enable_mask = BIT(9),
740 .hw.init = &(struct clk_init_data){
741 .name = "gsbi12_uart_clk",
742 .parent_names = (const char *[]){ "gsbi12_uart_src" },
743 .num_parents = 1,
744 .ops = &clk_branch_ops,
745 .flags = CLK_SET_RATE_PARENT,
746 },
747 },
748 };
749
750 static struct freq_tbl clk_tbl_gsbi_qup[] = {
751 { 1100000, P_PXO, 1, 2, 49 },
752 { 5400000, P_PXO, 1, 1, 5 },
753 { 10800000, P_PXO, 1, 2, 5 },
754 { 15060000, P_PLL8, 1, 2, 51 },
755 { 24000000, P_PLL8, 4, 1, 4 },
756 { 25600000, P_PLL8, 1, 1, 15 },
757 { 27000000, P_PXO, 1, 0, 0 },
758 { 48000000, P_PLL8, 4, 1, 2 },
759 { 51200000, P_PLL8, 1, 2, 15 },
760 { }
761 };
762
763 static struct clk_rcg gsbi1_qup_src = {
764 .ns_reg = 0x29cc,
765 .md_reg = 0x29c8,
766 .mn = {
767 .mnctr_en_bit = 8,
768 .mnctr_reset_bit = 7,
769 .mnctr_mode_shift = 5,
770 .n_val_shift = 16,
771 .m_val_shift = 16,
772 .width = 8,
773 },
774 .p = {
775 .pre_div_shift = 3,
776 .pre_div_width = 2,
777 },
778 .s = {
779 .src_sel_shift = 0,
780 .parent_map = gcc_pxo_pll8_map,
781 },
782 .freq_tbl = clk_tbl_gsbi_qup,
783 .clkr = {
784 .enable_reg = 0x29cc,
785 .enable_mask = BIT(11),
786 .hw.init = &(struct clk_init_data){
787 .name = "gsbi1_qup_src",
788 .parent_names = gcc_pxo_pll8,
789 .num_parents = 2,
790 .ops = &clk_rcg_ops,
791 .flags = CLK_SET_PARENT_GATE,
792 },
793 },
794 };
795
796 static struct clk_branch gsbi1_qup_clk = {
797 .halt_reg = 0x2fcc,
798 .halt_bit = 9,
799 .clkr = {
800 .enable_reg = 0x29cc,
801 .enable_mask = BIT(9),
802 .hw.init = &(struct clk_init_data){
803 .name = "gsbi1_qup_clk",
804 .parent_names = (const char *[]){ "gsbi1_qup_src" },
805 .num_parents = 1,
806 .ops = &clk_branch_ops,
807 .flags = CLK_SET_RATE_PARENT,
808 },
809 },
810 };
811
812 static struct clk_rcg gsbi2_qup_src = {
813 .ns_reg = 0x29ec,
814 .md_reg = 0x29e8,
815 .mn = {
816 .mnctr_en_bit = 8,
817 .mnctr_reset_bit = 7,
818 .mnctr_mode_shift = 5,
819 .n_val_shift = 16,
820 .m_val_shift = 16,
821 .width = 8,
822 },
823 .p = {
824 .pre_div_shift = 3,
825 .pre_div_width = 2,
826 },
827 .s = {
828 .src_sel_shift = 0,
829 .parent_map = gcc_pxo_pll8_map,
830 },
831 .freq_tbl = clk_tbl_gsbi_qup,
832 .clkr = {
833 .enable_reg = 0x29ec,
834 .enable_mask = BIT(11),
835 .hw.init = &(struct clk_init_data){
836 .name = "gsbi2_qup_src",
837 .parent_names = gcc_pxo_pll8,
838 .num_parents = 2,
839 .ops = &clk_rcg_ops,
840 .flags = CLK_SET_PARENT_GATE,
841 },
842 },
843 };
844
845 static struct clk_branch gsbi2_qup_clk = {
846 .halt_reg = 0x2fcc,
847 .halt_bit = 4,
848 .clkr = {
849 .enable_reg = 0x29ec,
850 .enable_mask = BIT(9),
851 .hw.init = &(struct clk_init_data){
852 .name = "gsbi2_qup_clk",
853 .parent_names = (const char *[]){ "gsbi2_qup_src" },
854 .num_parents = 1,
855 .ops = &clk_branch_ops,
856 .flags = CLK_SET_RATE_PARENT,
857 },
858 },
859 };
860
861 static struct clk_rcg gsbi3_qup_src = {
862 .ns_reg = 0x2a0c,
863 .md_reg = 0x2a08,
864 .mn = {
865 .mnctr_en_bit = 8,
866 .mnctr_reset_bit = 7,
867 .mnctr_mode_shift = 5,
868 .n_val_shift = 16,
869 .m_val_shift = 16,
870 .width = 8,
871 },
872 .p = {
873 .pre_div_shift = 3,
874 .pre_div_width = 2,
875 },
876 .s = {
877 .src_sel_shift = 0,
878 .parent_map = gcc_pxo_pll8_map,
879 },
880 .freq_tbl = clk_tbl_gsbi_qup,
881 .clkr = {
882 .enable_reg = 0x2a0c,
883 .enable_mask = BIT(11),
884 .hw.init = &(struct clk_init_data){
885 .name = "gsbi3_qup_src",
886 .parent_names = gcc_pxo_pll8,
887 .num_parents = 2,
888 .ops = &clk_rcg_ops,
889 .flags = CLK_SET_PARENT_GATE,
890 },
891 },
892 };
893
894 static struct clk_branch gsbi3_qup_clk = {
895 .halt_reg = 0x2fcc,
896 .halt_bit = 0,
897 .clkr = {
898 .enable_reg = 0x2a0c,
899 .enable_mask = BIT(9),
900 .hw.init = &(struct clk_init_data){
901 .name = "gsbi3_qup_clk",
902 .parent_names = (const char *[]){ "gsbi3_qup_src" },
903 .num_parents = 1,
904 .ops = &clk_branch_ops,
905 .flags = CLK_SET_RATE_PARENT,
906 },
907 },
908 };
909
910 static struct clk_rcg gsbi4_qup_src = {
911 .ns_reg = 0x2a2c,
912 .md_reg = 0x2a28,
913 .mn = {
914 .mnctr_en_bit = 8,
915 .mnctr_reset_bit = 7,
916 .mnctr_mode_shift = 5,
917 .n_val_shift = 16,
918 .m_val_shift = 16,
919 .width = 8,
920 },
921 .p = {
922 .pre_div_shift = 3,
923 .pre_div_width = 2,
924 },
925 .s = {
926 .src_sel_shift = 0,
927 .parent_map = gcc_pxo_pll8_map,
928 },
929 .freq_tbl = clk_tbl_gsbi_qup,
930 .clkr = {
931 .enable_reg = 0x2a2c,
932 .enable_mask = BIT(11),
933 .hw.init = &(struct clk_init_data){
934 .name = "gsbi4_qup_src",
935 .parent_names = gcc_pxo_pll8,
936 .num_parents = 2,
937 .ops = &clk_rcg_ops,
938 .flags = CLK_SET_PARENT_GATE,
939 },
940 },
941 };
942
943 static struct clk_branch gsbi4_qup_clk = {
944 .halt_reg = 0x2fd0,
945 .halt_bit = 24,
946 .clkr = {
947 .enable_reg = 0x2a2c,
948 .enable_mask = BIT(9),
949 .hw.init = &(struct clk_init_data){
950 .name = "gsbi4_qup_clk",
951 .parent_names = (const char *[]){ "gsbi4_qup_src" },
952 .num_parents = 1,
953 .ops = &clk_branch_ops,
954 .flags = CLK_SET_RATE_PARENT,
955 },
956 },
957 };
958
959 static struct clk_rcg gsbi5_qup_src = {
960 .ns_reg = 0x2a4c,
961 .md_reg = 0x2a48,
962 .mn = {
963 .mnctr_en_bit = 8,
964 .mnctr_reset_bit = 7,
965 .mnctr_mode_shift = 5,
966 .n_val_shift = 16,
967 .m_val_shift = 16,
968 .width = 8,
969 },
970 .p = {
971 .pre_div_shift = 3,
972 .pre_div_width = 2,
973 },
974 .s = {
975 .src_sel_shift = 0,
976 .parent_map = gcc_pxo_pll8_map,
977 },
978 .freq_tbl = clk_tbl_gsbi_qup,
979 .clkr = {
980 .enable_reg = 0x2a4c,
981 .enable_mask = BIT(11),
982 .hw.init = &(struct clk_init_data){
983 .name = "gsbi5_qup_src",
984 .parent_names = gcc_pxo_pll8,
985 .num_parents = 2,
986 .ops = &clk_rcg_ops,
987 .flags = CLK_SET_PARENT_GATE,
988 },
989 },
990 };
991
992 static struct clk_branch gsbi5_qup_clk = {
993 .halt_reg = 0x2fd0,
994 .halt_bit = 20,
995 .clkr = {
996 .enable_reg = 0x2a4c,
997 .enable_mask = BIT(9),
998 .hw.init = &(struct clk_init_data){
999 .name = "gsbi5_qup_clk",
1000 .parent_names = (const char *[]){ "gsbi5_qup_src" },
1001 .num_parents = 1,
1002 .ops = &clk_branch_ops,
1003 .flags = CLK_SET_RATE_PARENT,
1004 },
1005 },
1006 };
1007
1008 static struct clk_rcg gsbi6_qup_src = {
1009 .ns_reg = 0x2a6c,
1010 .md_reg = 0x2a68,
1011 .mn = {
1012 .mnctr_en_bit = 8,
1013 .mnctr_reset_bit = 7,
1014 .mnctr_mode_shift = 5,
1015 .n_val_shift = 16,
1016 .m_val_shift = 16,
1017 .width = 8,
1018 },
1019 .p = {
1020 .pre_div_shift = 3,
1021 .pre_div_width = 2,
1022 },
1023 .s = {
1024 .src_sel_shift = 0,
1025 .parent_map = gcc_pxo_pll8_map,
1026 },
1027 .freq_tbl = clk_tbl_gsbi_qup,
1028 .clkr = {
1029 .enable_reg = 0x2a6c,
1030 .enable_mask = BIT(11),
1031 .hw.init = &(struct clk_init_data){
1032 .name = "gsbi6_qup_src",
1033 .parent_names = gcc_pxo_pll8,
1034 .num_parents = 2,
1035 .ops = &clk_rcg_ops,
1036 .flags = CLK_SET_PARENT_GATE,
1037 },
1038 },
1039 };
1040
1041 static struct clk_branch gsbi6_qup_clk = {
1042 .halt_reg = 0x2fd0,
1043 .halt_bit = 16,
1044 .clkr = {
1045 .enable_reg = 0x2a6c,
1046 .enable_mask = BIT(9),
1047 .hw.init = &(struct clk_init_data){
1048 .name = "gsbi6_qup_clk",
1049 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1050 .num_parents = 1,
1051 .ops = &clk_branch_ops,
1052 .flags = CLK_SET_RATE_PARENT,
1053 },
1054 },
1055 };
1056
1057 static struct clk_rcg gsbi7_qup_src = {
1058 .ns_reg = 0x2a8c,
1059 .md_reg = 0x2a88,
1060 .mn = {
1061 .mnctr_en_bit = 8,
1062 .mnctr_reset_bit = 7,
1063 .mnctr_mode_shift = 5,
1064 .n_val_shift = 16,
1065 .m_val_shift = 16,
1066 .width = 8,
1067 },
1068 .p = {
1069 .pre_div_shift = 3,
1070 .pre_div_width = 2,
1071 },
1072 .s = {
1073 .src_sel_shift = 0,
1074 .parent_map = gcc_pxo_pll8_map,
1075 },
1076 .freq_tbl = clk_tbl_gsbi_qup,
1077 .clkr = {
1078 .enable_reg = 0x2a8c,
1079 .enable_mask = BIT(11),
1080 .hw.init = &(struct clk_init_data){
1081 .name = "gsbi7_qup_src",
1082 .parent_names = gcc_pxo_pll8,
1083 .num_parents = 2,
1084 .ops = &clk_rcg_ops,
1085 .flags = CLK_SET_PARENT_GATE,
1086 },
1087 },
1088 };
1089
1090 static struct clk_branch gsbi7_qup_clk = {
1091 .halt_reg = 0x2fd0,
1092 .halt_bit = 12,
1093 .clkr = {
1094 .enable_reg = 0x2a8c,
1095 .enable_mask = BIT(9),
1096 .hw.init = &(struct clk_init_data){
1097 .name = "gsbi7_qup_clk",
1098 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1099 .num_parents = 1,
1100 .ops = &clk_branch_ops,
1101 .flags = CLK_SET_RATE_PARENT,
1102 },
1103 },
1104 };
1105
1106 static struct clk_rcg gsbi8_qup_src = {
1107 .ns_reg = 0x2aac,
1108 .md_reg = 0x2aa8,
1109 .mn = {
1110 .mnctr_en_bit = 8,
1111 .mnctr_reset_bit = 7,
1112 .mnctr_mode_shift = 5,
1113 .n_val_shift = 16,
1114 .m_val_shift = 16,
1115 .width = 8,
1116 },
1117 .p = {
1118 .pre_div_shift = 3,
1119 .pre_div_width = 2,
1120 },
1121 .s = {
1122 .src_sel_shift = 0,
1123 .parent_map = gcc_pxo_pll8_map,
1124 },
1125 .freq_tbl = clk_tbl_gsbi_qup,
1126 .clkr = {
1127 .enable_reg = 0x2aac,
1128 .enable_mask = BIT(11),
1129 .hw.init = &(struct clk_init_data){
1130 .name = "gsbi8_qup_src",
1131 .parent_names = gcc_pxo_pll8,
1132 .num_parents = 2,
1133 .ops = &clk_rcg_ops,
1134 .flags = CLK_SET_PARENT_GATE,
1135 },
1136 },
1137 };
1138
1139 static struct clk_branch gsbi8_qup_clk = {
1140 .halt_reg = 0x2fd0,
1141 .halt_bit = 8,
1142 .clkr = {
1143 .enable_reg = 0x2aac,
1144 .enable_mask = BIT(9),
1145 .hw.init = &(struct clk_init_data){
1146 .name = "gsbi8_qup_clk",
1147 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1148 .num_parents = 1,
1149 .ops = &clk_branch_ops,
1150 .flags = CLK_SET_RATE_PARENT,
1151 },
1152 },
1153 };
1154
1155 static struct clk_rcg gsbi9_qup_src = {
1156 .ns_reg = 0x2acc,
1157 .md_reg = 0x2ac8,
1158 .mn = {
1159 .mnctr_en_bit = 8,
1160 .mnctr_reset_bit = 7,
1161 .mnctr_mode_shift = 5,
1162 .n_val_shift = 16,
1163 .m_val_shift = 16,
1164 .width = 8,
1165 },
1166 .p = {
1167 .pre_div_shift = 3,
1168 .pre_div_width = 2,
1169 },
1170 .s = {
1171 .src_sel_shift = 0,
1172 .parent_map = gcc_pxo_pll8_map,
1173 },
1174 .freq_tbl = clk_tbl_gsbi_qup,
1175 .clkr = {
1176 .enable_reg = 0x2acc,
1177 .enable_mask = BIT(11),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "gsbi9_qup_src",
1180 .parent_names = gcc_pxo_pll8,
1181 .num_parents = 2,
1182 .ops = &clk_rcg_ops,
1183 .flags = CLK_SET_PARENT_GATE,
1184 },
1185 },
1186 };
1187
1188 static struct clk_branch gsbi9_qup_clk = {
1189 .halt_reg = 0x2fd0,
1190 .halt_bit = 4,
1191 .clkr = {
1192 .enable_reg = 0x2acc,
1193 .enable_mask = BIT(9),
1194 .hw.init = &(struct clk_init_data){
1195 .name = "gsbi9_qup_clk",
1196 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1197 .num_parents = 1,
1198 .ops = &clk_branch_ops,
1199 .flags = CLK_SET_RATE_PARENT,
1200 },
1201 },
1202 };
1203
1204 static struct clk_rcg gsbi10_qup_src = {
1205 .ns_reg = 0x2aec,
1206 .md_reg = 0x2ae8,
1207 .mn = {
1208 .mnctr_en_bit = 8,
1209 .mnctr_reset_bit = 7,
1210 .mnctr_mode_shift = 5,
1211 .n_val_shift = 16,
1212 .m_val_shift = 16,
1213 .width = 8,
1214 },
1215 .p = {
1216 .pre_div_shift = 3,
1217 .pre_div_width = 2,
1218 },
1219 .s = {
1220 .src_sel_shift = 0,
1221 .parent_map = gcc_pxo_pll8_map,
1222 },
1223 .freq_tbl = clk_tbl_gsbi_qup,
1224 .clkr = {
1225 .enable_reg = 0x2aec,
1226 .enable_mask = BIT(11),
1227 .hw.init = &(struct clk_init_data){
1228 .name = "gsbi10_qup_src",
1229 .parent_names = gcc_pxo_pll8,
1230 .num_parents = 2,
1231 .ops = &clk_rcg_ops,
1232 .flags = CLK_SET_PARENT_GATE,
1233 },
1234 },
1235 };
1236
1237 static struct clk_branch gsbi10_qup_clk = {
1238 .halt_reg = 0x2fd0,
1239 .halt_bit = 0,
1240 .clkr = {
1241 .enable_reg = 0x2aec,
1242 .enable_mask = BIT(9),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "gsbi10_qup_clk",
1245 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1246 .num_parents = 1,
1247 .ops = &clk_branch_ops,
1248 .flags = CLK_SET_RATE_PARENT,
1249 },
1250 },
1251 };
1252
1253 static struct clk_rcg gsbi11_qup_src = {
1254 .ns_reg = 0x2b0c,
1255 .md_reg = 0x2b08,
1256 .mn = {
1257 .mnctr_en_bit = 8,
1258 .mnctr_reset_bit = 7,
1259 .mnctr_mode_shift = 5,
1260 .n_val_shift = 16,
1261 .m_val_shift = 16,
1262 .width = 8,
1263 },
1264 .p = {
1265 .pre_div_shift = 3,
1266 .pre_div_width = 2,
1267 },
1268 .s = {
1269 .src_sel_shift = 0,
1270 .parent_map = gcc_pxo_pll8_map,
1271 },
1272 .freq_tbl = clk_tbl_gsbi_qup,
1273 .clkr = {
1274 .enable_reg = 0x2b0c,
1275 .enable_mask = BIT(11),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gsbi11_qup_src",
1278 .parent_names = gcc_pxo_pll8,
1279 .num_parents = 2,
1280 .ops = &clk_rcg_ops,
1281 .flags = CLK_SET_PARENT_GATE,
1282 },
1283 },
1284 };
1285
1286 static struct clk_branch gsbi11_qup_clk = {
1287 .halt_reg = 0x2fd4,
1288 .halt_bit = 15,
1289 .clkr = {
1290 .enable_reg = 0x2b0c,
1291 .enable_mask = BIT(9),
1292 .hw.init = &(struct clk_init_data){
1293 .name = "gsbi11_qup_clk",
1294 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1295 .num_parents = 1,
1296 .ops = &clk_branch_ops,
1297 .flags = CLK_SET_RATE_PARENT,
1298 },
1299 },
1300 };
1301
1302 static struct clk_rcg gsbi12_qup_src = {
1303 .ns_reg = 0x2b2c,
1304 .md_reg = 0x2b28,
1305 .mn = {
1306 .mnctr_en_bit = 8,
1307 .mnctr_reset_bit = 7,
1308 .mnctr_mode_shift = 5,
1309 .n_val_shift = 16,
1310 .m_val_shift = 16,
1311 .width = 8,
1312 },
1313 .p = {
1314 .pre_div_shift = 3,
1315 .pre_div_width = 2,
1316 },
1317 .s = {
1318 .src_sel_shift = 0,
1319 .parent_map = gcc_pxo_pll8_map,
1320 },
1321 .freq_tbl = clk_tbl_gsbi_qup,
1322 .clkr = {
1323 .enable_reg = 0x2b2c,
1324 .enable_mask = BIT(11),
1325 .hw.init = &(struct clk_init_data){
1326 .name = "gsbi12_qup_src",
1327 .parent_names = gcc_pxo_pll8,
1328 .num_parents = 2,
1329 .ops = &clk_rcg_ops,
1330 .flags = CLK_SET_PARENT_GATE,
1331 },
1332 },
1333 };
1334
1335 static struct clk_branch gsbi12_qup_clk = {
1336 .halt_reg = 0x2fd4,
1337 .halt_bit = 11,
1338 .clkr = {
1339 .enable_reg = 0x2b2c,
1340 .enable_mask = BIT(9),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gsbi12_qup_clk",
1343 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1344 .num_parents = 1,
1345 .ops = &clk_branch_ops,
1346 .flags = CLK_SET_RATE_PARENT,
1347 },
1348 },
1349 };
1350
1351 static const struct freq_tbl clk_tbl_gp[] = {
1352 { 9600000, P_CXO, 2, 0, 0 },
1353 { 13500000, P_PXO, 2, 0, 0 },
1354 { 19200000, P_CXO, 1, 0, 0 },
1355 { 27000000, P_PXO, 1, 0, 0 },
1356 { 64000000, P_PLL8, 2, 1, 3 },
1357 { 76800000, P_PLL8, 1, 1, 5 },
1358 { 96000000, P_PLL8, 4, 0, 0 },
1359 { 128000000, P_PLL8, 3, 0, 0 },
1360 { 192000000, P_PLL8, 2, 0, 0 },
1361 { }
1362 };
1363
1364 static struct clk_rcg gp0_src = {
1365 .ns_reg = 0x2d24,
1366 .md_reg = 0x2d00,
1367 .mn = {
1368 .mnctr_en_bit = 8,
1369 .mnctr_reset_bit = 7,
1370 .mnctr_mode_shift = 5,
1371 .n_val_shift = 16,
1372 .m_val_shift = 16,
1373 .width = 8,
1374 },
1375 .p = {
1376 .pre_div_shift = 3,
1377 .pre_div_width = 2,
1378 },
1379 .s = {
1380 .src_sel_shift = 0,
1381 .parent_map = gcc_pxo_pll8_cxo_map,
1382 },
1383 .freq_tbl = clk_tbl_gp,
1384 .clkr = {
1385 .enable_reg = 0x2d24,
1386 .enable_mask = BIT(11),
1387 .hw.init = &(struct clk_init_data){
1388 .name = "gp0_src",
1389 .parent_names = gcc_pxo_pll8_cxo,
1390 .num_parents = 3,
1391 .ops = &clk_rcg_ops,
1392 .flags = CLK_SET_PARENT_GATE,
1393 },
1394 }
1395 };
1396
1397 static struct clk_branch gp0_clk = {
1398 .halt_reg = 0x2fd8,
1399 .halt_bit = 7,
1400 .clkr = {
1401 .enable_reg = 0x2d24,
1402 .enable_mask = BIT(9),
1403 .hw.init = &(struct clk_init_data){
1404 .name = "gp0_clk",
1405 .parent_names = (const char *[]){ "gp0_src" },
1406 .num_parents = 1,
1407 .ops = &clk_branch_ops,
1408 .flags = CLK_SET_RATE_PARENT,
1409 },
1410 },
1411 };
1412
1413 static struct clk_rcg gp1_src = {
1414 .ns_reg = 0x2d44,
1415 .md_reg = 0x2d40,
1416 .mn = {
1417 .mnctr_en_bit = 8,
1418 .mnctr_reset_bit = 7,
1419 .mnctr_mode_shift = 5,
1420 .n_val_shift = 16,
1421 .m_val_shift = 16,
1422 .width = 8,
1423 },
1424 .p = {
1425 .pre_div_shift = 3,
1426 .pre_div_width = 2,
1427 },
1428 .s = {
1429 .src_sel_shift = 0,
1430 .parent_map = gcc_pxo_pll8_cxo_map,
1431 },
1432 .freq_tbl = clk_tbl_gp,
1433 .clkr = {
1434 .enable_reg = 0x2d44,
1435 .enable_mask = BIT(11),
1436 .hw.init = &(struct clk_init_data){
1437 .name = "gp1_src",
1438 .parent_names = gcc_pxo_pll8_cxo,
1439 .num_parents = 3,
1440 .ops = &clk_rcg_ops,
1441 .flags = CLK_SET_RATE_GATE,
1442 },
1443 }
1444 };
1445
1446 static struct clk_branch gp1_clk = {
1447 .halt_reg = 0x2fd8,
1448 .halt_bit = 6,
1449 .clkr = {
1450 .enable_reg = 0x2d44,
1451 .enable_mask = BIT(9),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "gp1_clk",
1454 .parent_names = (const char *[]){ "gp1_src" },
1455 .num_parents = 1,
1456 .ops = &clk_branch_ops,
1457 .flags = CLK_SET_RATE_PARENT,
1458 },
1459 },
1460 };
1461
1462 static struct clk_rcg gp2_src = {
1463 .ns_reg = 0x2d64,
1464 .md_reg = 0x2d60,
1465 .mn = {
1466 .mnctr_en_bit = 8,
1467 .mnctr_reset_bit = 7,
1468 .mnctr_mode_shift = 5,
1469 .n_val_shift = 16,
1470 .m_val_shift = 16,
1471 .width = 8,
1472 },
1473 .p = {
1474 .pre_div_shift = 3,
1475 .pre_div_width = 2,
1476 },
1477 .s = {
1478 .src_sel_shift = 0,
1479 .parent_map = gcc_pxo_pll8_cxo_map,
1480 },
1481 .freq_tbl = clk_tbl_gp,
1482 .clkr = {
1483 .enable_reg = 0x2d64,
1484 .enable_mask = BIT(11),
1485 .hw.init = &(struct clk_init_data){
1486 .name = "gp2_src",
1487 .parent_names = gcc_pxo_pll8_cxo,
1488 .num_parents = 3,
1489 .ops = &clk_rcg_ops,
1490 .flags = CLK_SET_RATE_GATE,
1491 },
1492 }
1493 };
1494
1495 static struct clk_branch gp2_clk = {
1496 .halt_reg = 0x2fd8,
1497 .halt_bit = 5,
1498 .clkr = {
1499 .enable_reg = 0x2d64,
1500 .enable_mask = BIT(9),
1501 .hw.init = &(struct clk_init_data){
1502 .name = "gp2_clk",
1503 .parent_names = (const char *[]){ "gp2_src" },
1504 .num_parents = 1,
1505 .ops = &clk_branch_ops,
1506 .flags = CLK_SET_RATE_PARENT,
1507 },
1508 },
1509 };
1510
1511 static struct clk_branch pmem_clk = {
1512 .hwcg_reg = 0x25a0,
1513 .hwcg_bit = 6,
1514 .halt_reg = 0x2fc8,
1515 .halt_bit = 20,
1516 .clkr = {
1517 .enable_reg = 0x25a0,
1518 .enable_mask = BIT(4),
1519 .hw.init = &(struct clk_init_data){
1520 .name = "pmem_clk",
1521 .ops = &clk_branch_ops,
1522 .flags = CLK_IS_ROOT,
1523 },
1524 },
1525 };
1526
1527 static struct clk_rcg prng_src = {
1528 .ns_reg = 0x2e80,
1529 .p = {
1530 .pre_div_shift = 3,
1531 .pre_div_width = 4,
1532 },
1533 .s = {
1534 .src_sel_shift = 0,
1535 .parent_map = gcc_pxo_pll8_map,
1536 },
1537 .clkr = {
1538 .hw.init = &(struct clk_init_data){
1539 .name = "prng_src",
1540 .parent_names = gcc_pxo_pll8,
1541 .num_parents = 2,
1542 .ops = &clk_rcg_ops,
1543 },
1544 },
1545 };
1546
1547 static struct clk_branch prng_clk = {
1548 .halt_reg = 0x2fd8,
1549 .halt_check = BRANCH_HALT_VOTED,
1550 .halt_bit = 10,
1551 .clkr = {
1552 .enable_reg = 0x3080,
1553 .enable_mask = BIT(10),
1554 .hw.init = &(struct clk_init_data){
1555 .name = "prng_clk",
1556 .parent_names = (const char *[]){ "prng_src" },
1557 .num_parents = 1,
1558 .ops = &clk_branch_ops,
1559 },
1560 },
1561 };
1562
1563 static const struct freq_tbl clk_tbl_sdc[] = {
1564 { 144000, P_PXO, 3, 2, 125 },
1565 { 400000, P_PLL8, 4, 1, 240 },
1566 { 16000000, P_PLL8, 4, 1, 6 },
1567 { 17070000, P_PLL8, 1, 2, 45 },
1568 { 20210000, P_PLL8, 1, 1, 19 },
1569 { 24000000, P_PLL8, 4, 1, 4 },
1570 { 48000000, P_PLL8, 4, 1, 2 },
1571 { 64000000, P_PLL8, 3, 1, 2 },
1572 { 96000000, P_PLL8, 4, 0, 0 },
1573 { 192000000, P_PLL8, 2, 0, 0 },
1574 { }
1575 };
1576
1577 static struct clk_rcg sdc1_src = {
1578 .ns_reg = 0x282c,
1579 .md_reg = 0x2828,
1580 .mn = {
1581 .mnctr_en_bit = 8,
1582 .mnctr_reset_bit = 7,
1583 .mnctr_mode_shift = 5,
1584 .n_val_shift = 16,
1585 .m_val_shift = 16,
1586 .width = 8,
1587 },
1588 .p = {
1589 .pre_div_shift = 3,
1590 .pre_div_width = 2,
1591 },
1592 .s = {
1593 .src_sel_shift = 0,
1594 .parent_map = gcc_pxo_pll8_map,
1595 },
1596 .freq_tbl = clk_tbl_sdc,
1597 .clkr = {
1598 .enable_reg = 0x282c,
1599 .enable_mask = BIT(11),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "sdc1_src",
1602 .parent_names = gcc_pxo_pll8,
1603 .num_parents = 2,
1604 .ops = &clk_rcg_ops,
1605 .flags = CLK_SET_RATE_GATE,
1606 },
1607 }
1608 };
1609
1610 static struct clk_branch sdc1_clk = {
1611 .halt_reg = 0x2fc8,
1612 .halt_bit = 6,
1613 .clkr = {
1614 .enable_reg = 0x282c,
1615 .enable_mask = BIT(9),
1616 .hw.init = &(struct clk_init_data){
1617 .name = "sdc1_clk",
1618 .parent_names = (const char *[]){ "sdc1_src" },
1619 .num_parents = 1,
1620 .ops = &clk_branch_ops,
1621 .flags = CLK_SET_RATE_PARENT,
1622 },
1623 },
1624 };
1625
1626 static struct clk_rcg sdc2_src = {
1627 .ns_reg = 0x284c,
1628 .md_reg = 0x2848,
1629 .mn = {
1630 .mnctr_en_bit = 8,
1631 .mnctr_reset_bit = 7,
1632 .mnctr_mode_shift = 5,
1633 .n_val_shift = 16,
1634 .m_val_shift = 16,
1635 .width = 8,
1636 },
1637 .p = {
1638 .pre_div_shift = 3,
1639 .pre_div_width = 2,
1640 },
1641 .s = {
1642 .src_sel_shift = 0,
1643 .parent_map = gcc_pxo_pll8_map,
1644 },
1645 .freq_tbl = clk_tbl_sdc,
1646 .clkr = {
1647 .enable_reg = 0x284c,
1648 .enable_mask = BIT(11),
1649 .hw.init = &(struct clk_init_data){
1650 .name = "sdc2_src",
1651 .parent_names = gcc_pxo_pll8,
1652 .num_parents = 2,
1653 .ops = &clk_rcg_ops,
1654 .flags = CLK_SET_RATE_GATE,
1655 },
1656 }
1657 };
1658
1659 static struct clk_branch sdc2_clk = {
1660 .halt_reg = 0x2fc8,
1661 .halt_bit = 5,
1662 .clkr = {
1663 .enable_reg = 0x284c,
1664 .enable_mask = BIT(9),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "sdc2_clk",
1667 .parent_names = (const char *[]){ "sdc2_src" },
1668 .num_parents = 1,
1669 .ops = &clk_branch_ops,
1670 .flags = CLK_SET_RATE_PARENT,
1671 },
1672 },
1673 };
1674
1675 static struct clk_rcg sdc3_src = {
1676 .ns_reg = 0x286c,
1677 .md_reg = 0x2868,
1678 .mn = {
1679 .mnctr_en_bit = 8,
1680 .mnctr_reset_bit = 7,
1681 .mnctr_mode_shift = 5,
1682 .n_val_shift = 16,
1683 .m_val_shift = 16,
1684 .width = 8,
1685 },
1686 .p = {
1687 .pre_div_shift = 3,
1688 .pre_div_width = 2,
1689 },
1690 .s = {
1691 .src_sel_shift = 0,
1692 .parent_map = gcc_pxo_pll8_map,
1693 },
1694 .freq_tbl = clk_tbl_sdc,
1695 .clkr = {
1696 .enable_reg = 0x286c,
1697 .enable_mask = BIT(11),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "sdc3_src",
1700 .parent_names = gcc_pxo_pll8,
1701 .num_parents = 2,
1702 .ops = &clk_rcg_ops,
1703 .flags = CLK_SET_RATE_GATE,
1704 },
1705 }
1706 };
1707
1708 static struct clk_branch sdc3_clk = {
1709 .halt_reg = 0x2fc8,
1710 .halt_bit = 4,
1711 .clkr = {
1712 .enable_reg = 0x286c,
1713 .enable_mask = BIT(9),
1714 .hw.init = &(struct clk_init_data){
1715 .name = "sdc3_clk",
1716 .parent_names = (const char *[]){ "sdc3_src" },
1717 .num_parents = 1,
1718 .ops = &clk_branch_ops,
1719 .flags = CLK_SET_RATE_PARENT,
1720 },
1721 },
1722 };
1723
1724 static struct clk_rcg sdc4_src = {
1725 .ns_reg = 0x288c,
1726 .md_reg = 0x2888,
1727 .mn = {
1728 .mnctr_en_bit = 8,
1729 .mnctr_reset_bit = 7,
1730 .mnctr_mode_shift = 5,
1731 .n_val_shift = 16,
1732 .m_val_shift = 16,
1733 .width = 8,
1734 },
1735 .p = {
1736 .pre_div_shift = 3,
1737 .pre_div_width = 2,
1738 },
1739 .s = {
1740 .src_sel_shift = 0,
1741 .parent_map = gcc_pxo_pll8_map,
1742 },
1743 .freq_tbl = clk_tbl_sdc,
1744 .clkr = {
1745 .enable_reg = 0x288c,
1746 .enable_mask = BIT(11),
1747 .hw.init = &(struct clk_init_data){
1748 .name = "sdc4_src",
1749 .parent_names = gcc_pxo_pll8,
1750 .num_parents = 2,
1751 .ops = &clk_rcg_ops,
1752 .flags = CLK_SET_RATE_GATE,
1753 },
1754 }
1755 };
1756
1757 static struct clk_branch sdc4_clk = {
1758 .halt_reg = 0x2fc8,
1759 .halt_bit = 3,
1760 .clkr = {
1761 .enable_reg = 0x288c,
1762 .enable_mask = BIT(9),
1763 .hw.init = &(struct clk_init_data){
1764 .name = "sdc4_clk",
1765 .parent_names = (const char *[]){ "sdc4_src" },
1766 .num_parents = 1,
1767 .ops = &clk_branch_ops,
1768 .flags = CLK_SET_RATE_PARENT,
1769 },
1770 },
1771 };
1772
1773 static struct clk_rcg sdc5_src = {
1774 .ns_reg = 0x28ac,
1775 .md_reg = 0x28a8,
1776 .mn = {
1777 .mnctr_en_bit = 8,
1778 .mnctr_reset_bit = 7,
1779 .mnctr_mode_shift = 5,
1780 .n_val_shift = 16,
1781 .m_val_shift = 16,
1782 .width = 8,
1783 },
1784 .p = {
1785 .pre_div_shift = 3,
1786 .pre_div_width = 2,
1787 },
1788 .s = {
1789 .src_sel_shift = 0,
1790 .parent_map = gcc_pxo_pll8_map,
1791 },
1792 .freq_tbl = clk_tbl_sdc,
1793 .clkr = {
1794 .enable_reg = 0x28ac,
1795 .enable_mask = BIT(11),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "sdc5_src",
1798 .parent_names = gcc_pxo_pll8,
1799 .num_parents = 2,
1800 .ops = &clk_rcg_ops,
1801 .flags = CLK_SET_RATE_GATE,
1802 },
1803 }
1804 };
1805
1806 static struct clk_branch sdc5_clk = {
1807 .halt_reg = 0x2fc8,
1808 .halt_bit = 2,
1809 .clkr = {
1810 .enable_reg = 0x28ac,
1811 .enable_mask = BIT(9),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "sdc5_clk",
1814 .parent_names = (const char *[]){ "sdc5_src" },
1815 .num_parents = 1,
1816 .ops = &clk_branch_ops,
1817 .flags = CLK_SET_RATE_PARENT,
1818 },
1819 },
1820 };
1821
1822 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1823 { 105000, P_PXO, 1, 1, 256 },
1824 { }
1825 };
1826
1827 static struct clk_rcg tsif_ref_src = {
1828 .ns_reg = 0x2710,
1829 .md_reg = 0x270c,
1830 .mn = {
1831 .mnctr_en_bit = 8,
1832 .mnctr_reset_bit = 7,
1833 .mnctr_mode_shift = 5,
1834 .n_val_shift = 16,
1835 .m_val_shift = 16,
1836 .width = 16,
1837 },
1838 .p = {
1839 .pre_div_shift = 3,
1840 .pre_div_width = 2,
1841 },
1842 .s = {
1843 .src_sel_shift = 0,
1844 .parent_map = gcc_pxo_pll8_map,
1845 },
1846 .freq_tbl = clk_tbl_tsif_ref,
1847 .clkr = {
1848 .enable_reg = 0x2710,
1849 .enable_mask = BIT(11),
1850 .hw.init = &(struct clk_init_data){
1851 .name = "tsif_ref_src",
1852 .parent_names = gcc_pxo_pll8,
1853 .num_parents = 2,
1854 .ops = &clk_rcg_ops,
1855 .flags = CLK_SET_RATE_GATE,
1856 },
1857 }
1858 };
1859
1860 static struct clk_branch tsif_ref_clk = {
1861 .halt_reg = 0x2fd4,
1862 .halt_bit = 5,
1863 .clkr = {
1864 .enable_reg = 0x2710,
1865 .enable_mask = BIT(9),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "tsif_ref_clk",
1868 .parent_names = (const char *[]){ "tsif_ref_src" },
1869 .num_parents = 1,
1870 .ops = &clk_branch_ops,
1871 .flags = CLK_SET_RATE_PARENT,
1872 },
1873 },
1874 };
1875
1876 static const struct freq_tbl clk_tbl_usb[] = {
1877 { 60000000, P_PLL8, 1, 5, 32 },
1878 { }
1879 };
1880
1881 static struct clk_rcg usb_hs1_xcvr_src = {
1882 .ns_reg = 0x290c,
1883 .md_reg = 0x2908,
1884 .mn = {
1885 .mnctr_en_bit = 8,
1886 .mnctr_reset_bit = 7,
1887 .mnctr_mode_shift = 5,
1888 .n_val_shift = 16,
1889 .m_val_shift = 16,
1890 .width = 8,
1891 },
1892 .p = {
1893 .pre_div_shift = 3,
1894 .pre_div_width = 2,
1895 },
1896 .s = {
1897 .src_sel_shift = 0,
1898 .parent_map = gcc_pxo_pll8_map,
1899 },
1900 .freq_tbl = clk_tbl_usb,
1901 .clkr = {
1902 .enable_reg = 0x290c,
1903 .enable_mask = BIT(11),
1904 .hw.init = &(struct clk_init_data){
1905 .name = "usb_hs1_xcvr_src",
1906 .parent_names = gcc_pxo_pll8,
1907 .num_parents = 2,
1908 .ops = &clk_rcg_ops,
1909 .flags = CLK_SET_RATE_GATE,
1910 },
1911 }
1912 };
1913
1914 static struct clk_branch usb_hs1_xcvr_clk = {
1915 .halt_reg = 0x2fc8,
1916 .halt_bit = 0,
1917 .clkr = {
1918 .enable_reg = 0x290c,
1919 .enable_mask = BIT(9),
1920 .hw.init = &(struct clk_init_data){
1921 .name = "usb_hs1_xcvr_clk",
1922 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1923 .num_parents = 1,
1924 .ops = &clk_branch_ops,
1925 .flags = CLK_SET_RATE_PARENT,
1926 },
1927 },
1928 };
1929
1930 static struct clk_rcg usb_hsic_xcvr_fs_src = {
1931 .ns_reg = 0x2928,
1932 .md_reg = 0x2924,
1933 .mn = {
1934 .mnctr_en_bit = 8,
1935 .mnctr_reset_bit = 7,
1936 .mnctr_mode_shift = 5,
1937 .n_val_shift = 16,
1938 .m_val_shift = 16,
1939 .width = 8,
1940 },
1941 .p = {
1942 .pre_div_shift = 3,
1943 .pre_div_width = 2,
1944 },
1945 .s = {
1946 .src_sel_shift = 0,
1947 .parent_map = gcc_pxo_pll8_map,
1948 },
1949 .freq_tbl = clk_tbl_usb,
1950 .clkr = {
1951 .enable_reg = 0x2928,
1952 .enable_mask = BIT(11),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "usb_hsic_xcvr_fs_src",
1955 .parent_names = gcc_pxo_pll8,
1956 .num_parents = 2,
1957 .ops = &clk_rcg_ops,
1958 .flags = CLK_SET_RATE_GATE,
1959 },
1960 }
1961 };
1962
1963 static const char *usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
1964
1965 static struct clk_branch usb_hsic_xcvr_fs_clk = {
1966 .halt_reg = 0x2fc8,
1967 .halt_bit = 2,
1968 .clkr = {
1969 .enable_reg = 0x2928,
1970 .enable_mask = BIT(9),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "usb_hsic_xcvr_fs_clk",
1973 .parent_names = usb_hsic_xcvr_fs_src_p,
1974 .num_parents = 1,
1975 .ops = &clk_branch_ops,
1976 .flags = CLK_SET_RATE_PARENT,
1977 },
1978 },
1979 };
1980
1981 static struct clk_branch usb_hsic_system_clk = {
1982 .halt_reg = 0x2fcc,
1983 .halt_bit = 24,
1984 .clkr = {
1985 .enable_reg = 0x292c,
1986 .enable_mask = BIT(4),
1987 .hw.init = &(struct clk_init_data){
1988 .parent_names = usb_hsic_xcvr_fs_src_p,
1989 .num_parents = 1,
1990 .name = "usb_hsic_system_clk",
1991 .ops = &clk_branch_ops,
1992 .flags = CLK_SET_RATE_PARENT,
1993 },
1994 },
1995 };
1996
1997 static struct clk_branch usb_hsic_hsic_clk = {
1998 .halt_reg = 0x2fcc,
1999 .halt_bit = 19,
2000 .clkr = {
2001 .enable_reg = 0x2b44,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .parent_names = (const char *[]){ "pll14_vote" },
2005 .num_parents = 1,
2006 .name = "usb_hsic_hsic_clk",
2007 .ops = &clk_branch_ops,
2008 },
2009 },
2010 };
2011
2012 static struct clk_branch usb_hsic_hsio_cal_clk = {
2013 .halt_reg = 0x2fcc,
2014 .halt_bit = 23,
2015 .clkr = {
2016 .enable_reg = 0x2b48,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "usb_hsic_hsio_cal_clk",
2020 .ops = &clk_branch_ops,
2021 .flags = CLK_IS_ROOT,
2022 },
2023 },
2024 };
2025
2026 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2027 .ns_reg = 0x2968,
2028 .md_reg = 0x2964,
2029 .mn = {
2030 .mnctr_en_bit = 8,
2031 .mnctr_reset_bit = 7,
2032 .mnctr_mode_shift = 5,
2033 .n_val_shift = 16,
2034 .m_val_shift = 16,
2035 .width = 8,
2036 },
2037 .p = {
2038 .pre_div_shift = 3,
2039 .pre_div_width = 2,
2040 },
2041 .s = {
2042 .src_sel_shift = 0,
2043 .parent_map = gcc_pxo_pll8_map,
2044 },
2045 .freq_tbl = clk_tbl_usb,
2046 .clkr = {
2047 .enable_reg = 0x2968,
2048 .enable_mask = BIT(11),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "usb_fs1_xcvr_fs_src",
2051 .parent_names = gcc_pxo_pll8,
2052 .num_parents = 2,
2053 .ops = &clk_rcg_ops,
2054 .flags = CLK_SET_RATE_GATE,
2055 },
2056 }
2057 };
2058
2059 static const char *usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2060
2061 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2062 .halt_reg = 0x2fcc,
2063 .halt_bit = 15,
2064 .clkr = {
2065 .enable_reg = 0x2968,
2066 .enable_mask = BIT(9),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "usb_fs1_xcvr_fs_clk",
2069 .parent_names = usb_fs1_xcvr_fs_src_p,
2070 .num_parents = 1,
2071 .ops = &clk_branch_ops,
2072 .flags = CLK_SET_RATE_PARENT,
2073 },
2074 },
2075 };
2076
2077 static struct clk_branch usb_fs1_system_clk = {
2078 .halt_reg = 0x2fcc,
2079 .halt_bit = 16,
2080 .clkr = {
2081 .enable_reg = 0x296c,
2082 .enable_mask = BIT(4),
2083 .hw.init = &(struct clk_init_data){
2084 .parent_names = usb_fs1_xcvr_fs_src_p,
2085 .num_parents = 1,
2086 .name = "usb_fs1_system_clk",
2087 .ops = &clk_branch_ops,
2088 .flags = CLK_SET_RATE_PARENT,
2089 },
2090 },
2091 };
2092
2093 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2094 .ns_reg = 0x2988,
2095 .md_reg = 0x2984,
2096 .mn = {
2097 .mnctr_en_bit = 8,
2098 .mnctr_reset_bit = 7,
2099 .mnctr_mode_shift = 5,
2100 .n_val_shift = 16,
2101 .m_val_shift = 16,
2102 .width = 8,
2103 },
2104 .p = {
2105 .pre_div_shift = 3,
2106 .pre_div_width = 2,
2107 },
2108 .s = {
2109 .src_sel_shift = 0,
2110 .parent_map = gcc_pxo_pll8_map,
2111 },
2112 .freq_tbl = clk_tbl_usb,
2113 .clkr = {
2114 .enable_reg = 0x2988,
2115 .enable_mask = BIT(11),
2116 .hw.init = &(struct clk_init_data){
2117 .name = "usb_fs2_xcvr_fs_src",
2118 .parent_names = gcc_pxo_pll8,
2119 .num_parents = 2,
2120 .ops = &clk_rcg_ops,
2121 .flags = CLK_SET_RATE_GATE,
2122 },
2123 }
2124 };
2125
2126 static const char *usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2127
2128 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2129 .halt_reg = 0x2fcc,
2130 .halt_bit = 12,
2131 .clkr = {
2132 .enable_reg = 0x2988,
2133 .enable_mask = BIT(9),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "usb_fs2_xcvr_fs_clk",
2136 .parent_names = usb_fs2_xcvr_fs_src_p,
2137 .num_parents = 1,
2138 .ops = &clk_branch_ops,
2139 .flags = CLK_SET_RATE_PARENT,
2140 },
2141 },
2142 };
2143
2144 static struct clk_branch usb_fs2_system_clk = {
2145 .halt_reg = 0x2fcc,
2146 .halt_bit = 13,
2147 .clkr = {
2148 .enable_reg = 0x298c,
2149 .enable_mask = BIT(4),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "usb_fs2_system_clk",
2152 .parent_names = usb_fs2_xcvr_fs_src_p,
2153 .num_parents = 1,
2154 .ops = &clk_branch_ops,
2155 .flags = CLK_SET_RATE_PARENT,
2156 },
2157 },
2158 };
2159
2160 static struct clk_branch ce1_core_clk = {
2161 .hwcg_reg = 0x2724,
2162 .hwcg_bit = 6,
2163 .halt_reg = 0x2fd4,
2164 .halt_bit = 27,
2165 .clkr = {
2166 .enable_reg = 0x2724,
2167 .enable_mask = BIT(4),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "ce1_core_clk",
2170 .ops = &clk_branch_ops,
2171 .flags = CLK_IS_ROOT,
2172 },
2173 },
2174 };
2175
2176 static struct clk_branch ce1_h_clk = {
2177 .halt_reg = 0x2fd4,
2178 .halt_bit = 1,
2179 .clkr = {
2180 .enable_reg = 0x2720,
2181 .enable_mask = BIT(4),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "ce1_h_clk",
2184 .ops = &clk_branch_ops,
2185 .flags = CLK_IS_ROOT,
2186 },
2187 },
2188 };
2189
2190 static struct clk_branch dma_bam_h_clk = {
2191 .hwcg_reg = 0x25c0,
2192 .hwcg_bit = 6,
2193 .halt_reg = 0x2fc8,
2194 .halt_bit = 12,
2195 .clkr = {
2196 .enable_reg = 0x25c0,
2197 .enable_mask = BIT(4),
2198 .hw.init = &(struct clk_init_data){
2199 .name = "dma_bam_h_clk",
2200 .ops = &clk_branch_ops,
2201 .flags = CLK_IS_ROOT,
2202 },
2203 },
2204 };
2205
2206 static struct clk_branch gsbi1_h_clk = {
2207 .hwcg_reg = 0x29c0,
2208 .hwcg_bit = 6,
2209 .halt_reg = 0x2fcc,
2210 .halt_bit = 11,
2211 .clkr = {
2212 .enable_reg = 0x29c0,
2213 .enable_mask = BIT(4),
2214 .hw.init = &(struct clk_init_data){
2215 .name = "gsbi1_h_clk",
2216 .ops = &clk_branch_ops,
2217 .flags = CLK_IS_ROOT,
2218 },
2219 },
2220 };
2221
2222 static struct clk_branch gsbi2_h_clk = {
2223 .hwcg_reg = 0x29e0,
2224 .hwcg_bit = 6,
2225 .halt_reg = 0x2fcc,
2226 .halt_bit = 7,
2227 .clkr = {
2228 .enable_reg = 0x29e0,
2229 .enable_mask = BIT(4),
2230 .hw.init = &(struct clk_init_data){
2231 .name = "gsbi2_h_clk",
2232 .ops = &clk_branch_ops,
2233 .flags = CLK_IS_ROOT,
2234 },
2235 },
2236 };
2237
2238 static struct clk_branch gsbi3_h_clk = {
2239 .hwcg_reg = 0x2a00,
2240 .hwcg_bit = 6,
2241 .halt_reg = 0x2fcc,
2242 .halt_bit = 3,
2243 .clkr = {
2244 .enable_reg = 0x2a00,
2245 .enable_mask = BIT(4),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "gsbi3_h_clk",
2248 .ops = &clk_branch_ops,
2249 .flags = CLK_IS_ROOT,
2250 },
2251 },
2252 };
2253
2254 static struct clk_branch gsbi4_h_clk = {
2255 .hwcg_reg = 0x2a20,
2256 .hwcg_bit = 6,
2257 .halt_reg = 0x2fd0,
2258 .halt_bit = 27,
2259 .clkr = {
2260 .enable_reg = 0x2a20,
2261 .enable_mask = BIT(4),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "gsbi4_h_clk",
2264 .ops = &clk_branch_ops,
2265 .flags = CLK_IS_ROOT,
2266 },
2267 },
2268 };
2269
2270 static struct clk_branch gsbi5_h_clk = {
2271 .hwcg_reg = 0x2a40,
2272 .hwcg_bit = 6,
2273 .halt_reg = 0x2fd0,
2274 .halt_bit = 23,
2275 .clkr = {
2276 .enable_reg = 0x2a40,
2277 .enable_mask = BIT(4),
2278 .hw.init = &(struct clk_init_data){
2279 .name = "gsbi5_h_clk",
2280 .ops = &clk_branch_ops,
2281 .flags = CLK_IS_ROOT,
2282 },
2283 },
2284 };
2285
2286 static struct clk_branch gsbi6_h_clk = {
2287 .hwcg_reg = 0x2a60,
2288 .hwcg_bit = 6,
2289 .halt_reg = 0x2fd0,
2290 .halt_bit = 19,
2291 .clkr = {
2292 .enable_reg = 0x2a60,
2293 .enable_mask = BIT(4),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gsbi6_h_clk",
2296 .ops = &clk_branch_ops,
2297 .flags = CLK_IS_ROOT,
2298 },
2299 },
2300 };
2301
2302 static struct clk_branch gsbi7_h_clk = {
2303 .hwcg_reg = 0x2a80,
2304 .hwcg_bit = 6,
2305 .halt_reg = 0x2fd0,
2306 .halt_bit = 15,
2307 .clkr = {
2308 .enable_reg = 0x2a80,
2309 .enable_mask = BIT(4),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "gsbi7_h_clk",
2312 .ops = &clk_branch_ops,
2313 .flags = CLK_IS_ROOT,
2314 },
2315 },
2316 };
2317
2318 static struct clk_branch gsbi8_h_clk = {
2319 .hwcg_reg = 0x2aa0,
2320 .hwcg_bit = 6,
2321 .halt_reg = 0x2fd0,
2322 .halt_bit = 11,
2323 .clkr = {
2324 .enable_reg = 0x2aa0,
2325 .enable_mask = BIT(4),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "gsbi8_h_clk",
2328 .ops = &clk_branch_ops,
2329 .flags = CLK_IS_ROOT,
2330 },
2331 },
2332 };
2333
2334 static struct clk_branch gsbi9_h_clk = {
2335 .hwcg_reg = 0x2ac0,
2336 .hwcg_bit = 6,
2337 .halt_reg = 0x2fd0,
2338 .halt_bit = 7,
2339 .clkr = {
2340 .enable_reg = 0x2ac0,
2341 .enable_mask = BIT(4),
2342 .hw.init = &(struct clk_init_data){
2343 .name = "gsbi9_h_clk",
2344 .ops = &clk_branch_ops,
2345 .flags = CLK_IS_ROOT,
2346 },
2347 },
2348 };
2349
2350 static struct clk_branch gsbi10_h_clk = {
2351 .hwcg_reg = 0x2ae0,
2352 .hwcg_bit = 6,
2353 .halt_reg = 0x2fd0,
2354 .halt_bit = 3,
2355 .clkr = {
2356 .enable_reg = 0x2ae0,
2357 .enable_mask = BIT(4),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "gsbi10_h_clk",
2360 .ops = &clk_branch_ops,
2361 .flags = CLK_IS_ROOT,
2362 },
2363 },
2364 };
2365
2366 static struct clk_branch gsbi11_h_clk = {
2367 .hwcg_reg = 0x2b00,
2368 .hwcg_bit = 6,
2369 .halt_reg = 0x2fd4,
2370 .halt_bit = 18,
2371 .clkr = {
2372 .enable_reg = 0x2b00,
2373 .enable_mask = BIT(4),
2374 .hw.init = &(struct clk_init_data){
2375 .name = "gsbi11_h_clk",
2376 .ops = &clk_branch_ops,
2377 .flags = CLK_IS_ROOT,
2378 },
2379 },
2380 };
2381
2382 static struct clk_branch gsbi12_h_clk = {
2383 .hwcg_reg = 0x2b20,
2384 .hwcg_bit = 6,
2385 .halt_reg = 0x2fd4,
2386 .halt_bit = 14,
2387 .clkr = {
2388 .enable_reg = 0x2b20,
2389 .enable_mask = BIT(4),
2390 .hw.init = &(struct clk_init_data){
2391 .name = "gsbi12_h_clk",
2392 .ops = &clk_branch_ops,
2393 .flags = CLK_IS_ROOT,
2394 },
2395 },
2396 };
2397
2398 static struct clk_branch tsif_h_clk = {
2399 .hwcg_reg = 0x2700,
2400 .hwcg_bit = 6,
2401 .halt_reg = 0x2fd4,
2402 .halt_bit = 7,
2403 .clkr = {
2404 .enable_reg = 0x2700,
2405 .enable_mask = BIT(4),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "tsif_h_clk",
2408 .ops = &clk_branch_ops,
2409 .flags = CLK_IS_ROOT,
2410 },
2411 },
2412 };
2413
2414 static struct clk_branch usb_fs1_h_clk = {
2415 .halt_reg = 0x2fcc,
2416 .halt_bit = 17,
2417 .clkr = {
2418 .enable_reg = 0x2960,
2419 .enable_mask = BIT(4),
2420 .hw.init = &(struct clk_init_data){
2421 .name = "usb_fs1_h_clk",
2422 .ops = &clk_branch_ops,
2423 .flags = CLK_IS_ROOT,
2424 },
2425 },
2426 };
2427
2428 static struct clk_branch usb_fs2_h_clk = {
2429 .halt_reg = 0x2fcc,
2430 .halt_bit = 14,
2431 .clkr = {
2432 .enable_reg = 0x2980,
2433 .enable_mask = BIT(4),
2434 .hw.init = &(struct clk_init_data){
2435 .name = "usb_fs2_h_clk",
2436 .ops = &clk_branch_ops,
2437 .flags = CLK_IS_ROOT,
2438 },
2439 },
2440 };
2441
2442 static struct clk_branch usb_hs1_h_clk = {
2443 .hwcg_reg = 0x2900,
2444 .hwcg_bit = 6,
2445 .halt_reg = 0x2fc8,
2446 .halt_bit = 1,
2447 .clkr = {
2448 .enable_reg = 0x2900,
2449 .enable_mask = BIT(4),
2450 .hw.init = &(struct clk_init_data){
2451 .name = "usb_hs1_h_clk",
2452 .ops = &clk_branch_ops,
2453 .flags = CLK_IS_ROOT,
2454 },
2455 },
2456 };
2457
2458 static struct clk_branch usb_hsic_h_clk = {
2459 .halt_reg = 0x2fcc,
2460 .halt_bit = 28,
2461 .clkr = {
2462 .enable_reg = 0x2920,
2463 .enable_mask = BIT(4),
2464 .hw.init = &(struct clk_init_data){
2465 .name = "usb_hsic_h_clk",
2466 .ops = &clk_branch_ops,
2467 .flags = CLK_IS_ROOT,
2468 },
2469 },
2470 };
2471
2472 static struct clk_branch sdc1_h_clk = {
2473 .hwcg_reg = 0x2820,
2474 .hwcg_bit = 6,
2475 .halt_reg = 0x2fc8,
2476 .halt_bit = 11,
2477 .clkr = {
2478 .enable_reg = 0x2820,
2479 .enable_mask = BIT(4),
2480 .hw.init = &(struct clk_init_data){
2481 .name = "sdc1_h_clk",
2482 .ops = &clk_branch_ops,
2483 .flags = CLK_IS_ROOT,
2484 },
2485 },
2486 };
2487
2488 static struct clk_branch sdc2_h_clk = {
2489 .hwcg_reg = 0x2840,
2490 .hwcg_bit = 6,
2491 .halt_reg = 0x2fc8,
2492 .halt_bit = 10,
2493 .clkr = {
2494 .enable_reg = 0x2840,
2495 .enable_mask = BIT(4),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "sdc2_h_clk",
2498 .ops = &clk_branch_ops,
2499 .flags = CLK_IS_ROOT,
2500 },
2501 },
2502 };
2503
2504 static struct clk_branch sdc3_h_clk = {
2505 .hwcg_reg = 0x2860,
2506 .hwcg_bit = 6,
2507 .halt_reg = 0x2fc8,
2508 .halt_bit = 9,
2509 .clkr = {
2510 .enable_reg = 0x2860,
2511 .enable_mask = BIT(4),
2512 .hw.init = &(struct clk_init_data){
2513 .name = "sdc3_h_clk",
2514 .ops = &clk_branch_ops,
2515 .flags = CLK_IS_ROOT,
2516 },
2517 },
2518 };
2519
2520 static struct clk_branch sdc4_h_clk = {
2521 .hwcg_reg = 0x2880,
2522 .hwcg_bit = 6,
2523 .halt_reg = 0x2fc8,
2524 .halt_bit = 8,
2525 .clkr = {
2526 .enable_reg = 0x2880,
2527 .enable_mask = BIT(4),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "sdc4_h_clk",
2530 .ops = &clk_branch_ops,
2531 .flags = CLK_IS_ROOT,
2532 },
2533 },
2534 };
2535
2536 static struct clk_branch sdc5_h_clk = {
2537 .hwcg_reg = 0x28a0,
2538 .hwcg_bit = 6,
2539 .halt_reg = 0x2fc8,
2540 .halt_bit = 7,
2541 .clkr = {
2542 .enable_reg = 0x28a0,
2543 .enable_mask = BIT(4),
2544 .hw.init = &(struct clk_init_data){
2545 .name = "sdc5_h_clk",
2546 .ops = &clk_branch_ops,
2547 .flags = CLK_IS_ROOT,
2548 },
2549 },
2550 };
2551
2552 static struct clk_branch adm0_clk = {
2553 .halt_reg = 0x2fdc,
2554 .halt_check = BRANCH_HALT_VOTED,
2555 .halt_bit = 14,
2556 .clkr = {
2557 .enable_reg = 0x3080,
2558 .enable_mask = BIT(2),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "adm0_clk",
2561 .ops = &clk_branch_ops,
2562 .flags = CLK_IS_ROOT,
2563 },
2564 },
2565 };
2566
2567 static struct clk_branch adm0_pbus_clk = {
2568 .hwcg_reg = 0x2208,
2569 .hwcg_bit = 6,
2570 .halt_reg = 0x2fdc,
2571 .halt_check = BRANCH_HALT_VOTED,
2572 .halt_bit = 13,
2573 .clkr = {
2574 .enable_reg = 0x3080,
2575 .enable_mask = BIT(3),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "adm0_pbus_clk",
2578 .ops = &clk_branch_ops,
2579 .flags = CLK_IS_ROOT,
2580 },
2581 },
2582 };
2583
2584 static struct clk_branch pmic_arb0_h_clk = {
2585 .halt_reg = 0x2fd8,
2586 .halt_check = BRANCH_HALT_VOTED,
2587 .halt_bit = 22,
2588 .clkr = {
2589 .enable_reg = 0x3080,
2590 .enable_mask = BIT(8),
2591 .hw.init = &(struct clk_init_data){
2592 .name = "pmic_arb0_h_clk",
2593 .ops = &clk_branch_ops,
2594 .flags = CLK_IS_ROOT,
2595 },
2596 },
2597 };
2598
2599 static struct clk_branch pmic_arb1_h_clk = {
2600 .halt_reg = 0x2fd8,
2601 .halt_check = BRANCH_HALT_VOTED,
2602 .halt_bit = 21,
2603 .clkr = {
2604 .enable_reg = 0x3080,
2605 .enable_mask = BIT(9),
2606 .hw.init = &(struct clk_init_data){
2607 .name = "pmic_arb1_h_clk",
2608 .ops = &clk_branch_ops,
2609 .flags = CLK_IS_ROOT,
2610 },
2611 },
2612 };
2613
2614 static struct clk_branch pmic_ssbi2_clk = {
2615 .halt_reg = 0x2fd8,
2616 .halt_check = BRANCH_HALT_VOTED,
2617 .halt_bit = 23,
2618 .clkr = {
2619 .enable_reg = 0x3080,
2620 .enable_mask = BIT(7),
2621 .hw.init = &(struct clk_init_data){
2622 .name = "pmic_ssbi2_clk",
2623 .ops = &clk_branch_ops,
2624 .flags = CLK_IS_ROOT,
2625 },
2626 },
2627 };
2628
2629 static struct clk_branch rpm_msg_ram_h_clk = {
2630 .hwcg_reg = 0x27e0,
2631 .hwcg_bit = 6,
2632 .halt_reg = 0x2fd8,
2633 .halt_check = BRANCH_HALT_VOTED,
2634 .halt_bit = 12,
2635 .clkr = {
2636 .enable_reg = 0x3080,
2637 .enable_mask = BIT(6),
2638 .hw.init = &(struct clk_init_data){
2639 .name = "rpm_msg_ram_h_clk",
2640 .ops = &clk_branch_ops,
2641 .flags = CLK_IS_ROOT,
2642 },
2643 },
2644 };
2645
2646 static struct clk_regmap *gcc_msm8960_clks[] = {
2647 [PLL3] = &pll3.clkr,
2648 [PLL8] = &pll8.clkr,
2649 [PLL8_VOTE] = &pll8_vote,
2650 [PLL14] = &pll14.clkr,
2651 [PLL14_VOTE] = &pll14_vote,
2652 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2653 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2654 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2655 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2656 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2657 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2658 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2659 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2660 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2661 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2662 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2663 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2664 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2665 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2666 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2667 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2668 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2669 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2670 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2671 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2672 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2673 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2674 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2675 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2676 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2677 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2678 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2679 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2680 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2681 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2682 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2683 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2684 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2685 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2686 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2687 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2688 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2689 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2690 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2691 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2692 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2693 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2694 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2695 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2696 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2697 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2698 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2699 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2700 [GP0_SRC] = &gp0_src.clkr,
2701 [GP0_CLK] = &gp0_clk.clkr,
2702 [GP1_SRC] = &gp1_src.clkr,
2703 [GP1_CLK] = &gp1_clk.clkr,
2704 [GP2_SRC] = &gp2_src.clkr,
2705 [GP2_CLK] = &gp2_clk.clkr,
2706 [PMEM_A_CLK] = &pmem_clk.clkr,
2707 [PRNG_SRC] = &prng_src.clkr,
2708 [PRNG_CLK] = &prng_clk.clkr,
2709 [SDC1_SRC] = &sdc1_src.clkr,
2710 [SDC1_CLK] = &sdc1_clk.clkr,
2711 [SDC2_SRC] = &sdc2_src.clkr,
2712 [SDC2_CLK] = &sdc2_clk.clkr,
2713 [SDC3_SRC] = &sdc3_src.clkr,
2714 [SDC3_CLK] = &sdc3_clk.clkr,
2715 [SDC4_SRC] = &sdc4_src.clkr,
2716 [SDC4_CLK] = &sdc4_clk.clkr,
2717 [SDC5_SRC] = &sdc5_src.clkr,
2718 [SDC5_CLK] = &sdc5_clk.clkr,
2719 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2720 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2721 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2722 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2723 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
2724 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
2725 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
2726 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
2727 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
2728 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2729 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2730 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2731 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2732 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2733 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2734 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
2735 [CE1_H_CLK] = &ce1_h_clk.clkr,
2736 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2737 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2738 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2739 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2740 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2741 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2742 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2743 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2744 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2745 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2746 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2747 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2748 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2749 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2750 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2751 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2752 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2753 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
2754 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2755 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2756 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2757 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2758 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2759 [ADM0_CLK] = &adm0_clk.clkr,
2760 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2761 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2762 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2763 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2764 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2765 };
2766
2767 static const struct qcom_reset_map gcc_msm8960_resets[] = {
2768 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
2769 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
2770 [QDSS_STM_RESET] = { 0x2060, 6 },
2771 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2772 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2773 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2774 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2775 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
2776 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2777 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2778 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2779 [ADM0_C2_RESET] = { 0x220c, 4},
2780 [ADM0_C1_RESET] = { 0x220c, 3},
2781 [ADM0_C0_RESET] = { 0x220c, 2},
2782 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2783 [ADM0_RESET] = { 0x220c },
2784 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2785 [QDSS_POR_RESET] = { 0x2260, 4 },
2786 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2787 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2788 [QDSS_AXI_RESET] = { 0x2260, 1 },
2789 [QDSS_DBG_RESET] = { 0x2260 },
2790 [PCIE_A_RESET] = { 0x22c0, 7 },
2791 [PCIE_AUX_RESET] = { 0x22c8, 7 },
2792 [PCIE_H_RESET] = { 0x22d0, 7 },
2793 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
2794 [SFAB_PCIE_S_RESET] = { 0x22d4 },
2795 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
2796 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
2797 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
2798 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2799 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2800 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2801 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2802 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2803 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2804 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2805 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2806 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2807 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2808 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2809 [PPSS_PROC_RESET] = { 0x2594, 1 },
2810 [PPSS_RESET] = { 0x2594},
2811 [DMA_BAM_RESET] = { 0x25c0, 7 },
2812 [SIC_TIC_RESET] = { 0x2600, 7 },
2813 [SLIMBUS_H_RESET] = { 0x2620, 7 },
2814 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2815 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2816 [TSIF_H_RESET] = { 0x2700, 7 },
2817 [CE1_H_RESET] = { 0x2720, 7 },
2818 [CE1_CORE_RESET] = { 0x2724, 7 },
2819 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2820 [CE2_H_RESET] = { 0x2740, 7 },
2821 [CE2_CORE_RESET] = { 0x2744, 7 },
2822 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2823 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2824 [RPM_PROC_RESET] = { 0x27c0, 7 },
2825 [PMIC_SSBI2_RESET] = { 0x270c, 12 },
2826 [SDC1_RESET] = { 0x2830 },
2827 [SDC2_RESET] = { 0x2850 },
2828 [SDC3_RESET] = { 0x2870 },
2829 [SDC4_RESET] = { 0x2890 },
2830 [SDC5_RESET] = { 0x28b0 },
2831 [DFAB_A2_RESET] = { 0x28c0, 7 },
2832 [USB_HS1_RESET] = { 0x2910 },
2833 [USB_HSIC_RESET] = { 0x2934 },
2834 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2835 [USB_FS1_RESET] = { 0x2974 },
2836 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2837 [USB_FS2_RESET] = { 0x2994 },
2838 [GSBI1_RESET] = { 0x29dc },
2839 [GSBI2_RESET] = { 0x29fc },
2840 [GSBI3_RESET] = { 0x2a1c },
2841 [GSBI4_RESET] = { 0x2a3c },
2842 [GSBI5_RESET] = { 0x2a5c },
2843 [GSBI6_RESET] = { 0x2a7c },
2844 [GSBI7_RESET] = { 0x2a9c },
2845 [GSBI8_RESET] = { 0x2abc },
2846 [GSBI9_RESET] = { 0x2adc },
2847 [GSBI10_RESET] = { 0x2afc },
2848 [GSBI11_RESET] = { 0x2b1c },
2849 [GSBI12_RESET] = { 0x2b3c },
2850 [SPDM_RESET] = { 0x2b6c },
2851 [TLMM_H_RESET] = { 0x2ba0, 7 },
2852 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2853 [MSS_SLP_RESET] = { 0x2c60, 7 },
2854 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
2855 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
2856 [MSS_RESET] = { 0x2c64 },
2857 [SATA_H_RESET] = { 0x2c80, 7 },
2858 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
2859 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
2860 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
2861 [TSSC_RESET] = { 0x2ca0, 7 },
2862 [PDM_RESET] = { 0x2cc0, 12 },
2863 [MPM_H_RESET] = { 0x2da0, 7 },
2864 [MPM_RESET] = { 0x2da4 },
2865 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2866 [PRNG_RESET] = { 0x2e80, 12 },
2867 [RIVA_RESET] = { 0x35e0 },
2868 };
2869
2870 static const struct regmap_config gcc_msm8960_regmap_config = {
2871 .reg_bits = 32,
2872 .reg_stride = 4,
2873 .val_bits = 32,
2874 .max_register = 0x3660,
2875 .fast_io = true,
2876 };
2877
2878 static const struct of_device_id gcc_msm8960_match_table[] = {
2879 { .compatible = "qcom,gcc-msm8960" },
2880 { }
2881 };
2882 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
2883
2884 struct qcom_cc {
2885 struct qcom_reset_controller reset;
2886 struct clk_onecell_data data;
2887 struct clk *clks[];
2888 };
2889
2890 static int gcc_msm8960_probe(struct platform_device *pdev)
2891 {
2892 void __iomem *base;
2893 struct resource *res;
2894 int i, ret;
2895 struct device *dev = &pdev->dev;
2896 struct clk *clk;
2897 struct clk_onecell_data *data;
2898 struct clk **clks;
2899 struct regmap *regmap;
2900 size_t num_clks;
2901 struct qcom_reset_controller *reset;
2902 struct qcom_cc *cc;
2903
2904 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2905 base = devm_ioremap_resource(dev, res);
2906 if (IS_ERR(base))
2907 return PTR_ERR(base);
2908
2909 regmap = devm_regmap_init_mmio(dev, base, &gcc_msm8960_regmap_config);
2910 if (IS_ERR(regmap))
2911 return PTR_ERR(regmap);
2912
2913 num_clks = ARRAY_SIZE(gcc_msm8960_clks);
2914 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2915 GFP_KERNEL);
2916 if (!cc)
2917 return -ENOMEM;
2918
2919 clks = cc->clks;
2920 data = &cc->data;
2921 data->clks = clks;
2922 data->clk_num = num_clks;
2923
2924 /* Temporary until RPM clocks supported */
2925 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000);
2926 if (IS_ERR(clk))
2927 return PTR_ERR(clk);
2928
2929 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000);
2930 if (IS_ERR(clk))
2931 return PTR_ERR(clk);
2932
2933 for (i = 0; i < num_clks; i++) {
2934 if (!gcc_msm8960_clks[i])
2935 continue;
2936 clk = devm_clk_register_regmap(dev, gcc_msm8960_clks[i]);
2937 if (IS_ERR(clk))
2938 return PTR_ERR(clk);
2939 clks[i] = clk;
2940 }
2941
2942 ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2943 if (ret)
2944 return ret;
2945
2946 reset = &cc->reset;
2947 reset->rcdev.of_node = dev->of_node;
2948 reset->rcdev.ops = &qcom_reset_ops,
2949 reset->rcdev.owner = THIS_MODULE,
2950 reset->rcdev.nr_resets = ARRAY_SIZE(gcc_msm8960_resets),
2951 reset->regmap = regmap;
2952 reset->reset_map = gcc_msm8960_resets,
2953 platform_set_drvdata(pdev, &reset->rcdev);
2954
2955 ret = reset_controller_register(&reset->rcdev);
2956 if (ret)
2957 of_clk_del_provider(dev->of_node);
2958
2959 return ret;
2960 }
2961
2962 static int gcc_msm8960_remove(struct platform_device *pdev)
2963 {
2964 of_clk_del_provider(pdev->dev.of_node);
2965 reset_controller_unregister(platform_get_drvdata(pdev));
2966 return 0;
2967 }
2968
2969 static struct platform_driver gcc_msm8960_driver = {
2970 .probe = gcc_msm8960_probe,
2971 .remove = gcc_msm8960_remove,
2972 .driver = {
2973 .name = "gcc-msm8960",
2974 .owner = THIS_MODULE,
2975 .of_match_table = gcc_msm8960_match_table,
2976 },
2977 };
2978
2979 static int __init gcc_msm8960_init(void)
2980 {
2981 return platform_driver_register(&gcc_msm8960_driver);
2982 }
2983 core_initcall(gcc_msm8960_init);
2984
2985 static void __exit gcc_msm8960_exit(void)
2986 {
2987 platform_driver_unregister(&gcc_msm8960_driver);
2988 }
2989 module_exit(gcc_msm8960_exit);
2990
2991 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
2992 MODULE_LICENSE("GPL v2");
2993 MODULE_ALIAS("platform:gcc-msm8960");
Linux with added FPC-III support