drivers/clk/tegra/clk-tegra-periph.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/clkdev.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/delay.h>
  24 #include <linux/export.h>
  25 #include <linux/clk/tegra.h>
  26
  27 #include "clk.h"
  28 #include "clk-id.h"
  29
  30 #define CLK_SOURCE_I2S0 0x1d8
  31 #define CLK_SOURCE_I2S1 0x100
  32 #define CLK_SOURCE_I2S2 0x104
  33 #define CLK_SOURCE_NDFLASH 0x160
  34 #define CLK_SOURCE_I2S3 0x3bc
  35 #define CLK_SOURCE_I2S4 0x3c0
  36 #define CLK_SOURCE_SPDIF_OUT 0x108
  37 #define CLK_SOURCE_SPDIF_IN 0x10c
  38 #define CLK_SOURCE_PWM 0x110
  39 #define CLK_SOURCE_ADX 0x638
  40 #define CLK_SOURCE_ADX1 0x670
  41 #define CLK_SOURCE_AMX 0x63c
  42 #define CLK_SOURCE_AMX1 0x674
  43 #define CLK_SOURCE_HDA 0x428
  44 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
  45 #define CLK_SOURCE_SBC1 0x134
  46 #define CLK_SOURCE_SBC2 0x118
  47 #define CLK_SOURCE_SBC3 0x11c
  48 #define CLK_SOURCE_SBC4 0x1b4
  49 #define CLK_SOURCE_SBC5 0x3c8
  50 #define CLK_SOURCE_SBC6 0x3cc
  51 #define CLK_SOURCE_SATA_OOB 0x420
  52 #define CLK_SOURCE_SATA 0x424
  53 #define CLK_SOURCE_NDSPEED 0x3f8
  54 #define CLK_SOURCE_VFIR 0x168
  55 #define CLK_SOURCE_SDMMC1 0x150
  56 #define CLK_SOURCE_SDMMC2 0x154
  57 #define CLK_SOURCE_SDMMC3 0x1bc
  58 #define CLK_SOURCE_SDMMC4 0x164
  59 #define CLK_SOURCE_CVE 0x140
  60 #define CLK_SOURCE_TVO 0x188
  61 #define CLK_SOURCE_TVDAC 0x194
  62 #define CLK_SOURCE_VDE 0x1c8
  63 #define CLK_SOURCE_CSITE 0x1d4
  64 #define CLK_SOURCE_LA 0x1f8
  65 #define CLK_SOURCE_TRACE 0x634
  66 #define CLK_SOURCE_OWR 0x1cc
  67 #define CLK_SOURCE_NOR 0x1d0
  68 #define CLK_SOURCE_MIPI 0x174
  69 #define CLK_SOURCE_I2C1 0x124
  70 #define CLK_SOURCE_I2C2 0x198
  71 #define CLK_SOURCE_I2C3 0x1b8
  72 #define CLK_SOURCE_I2C4 0x3c4
  73 #define CLK_SOURCE_I2C5 0x128
  74 #define CLK_SOURCE_I2C6 0x65c
  75 #define CLK_SOURCE_UARTA 0x178
  76 #define CLK_SOURCE_UARTB 0x17c
  77 #define CLK_SOURCE_UARTC 0x1a0
  78 #define CLK_SOURCE_UARTD 0x1c0
  79 #define CLK_SOURCE_UARTE 0x1c4
  80 #define CLK_SOURCE_3D 0x158
  81 #define CLK_SOURCE_2D 0x15c
  82 #define CLK_SOURCE_MPE 0x170
  83 #define CLK_SOURCE_UARTE 0x1c4
  84 #define CLK_SOURCE_VI_SENSOR 0x1a8
  85 #define CLK_SOURCE_VI 0x148
  86 #define CLK_SOURCE_EPP 0x16c
  87 #define CLK_SOURCE_MSENC 0x1f0
  88 #define CLK_SOURCE_TSEC 0x1f4
  89 #define CLK_SOURCE_HOST1X 0x180
  90 #define CLK_SOURCE_HDMI 0x18c
  91 #define CLK_SOURCE_DISP1 0x138
  92 #define CLK_SOURCE_DISP2 0x13c
  93 #define CLK_SOURCE_CILAB 0x614
  94 #define CLK_SOURCE_CILCD 0x618
  95 #define CLK_SOURCE_CILE 0x61c
  96 #define CLK_SOURCE_DSIALP 0x620
  97 #define CLK_SOURCE_DSIBLP 0x624
  98 #define CLK_SOURCE_TSENSOR 0x3b8
  99 #define CLK_SOURCE_D_AUDIO 0x3d0
 100 #define CLK_SOURCE_DAM0 0x3d8
 101 #define CLK_SOURCE_DAM1 0x3dc
 102 #define CLK_SOURCE_DAM2 0x3e0
 103 #define CLK_SOURCE_ACTMON 0x3e8
 104 #define CLK_SOURCE_EXTERN1 0x3ec
 105 #define CLK_SOURCE_EXTERN2 0x3f0
 106 #define CLK_SOURCE_EXTERN3 0x3f4
 107 #define CLK_SOURCE_I2CSLOW 0x3fc
 108 #define CLK_SOURCE_SE 0x42c
 109 #define CLK_SOURCE_MSELECT 0x3b4
 110 #define CLK_SOURCE_DFLL_REF 0x62c
 111 #define CLK_SOURCE_DFLL_SOC 0x630
 112 #define CLK_SOURCE_SOC_THERM 0x644
 113 #define CLK_SOURCE_XUSB_HOST_SRC 0x600
 114 #define CLK_SOURCE_XUSB_FALCON_SRC 0x604
 115 #define CLK_SOURCE_XUSB_FS_SRC 0x608
 116 #define CLK_SOURCE_XUSB_SS_SRC 0x610
 117 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
 118 #define CLK_SOURCE_ISP 0x144
 119 #define CLK_SOURCE_SOR0 0x414
 120 #define CLK_SOURCE_DPAUX 0x418
 121 #define CLK_SOURCE_SATA_OOB 0x420
 122 #define CLK_SOURCE_SATA 0x424
 123 #define CLK_SOURCE_ENTROPY 0x628
 124 #define CLK_SOURCE_VI_SENSOR2 0x658
 125 #define CLK_SOURCE_HDMI_AUDIO 0x668
 126 #define CLK_SOURCE_VIC03 0x678
 127 #define CLK_SOURCE_CLK72MHZ 0x66c
 128
 129 #define MASK(x) (BIT(x) - 1)
 130
 131 #define MUX(_name, _parents, _offset,   \
 132                             _clk_num, _gate_flags, _clk_id)     \
 133         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 134                         30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
 135                         _clk_num,  _gate_flags, _clk_id, _parents##_idx, 0,\
 136                         NULL)
 137
 138 #define MUX_FLAGS(_name, _parents, _offset,\
 139                             _clk_num, _gate_flags, _clk_id, flags)\
 140         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 141                         30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
 142                         _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
 143                         NULL)
 144
 145 #define MUX8(_name, _parents, _offset, \
 146                              _clk_num, _gate_flags, _clk_id)    \
 147         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 148                         29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
 149                         _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
 150                         NULL)
 151
 152 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock)      \
 153         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,     \
 154                               29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
 155                               0, TEGRA_PERIPH_NO_GATE, _clk_id,\
 156                               _parents##_idx, 0, _lock)
 157
 158 #define INT(_name, _parents, _offset,   \
 159                             _clk_num, _gate_flags, _clk_id)     \
 160         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 161                         30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
 162                         TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
 163                         _clk_id, _parents##_idx, 0, NULL)
 164
 165 #define INT_FLAGS(_name, _parents, _offset,\
 166                             _clk_num, _gate_flags, _clk_id, flags)\
 167         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 168                         30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
 169                         TEGRA_DIVIDER_ROUND_UP, _clk_num,  _gate_flags,\
 170                         _clk_id, _parents##_idx, flags, NULL)
 171
 172 #define INT8(_name, _parents, _offset,\
 173                             _clk_num, _gate_flags, _clk_id)     \
 174         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 175                         29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
 176                         TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
 177                         _clk_id, _parents##_idx, 0, NULL)
 178
 179 #define UART(_name, _parents, _offset,\
 180                              _clk_num, _clk_id)                 \
 181         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 182                         30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
 183                         TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
 184                         _parents##_idx, 0, NULL)
 185
 186 #define I2C(_name, _parents, _offset,\
 187                              _clk_num, _clk_id)                 \
 188         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 189                         30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
 190                         _clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
 191
 192 #define XUSB(_name, _parents, _offset, \
 193                              _clk_num, _gate_flags, _clk_id)     \
 194         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
 195                         29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
 196                         TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
 197                         _clk_id, _parents##_idx, 0, NULL)
 198
 199 #define AUDIO(_name, _offset,  _clk_num,\
 200                                  _gate_flags, _clk_id)          \
 201         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk,       \
 202                         _offset, 16, 0xE01F, 0, 0, 8, 1,                \
 203                         TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,  \
 204                         _clk_id, mux_d_audio_clk_idx, 0, NULL)
 205
 206 #define NODIV(_name, _parents, _offset, \
 207                               _mux_shift, _mux_mask, _clk_num, \
 208                               _gate_flags, _clk_id, _lock)              \
 209         TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
 210                         _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
 211                         _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
 212                         _clk_id, _parents##_idx, 0, _lock)
 213
 214 #define GATE(_name, _parent_name,       \
 215                              _clk_num, _gate_flags,  _clk_id, _flags)   \
 216         {                                                               \
 217                 .name = _name,                                          \
 218                 .clk_id = _clk_id,                                      \
 219                 .p.parent_name = _parent_name,                          \
 220                 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0,         \
 221                                 _clk_num, _gate_flags, 0, NULL),        \
 222                 .flags = _flags                                         \
 223         }
 224
 225 #define PLLP_BASE 0xa0
 226 #define PLLP_MISC 0xac
 227 #define PLLP_OUTA 0xa4
 228 #define PLLP_OUTB 0xa8
 229 #define PLLP_OUTC 0x67c
 230
 231 #define PLL_BASE_LOCK BIT(27)
 232 #define PLL_MISC_LOCK_ENABLE 18
 233
 234 static DEFINE_SPINLOCK(PLLP_OUTA_lock);
 235 static DEFINE_SPINLOCK(PLLP_OUTB_lock);
 236 static DEFINE_SPINLOCK(PLLP_OUTC_lock);
 237 static DEFINE_SPINLOCK(sor0_lock);
 238
 239 #define MUX_I2S_SPDIF(_id)                                              \
 240 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
 241                                                            #_id, "pll_p",\
 242                                                            "clk_m"};
 243 MUX_I2S_SPDIF(audio0)
 244 MUX_I2S_SPDIF(audio1)
 245 MUX_I2S_SPDIF(audio2)
 246 MUX_I2S_SPDIF(audio3)
 247 MUX_I2S_SPDIF(audio4)
 248 MUX_I2S_SPDIF(audio)
 249
 250 #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
 251 #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
 252 #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
 253 #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
 254 #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
 255 #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
 256
 257 static const char *mux_pllp_pllc_pllm_clkm[] = {
 258         "pll_p", "pll_c", "pll_m", "clk_m"
 259 };
 260 #define mux_pllp_pllc_pllm_clkm_idx NULL
 261
 262 static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
 263 #define mux_pllp_pllc_pllm_idx NULL
 264
 265 static const char *mux_pllp_pllc_clk32_clkm[] = {
 266         "pll_p", "pll_c", "clk_32k", "clk_m"
 267 };
 268 #define mux_pllp_pllc_clk32_clkm_idx NULL
 269
 270 static const char *mux_plla_pllc_pllp_clkm[] = {
 271         "pll_a_out0", "pll_c", "pll_p", "clk_m"
 272 };
 273 #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
 274
 275 static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
 276         "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
 277 };
 278 static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
 279         [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
 280 };
 281
 282 static const char *mux_pllp_clkm[] = {
 283         "pll_p", "clk_m"
 284 };
 285 static u32 mux_pllp_clkm_idx[] = {
 286         [0] = 0, [1] = 3,
 287 };
 288
 289 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
 290         "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
 291 };
 292 #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
 293
 294 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
 295         "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
 296         "pll_d2_out0", "clk_m"
 297 };
 298 #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
 299
 300 static const char *mux_pllm_pllc_pllp_plla[] = {
 301         "pll_m", "pll_c", "pll_p", "pll_a_out0"
 302 };
 303 #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
 304
 305 static const char *mux_pllp_pllc_clkm[] = {
 306         "pll_p", "pll_c", "pll_m"
 307 };
 308 static u32 mux_pllp_pllc_clkm_idx[] = {
 309         [0] = 0, [1] = 1, [2] = 3,
 310 };
 311
 312 static const char *mux_pllp_pllc_clkm_clk32[] = {
 313         "pll_p", "pll_c", "clk_m", "clk_32k"
 314 };
 315 #define mux_pllp_pllc_clkm_clk32_idx NULL
 316
 317 static const char *mux_plla_clk32_pllp_clkm_plle[] = {
 318         "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
 319 };
 320 #define mux_plla_clk32_pllp_clkm_plle_idx NULL
 321
 322 static const char *mux_clkm_pllp_pllc_pllre[] = {
 323         "clk_m", "pll_p", "pll_c", "pll_re_out"
 324 };
 325 static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
 326         [0] = 0, [1] = 1, [2] = 3, [3] = 5,
 327 };
 328
 329 static const char *mux_clkm_48M_pllp_480M[] = {
 330         "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
 331 };
 332 #define mux_clkm_48M_pllp_480M_idx NULL
 333
 334 static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
 335         "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
 336 };
 337 static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
 338         [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
 339 };
 340
 341 static const char *mux_d_audio_clk[] = {
 342         "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
 343         "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
 344 };
 345 static u32 mux_d_audio_clk_idx[] = {
 346         [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
 347         [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
 348 };
 349
 350 static const char *mux_pllp_plld_pllc_clkm[] = {
 351         "pll_p", "pll_d_out0", "pll_c", "clk_m"
 352 };
 353 #define mux_pllp_plld_pllc_clkm_idx NULL
 354 static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
 355         "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4",
 356 };
 357 static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = {
 358         [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7,
 359 };
 360
 361 static const char *mux_pllp_clkm1[] = {
 362         "pll_p", "clk_m",
 363 };
 364 #define mux_pllp_clkm1_idx NULL
 365
 366 static const char *mux_pllp3_pllc_clkm[] = {
 367         "pll_p_out3", "pll_c", "pll_c2", "clk_m",
 368 };
 369 #define mux_pllp3_pllc_clkm_idx NULL
 370
 371 static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
 372         "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
 373 };
 374 static u32 mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx[] = {
 375         [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
 376 };
 377
 378 static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
 379         "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
 380 };
 381 static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
 382         [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
 383 };
 384
 385 static const char *mux_clkm_plldp_sor0lvds[] = {
 386         "clk_m", "pll_dp", "sor0_lvds",
 387 };
 388 #define mux_clkm_plldp_sor0lvds_idx NULL
 389
 390 static struct tegra_periph_init_data periph_clks[] = {
 391         AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
 392         AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
 393         AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1),
 394         AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2),
 395         I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
 396         I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
 397         I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
 398         I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
 399         I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
 400         INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
 401         INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
 402         INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
 403         INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
 404         INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
 405         INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
 406         INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
 407         INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
 408         INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
 409         INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
 410         INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
 411         INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
 412         INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
 413         INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
 414         INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
 415         INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
 416         INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
 417         INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
 418         INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
 419         MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
 420         MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
 421         MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2),
 422         MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3),
 423         MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
 424         MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
 425         MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
 426         MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
 427         MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
 428         MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
 429         MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
 430         MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
 431         MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
 432         MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1),
 433         MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2),
 434         MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3),
 435         MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4),
 436         MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
 437         MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
 438         MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
 439         MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
 440         MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
 441         MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
 442         MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
 443         MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
 444         MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
 445         MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
 446         MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
 447         MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor),
 448         MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
 449         MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref),
 450         MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc),
 451         MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow),
 452         MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1),
 453         MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2),
 454         MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3),
 455         MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4),
 456         MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5),
 457         MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6),
 458         MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
 459         MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
 460         MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac),
 461         MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
 462         MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
 463         MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
 464         MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
 465         MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
 466         MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
 467         MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
 468         MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
 469         MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
 470         MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
 471         MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
 472         MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
 473         MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
 474         MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
 475         MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
 476         MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
 477         MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1),
 478         MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
 479         MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
 480         MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
 481         MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
 482         MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
 483         MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149,  0, tegra_clk_entropy),
 484         MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
 485         MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
 486         MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
 487         MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
 488         NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
 489         NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
 490         NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
 491         UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
 492         UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
 493         UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
 494         UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
 495         UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte),
 496         XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
 497         XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
 498         XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
 499         XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
 500         XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
 501 };
 502
 503 static struct tegra_periph_init_data gate_clks[] = {
 504         GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
 505         GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0),
 506         GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
 507         GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
 508         GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
 509         GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
 510         GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
 511         GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
 512         GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
 513         GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
 514         GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
 515         GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
 516         GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
 517         GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal, 0),
 518         GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
 519         GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
 520         GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
 521         GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
 522         GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0),
 523         GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
 524         GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
 525         GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
 526         GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
 527         GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
 528         GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
 529         GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
 530         GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia, 0),
 531         GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib, 0),
 532         GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
 533         GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
 534         GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
 535         GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
 536         GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
 537         GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0),
 538         GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
 539 };
 540
 541 struct pll_out_data {
 542         char *div_name;
 543         char *pll_out_name;
 544         u32 offset;
 545         int clk_id;
 546         u8 div_shift;
 547         u8 div_flags;
 548         u8 rst_shift;
 549         spinlock_t *lock;
 550 };
 551
 552 #define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
 553         {\
 554                 .div_name = "pll_p_out" #_num "_div",\
 555                 .pll_out_name = "pll_p_out" #_num,\
 556                 .offset = _offset,\
 557                 .div_shift = _div_shift,\
 558                 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
 559                                         TEGRA_DIVIDER_ROUND_UP,\
 560                 .rst_shift = _rst_shift,\
 561                 .clk_id = tegra_clk_ ## _id,\
 562                 .lock = &_offset ##_lock,\
 563         }
 564
 565 static struct pll_out_data pllp_out_clks[] = {
 566         PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1),
 567         PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2),
 568         PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
 569         PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3),
 570         PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4),
 571         PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5),
 572 };
 573
 574 static void __init periph_clk_init(void __iomem *clk_base,
 575                                 struct tegra_clk *tegra_clks)
 576 {
 577         int i;
 578         struct clk *clk;
 579         struct clk **dt_clk;
 580
 581         for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {
 582                 struct tegra_clk_periph_regs *bank;
 583                 struct tegra_periph_init_data *data;
 584
 585                 data = periph_clks + i;
 586
 587                 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
 588                 if (!dt_clk)
 589                         continue;
 590
 591                 bank = get_reg_bank(data->periph.gate.clk_num);
 592                 if (!bank)
 593                         continue;
 594
 595                 data->periph.gate.regs = bank;
 596                 clk = tegra_clk_register_periph(data->name,
 597                         data->p.parent_names, data->num_parents,
 598                         &data->periph, clk_base, data->offset,
 599                         data->flags);
 600                 *dt_clk = clk;
 601         }
 602 }
 603
 604 static void __init gate_clk_init(void __iomem *clk_base,
 605                                 struct tegra_clk *tegra_clks)
 606 {
 607         int i;
 608         struct clk *clk;
 609         struct clk **dt_clk;
 610
 611         for (i = 0; i < ARRAY_SIZE(gate_clks); i++) {
 612                 struct tegra_periph_init_data *data;
 613
 614                 data = gate_clks + i;
 615
 616                 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
 617                 if (!dt_clk)
 618                         continue;
 619
 620                 clk = tegra_clk_register_periph_gate(data->name,
 621                                 data->p.parent_name, data->periph.gate.flags,
 622                                 clk_base, data->flags,
 623                                 data->periph.gate.clk_num,
 624                                 periph_clk_enb_refcnt);
 625                 *dt_clk = clk;
 626         }
 627 }
 628
 629 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
 630                                 struct tegra_clk *tegra_clks,
 631                                 struct tegra_clk_pll_params *pll_params)
 632 {
 633         struct clk *clk;
 634         struct clk **dt_clk;
 635         int i;
 636
 637         dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
 638         if (dt_clk) {
 639                 /* PLLP */
 640                 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
 641                                         pmc_base, 0, pll_params, NULL);
 642                 clk_register_clkdev(clk, "pll_p", NULL);
 643                 *dt_clk = clk;
 644         }
 645
 646         for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
 647                 struct pll_out_data *data;
 648
 649                 data = pllp_out_clks + i;
 650
 651                 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
 652                 if (!dt_clk)
 653                         continue;
 654
 655                 clk = tegra_clk_register_divider(data->div_name, "pll_p",
 656                                 clk_base + data->offset, 0, data->div_flags,
 657                                 data->div_shift, 8, 1, data->lock);
 658                 clk = tegra_clk_register_pll_out(data->pll_out_name,
 659                                 data->div_name, clk_base + data->offset,
 660                                 data->rst_shift + 1, data->rst_shift,
 661                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
 662                                 data->lock);
 663                 *dt_clk = clk;
 664         }
 665 }
 666
 667 void __init tegra_periph_clk_init(void __iomem *clk_base,
 668                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
 669                         struct tegra_clk_pll_params *pll_params)
 670 {
 671         init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
 672         periph_clk_init(clk_base, tegra_clks);
 673         gate_clk_init(clk_base, tegra_clks);
 674 }