?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / clk / tegra / clk-tegra114.c
blob90d9d25f2228195308f328a9d7c05c1a5bbe5a40
1 /*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/clkdev.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/clk/tegra.h>
26 #include <dt-bindings/clock/tegra114-car.h>
27
28 #include "clk.h"
29 #include "clk-id.h"
30
31 #define RST_DFLL_DVCO 0x2F4
32 #define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
33 #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
34 #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
35
36 /* RST_DFLL_DVCO bitfields */
37 #define DVFS_DFLL_RESET_SHIFT 0
38
39 /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
40 #define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */
41 #define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */
42 #define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */
43 #define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */
44 #define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */
45 #define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */
46
47 /* CPU_FINETRIM_R bitfields */
48 #define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */
49 #define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
50 #define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */
51 #define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
52 #define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */
53 #define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
54 #define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */
55 #define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
56 #define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */
57 #define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
58 #define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */
59 #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
60
61 #define TEGRA114_CLK_PERIPH_BANKS 5
62
63 #define PLLC_BASE 0x80
64 #define PLLC_MISC2 0x88
65 #define PLLC_MISC 0x8c
66 #define PLLC2_BASE 0x4e8
67 #define PLLC2_MISC 0x4ec
68 #define PLLC3_BASE 0x4fc
69 #define PLLC3_MISC 0x500
70 #define PLLM_BASE 0x90
71 #define PLLM_MISC 0x9c
72 #define PLLP_BASE 0xa0
73 #define PLLP_MISC 0xac
74 #define PLLX_BASE 0xe0
75 #define PLLX_MISC 0xe4
76 #define PLLX_MISC2 0x514
77 #define PLLX_MISC3 0x518
78 #define PLLD_BASE 0xd0
79 #define PLLD_MISC 0xdc
80 #define PLLD2_BASE 0x4b8
81 #define PLLD2_MISC 0x4bc
82 #define PLLE_BASE 0xe8
83 #define PLLE_MISC 0xec
84 #define PLLA_BASE 0xb0
85 #define PLLA_MISC 0xbc
86 #define PLLU_BASE 0xc0
87 #define PLLU_MISC 0xcc
88 #define PLLRE_BASE 0x4c4
89 #define PLLRE_MISC 0x4c8
90
91 #define PLL_MISC_LOCK_ENABLE 18
92 #define PLLC_MISC_LOCK_ENABLE 24
93 #define PLLDU_MISC_LOCK_ENABLE 22
94 #define PLLE_MISC_LOCK_ENABLE 9
95 #define PLLRE_MISC_LOCK_ENABLE 30
96
97 #define PLLC_IDDQ_BIT 26
98 #define PLLX_IDDQ_BIT 3
99 #define PLLRE_IDDQ_BIT 16
100
101 #define PLL_BASE_LOCK BIT(27)
102 #define PLLE_MISC_LOCK BIT(11)
103 #define PLLRE_MISC_LOCK BIT(24)
104 #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
105
106 #define PLLE_AUX 0x48c
107 #define PLLC_OUT 0x84
108 #define PLLM_OUT 0x94
109
110 #define OSC_CTRL 0x50
111 #define OSC_CTRL_OSC_FREQ_SHIFT 28
112 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
113
114 #define PLLXC_SW_MAX_P 6
115
116 #define CCLKG_BURST_POLICY 0x368
117
118 #define UTMIP_PLL_CFG2 0x488
119 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
120 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
121 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
122 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
123 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
124
125 #define UTMIP_PLL_CFG1 0x484
126 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
127 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
128 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
129 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
130 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
131 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
132 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
133
134 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
135 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
136 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
137 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
138 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
139 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
140 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
141 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
142 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
143
144 #define CLK_SOURCE_CSITE 0x1d4
145 #define CLK_SOURCE_XUSB_SS_SRC 0x610
146 #define CLK_SOURCE_EMC 0x19c
147
148 /* PLLM override registers */
149 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
150 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
151
152 /* Tegra CPU clock and reset control regs */
153 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
154
155 #ifdef CONFIG_PM_SLEEP
156 static struct cpu_clk_suspend_context {
157 u32 clk_csite_src;
158 u32 cclkg_burst;
159 u32 cclkg_divider;
160 } tegra114_cpu_clk_sctx;
161 #endif
162
163 static void __iomem *clk_base;
164 static void __iomem *pmc_base;
165
166 static DEFINE_SPINLOCK(pll_d_lock);
167 static DEFINE_SPINLOCK(pll_d2_lock);
168 static DEFINE_SPINLOCK(pll_u_lock);
169 static DEFINE_SPINLOCK(pll_re_lock);
170
171 static struct div_nmp pllxc_nmp = {
172 .divm_shift = 0,
173 .divm_width = 8,
174 .divn_shift = 8,
175 .divn_width = 8,
176 .divp_shift = 20,
177 .divp_width = 4,
178 };
179
180 static struct pdiv_map pllxc_p[] = {
181 { .pdiv = 1, .hw_val = 0 },
182 { .pdiv = 2, .hw_val = 1 },
183 { .pdiv = 3, .hw_val = 2 },
184 { .pdiv = 4, .hw_val = 3 },
185 { .pdiv = 5, .hw_val = 4 },
186 { .pdiv = 6, .hw_val = 5 },
187 { .pdiv = 8, .hw_val = 6 },
188 { .pdiv = 10, .hw_val = 7 },
189 { .pdiv = 12, .hw_val = 8 },
190 { .pdiv = 16, .hw_val = 9 },
191 { .pdiv = 12, .hw_val = 10 },
192 { .pdiv = 16, .hw_val = 11 },
193 { .pdiv = 20, .hw_val = 12 },
194 { .pdiv = 24, .hw_val = 13 },
195 { .pdiv = 32, .hw_val = 14 },
196 { .pdiv = 0, .hw_val = 0 },
197 };
198
199 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
200 { 12000000, 624000000, 104, 0, 2},
201 { 12000000, 600000000, 100, 0, 2},
202 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
203 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
204 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
205 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
206 { 0, 0, 0, 0, 0, 0 },
207 };
208
209 static struct tegra_clk_pll_params pll_c_params = {
210 .input_min = 12000000,
211 .input_max = 800000000,
212 .cf_min = 12000000,
213 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
214 .vco_min = 600000000,
215 .vco_max = 1400000000,
216 .base_reg = PLLC_BASE,
217 .misc_reg = PLLC_MISC,
218 .lock_mask = PLL_BASE_LOCK,
219 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
220 .lock_delay = 300,
221 .iddq_reg = PLLC_MISC,
222 .iddq_bit_idx = PLLC_IDDQ_BIT,
223 .max_p = PLLXC_SW_MAX_P,
224 .dyn_ramp_reg = PLLC_MISC2,
225 .stepa_shift = 17,
226 .stepb_shift = 9,
227 .pdiv_tohw = pllxc_p,
228 .div_nmp = &pllxc_nmp,
229 .freq_table = pll_c_freq_table,
230 .flags = TEGRA_PLL_USE_LOCK,
231 };
232
233 static struct div_nmp pllcx_nmp = {
234 .divm_shift = 0,
235 .divm_width = 2,
236 .divn_shift = 8,
237 .divn_width = 8,
238 .divp_shift = 20,
239 .divp_width = 3,
240 };
241
242 static struct pdiv_map pllc_p[] = {
243 { .pdiv = 1, .hw_val = 0 },
244 { .pdiv = 2, .hw_val = 1 },
245 { .pdiv = 4, .hw_val = 3 },
246 { .pdiv = 8, .hw_val = 5 },
247 { .pdiv = 16, .hw_val = 7 },
248 { .pdiv = 0, .hw_val = 0 },
249 };
250
251 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
252 {12000000, 600000000, 100, 0, 2},
253 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
254 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
255 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
256 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
257 {0, 0, 0, 0, 0, 0},
258 };
259
260 static struct tegra_clk_pll_params pll_c2_params = {
261 .input_min = 12000000,
262 .input_max = 48000000,
263 .cf_min = 12000000,
264 .cf_max = 19200000,
265 .vco_min = 600000000,
266 .vco_max = 1200000000,
267 .base_reg = PLLC2_BASE,
268 .misc_reg = PLLC2_MISC,
269 .lock_mask = PLL_BASE_LOCK,
270 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
271 .lock_delay = 300,
272 .pdiv_tohw = pllc_p,
273 .div_nmp = &pllcx_nmp,
274 .max_p = 7,
275 .ext_misc_reg[0] = 0x4f0,
276 .ext_misc_reg[1] = 0x4f4,
277 .ext_misc_reg[2] = 0x4f8,
278 .freq_table = pll_cx_freq_table,
279 .flags = TEGRA_PLL_USE_LOCK,
280 };
281
282 static struct tegra_clk_pll_params pll_c3_params = {
283 .input_min = 12000000,
284 .input_max = 48000000,
285 .cf_min = 12000000,
286 .cf_max = 19200000,
287 .vco_min = 600000000,
288 .vco_max = 1200000000,
289 .base_reg = PLLC3_BASE,
290 .misc_reg = PLLC3_MISC,
291 .lock_mask = PLL_BASE_LOCK,
292 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
293 .lock_delay = 300,
294 .pdiv_tohw = pllc_p,
295 .div_nmp = &pllcx_nmp,
296 .max_p = 7,
297 .ext_misc_reg[0] = 0x504,
298 .ext_misc_reg[1] = 0x508,
299 .ext_misc_reg[2] = 0x50c,
300 .freq_table = pll_cx_freq_table,
301 .flags = TEGRA_PLL_USE_LOCK,
302 };
303
304 static struct div_nmp pllm_nmp = {
305 .divm_shift = 0,
306 .divm_width = 8,
307 .override_divm_shift = 0,
308 .divn_shift = 8,
309 .divn_width = 8,
310 .override_divn_shift = 8,
311 .divp_shift = 20,
312 .divp_width = 1,
313 .override_divp_shift = 27,
314 };
315
316 static struct pdiv_map pllm_p[] = {
317 { .pdiv = 1, .hw_val = 0 },
318 { .pdiv = 2, .hw_val = 1 },
319 { .pdiv = 0, .hw_val = 0 },
320 };
321
322 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
323 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */
324 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */
325 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */
326 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */
327 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
328 {0, 0, 0, 0, 0, 0},
329 };
330
331 static struct tegra_clk_pll_params pll_m_params = {
332 .input_min = 12000000,
333 .input_max = 500000000,
334 .cf_min = 12000000,
335 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
336 .vco_min = 400000000,
337 .vco_max = 1066000000,
338 .base_reg = PLLM_BASE,
339 .misc_reg = PLLM_MISC,
340 .lock_mask = PLL_BASE_LOCK,
341 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
342 .lock_delay = 300,
343 .max_p = 2,
344 .pdiv_tohw = pllm_p,
345 .div_nmp = &pllm_nmp,
346 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
347 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
348 .freq_table = pll_m_freq_table,
349 .flags = TEGRA_PLL_USE_LOCK,
350 };
351
352 static struct div_nmp pllp_nmp = {
353 .divm_shift = 0,
354 .divm_width = 5,
355 .divn_shift = 8,
356 .divn_width = 10,
357 .divp_shift = 20,
358 .divp_width = 3,
359 };
360
361 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
362 {12000000, 216000000, 432, 12, 1, 8},
363 {13000000, 216000000, 432, 13, 1, 8},
364 {16800000, 216000000, 360, 14, 1, 8},
365 {19200000, 216000000, 360, 16, 1, 8},
366 {26000000, 216000000, 432, 26, 1, 8},
367 {0, 0, 0, 0, 0, 0},
368 };
369
370 static struct tegra_clk_pll_params pll_p_params = {
371 .input_min = 2000000,
372 .input_max = 31000000,
373 .cf_min = 1000000,
374 .cf_max = 6000000,
375 .vco_min = 200000000,
376 .vco_max = 700000000,
377 .base_reg = PLLP_BASE,
378 .misc_reg = PLLP_MISC,
379 .lock_mask = PLL_BASE_LOCK,
380 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
381 .lock_delay = 300,
382 .div_nmp = &pllp_nmp,
383 .freq_table = pll_p_freq_table,
384 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
385 .fixed_rate = 408000000,
386 };
387
388 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
389 {9600000, 282240000, 147, 5, 0, 4},
390 {9600000, 368640000, 192, 5, 0, 4},
391 {9600000, 240000000, 200, 8, 0, 8},
392
393 {28800000, 282240000, 245, 25, 0, 8},
394 {28800000, 368640000, 320, 25, 0, 8},
395 {28800000, 240000000, 200, 24, 0, 8},
396 {0, 0, 0, 0, 0, 0},
397 };
398
399
400 static struct tegra_clk_pll_params pll_a_params = {
401 .input_min = 2000000,
402 .input_max = 31000000,
403 .cf_min = 1000000,
404 .cf_max = 6000000,
405 .vco_min = 200000000,
406 .vco_max = 700000000,
407 .base_reg = PLLA_BASE,
408 .misc_reg = PLLA_MISC,
409 .lock_mask = PLL_BASE_LOCK,
410 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
411 .lock_delay = 300,
412 .div_nmp = &pllp_nmp,
413 .freq_table = pll_a_freq_table,
414 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
415 };
416
417 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
418 {12000000, 216000000, 864, 12, 2, 12},
419 {13000000, 216000000, 864, 13, 2, 12},
420 {16800000, 216000000, 720, 14, 2, 12},
421 {19200000, 216000000, 720, 16, 2, 12},
422 {26000000, 216000000, 864, 26, 2, 12},
423
424 {12000000, 594000000, 594, 12, 0, 12},
425 {13000000, 594000000, 594, 13, 0, 12},
426 {16800000, 594000000, 495, 14, 0, 12},
427 {19200000, 594000000, 495, 16, 0, 12},
428 {26000000, 594000000, 594, 26, 0, 12},
429
430 {12000000, 1000000000, 1000, 12, 0, 12},
431 {13000000, 1000000000, 1000, 13, 0, 12},
432 {19200000, 1000000000, 625, 12, 0, 12},
433 {26000000, 1000000000, 1000, 26, 0, 12},
434
435 {0, 0, 0, 0, 0, 0},
436 };
437
438 static struct tegra_clk_pll_params pll_d_params = {
439 .input_min = 2000000,
440 .input_max = 40000000,
441 .cf_min = 1000000,
442 .cf_max = 6000000,
443 .vco_min = 500000000,
444 .vco_max = 1000000000,
445 .base_reg = PLLD_BASE,
446 .misc_reg = PLLD_MISC,
447 .lock_mask = PLL_BASE_LOCK,
448 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
449 .lock_delay = 1000,
450 .div_nmp = &pllp_nmp,
451 .freq_table = pll_d_freq_table,
452 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
453 TEGRA_PLL_USE_LOCK,
454 };
455
456 static struct tegra_clk_pll_params pll_d2_params = {
457 .input_min = 2000000,
458 .input_max = 40000000,
459 .cf_min = 1000000,
460 .cf_max = 6000000,
461 .vco_min = 500000000,
462 .vco_max = 1000000000,
463 .base_reg = PLLD2_BASE,
464 .misc_reg = PLLD2_MISC,
465 .lock_mask = PLL_BASE_LOCK,
466 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
467 .lock_delay = 1000,
468 .div_nmp = &pllp_nmp,
469 .freq_table = pll_d_freq_table,
470 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
471 TEGRA_PLL_USE_LOCK,
472 };
473
474 static struct pdiv_map pllu_p[] = {
475 { .pdiv = 1, .hw_val = 1 },
476 { .pdiv = 2, .hw_val = 0 },
477 { .pdiv = 0, .hw_val = 0 },
478 };
479
480 static struct div_nmp pllu_nmp = {
481 .divm_shift = 0,
482 .divm_width = 5,
483 .divn_shift = 8,
484 .divn_width = 10,
485 .divp_shift = 20,
486 .divp_width = 1,
487 };
488
489 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
490 {12000000, 480000000, 960, 12, 0, 12},
491 {13000000, 480000000, 960, 13, 0, 12},
492 {16800000, 480000000, 400, 7, 0, 5},
493 {19200000, 480000000, 200, 4, 0, 3},
494 {26000000, 480000000, 960, 26, 0, 12},
495 {0, 0, 0, 0, 0, 0},
496 };
497
498 static struct tegra_clk_pll_params pll_u_params = {
499 .input_min = 2000000,
500 .input_max = 40000000,
501 .cf_min = 1000000,
502 .cf_max = 6000000,
503 .vco_min = 480000000,
504 .vco_max = 960000000,
505 .base_reg = PLLU_BASE,
506 .misc_reg = PLLU_MISC,
507 .lock_mask = PLL_BASE_LOCK,
508 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
509 .lock_delay = 1000,
510 .pdiv_tohw = pllu_p,
511 .div_nmp = &pllu_nmp,
512 .freq_table = pll_u_freq_table,
513 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
514 TEGRA_PLL_USE_LOCK,
515 };
516
517 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
518 /* 1 GHz */
519 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
520 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
521 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
522 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
523 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
524
525 {0, 0, 0, 0, 0, 0},
526 };
527
528 static struct tegra_clk_pll_params pll_x_params = {
529 .input_min = 12000000,
530 .input_max = 800000000,
531 .cf_min = 12000000,
532 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
533 .vco_min = 700000000,
534 .vco_max = 2400000000U,
535 .base_reg = PLLX_BASE,
536 .misc_reg = PLLX_MISC,
537 .lock_mask = PLL_BASE_LOCK,
538 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
539 .lock_delay = 300,
540 .iddq_reg = PLLX_MISC3,
541 .iddq_bit_idx = PLLX_IDDQ_BIT,
542 .max_p = PLLXC_SW_MAX_P,
543 .dyn_ramp_reg = PLLX_MISC2,
544 .stepa_shift = 16,
545 .stepb_shift = 24,
546 .pdiv_tohw = pllxc_p,
547 .div_nmp = &pllxc_nmp,
548 .freq_table = pll_x_freq_table,
549 .flags = TEGRA_PLL_USE_LOCK,
550 };
551
552 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
553 /* PLLE special case: use cpcon field to store cml divider value */
554 {336000000, 100000000, 100, 21, 16, 11},
555 {312000000, 100000000, 200, 26, 24, 13},
556 {12000000, 100000000, 200, 1, 24, 13},
557 {0, 0, 0, 0, 0, 0},
558 };
559
560 static struct div_nmp plle_nmp = {
561 .divm_shift = 0,
562 .divm_width = 8,
563 .divn_shift = 8,
564 .divn_width = 8,
565 .divp_shift = 24,
566 .divp_width = 4,
567 };
568
569 static struct tegra_clk_pll_params pll_e_params = {
570 .input_min = 12000000,
571 .input_max = 1000000000,
572 .cf_min = 12000000,
573 .cf_max = 75000000,
574 .vco_min = 1600000000,
575 .vco_max = 2400000000U,
576 .base_reg = PLLE_BASE,
577 .misc_reg = PLLE_MISC,
578 .aux_reg = PLLE_AUX,
579 .lock_mask = PLLE_MISC_LOCK,
580 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
581 .lock_delay = 300,
582 .div_nmp = &plle_nmp,
583 .freq_table = pll_e_freq_table,
584 .flags = TEGRA_PLL_FIXED,
585 .fixed_rate = 100000000,
586 };
587
588 static struct div_nmp pllre_nmp = {
589 .divm_shift = 0,
590 .divm_width = 8,
591 .divn_shift = 8,
592 .divn_width = 8,
593 .divp_shift = 16,
594 .divp_width = 4,
595 };
596
597 static struct tegra_clk_pll_params pll_re_vco_params = {
598 .input_min = 12000000,
599 .input_max = 1000000000,
600 .cf_min = 12000000,
601 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
602 .vco_min = 300000000,
603 .vco_max = 600000000,
604 .base_reg = PLLRE_BASE,
605 .misc_reg = PLLRE_MISC,
606 .lock_mask = PLLRE_MISC_LOCK,
607 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
608 .lock_delay = 300,
609 .iddq_reg = PLLRE_MISC,
610 .iddq_bit_idx = PLLRE_IDDQ_BIT,
611 .div_nmp = &pllre_nmp,
612 .flags = TEGRA_PLL_USE_LOCK,
613 };
614
615 /* possible OSC frequencies in Hz */
616 static unsigned long tegra114_input_freq[] = {
617 [0] = 13000000,
618 [1] = 16800000,
619 [4] = 19200000,
620 [5] = 38400000,
621 [8] = 12000000,
622 [9] = 48000000,
623 [12] = 260000000,
624 };
625
626 #define MASK(x) (BIT(x) - 1)
627
628 struct utmi_clk_param {
629 /* Oscillator Frequency in KHz */
630 u32 osc_frequency;
631 /* UTMIP PLL Enable Delay Count */
632 u8 enable_delay_count;
633 /* UTMIP PLL Stable count */
634 u8 stable_count;
635 /* UTMIP PLL Active delay count */
636 u8 active_delay_count;
637 /* UTMIP PLL Xtal frequency count */
638 u8 xtal_freq_count;
639 };
640
641 static const struct utmi_clk_param utmi_parameters[] = {
642 {.osc_frequency = 13000000, .enable_delay_count = 0x02,
643 .stable_count = 0x33, .active_delay_count = 0x05,
644 .xtal_freq_count = 0x7F},
645 {.osc_frequency = 19200000, .enable_delay_count = 0x03,
646 .stable_count = 0x4B, .active_delay_count = 0x06,
647 .xtal_freq_count = 0xBB},
648 {.osc_frequency = 12000000, .enable_delay_count = 0x02,
649 .stable_count = 0x2F, .active_delay_count = 0x04,
650 .xtal_freq_count = 0x76},
651 {.osc_frequency = 26000000, .enable_delay_count = 0x04,
652 .stable_count = 0x66, .active_delay_count = 0x09,
653 .xtal_freq_count = 0xFE},
654 {.osc_frequency = 16800000, .enable_delay_count = 0x03,
655 .stable_count = 0x41, .active_delay_count = 0x0A,
656 .xtal_freq_count = 0xA4},
657 };
658
659 /* peripheral mux definitions */
660
661 static const char *mux_plld_out0_plld2_out0[] = {
662 "pll_d_out0", "pll_d2_out0",
663 };
664 #define mux_plld_out0_plld2_out0_idx NULL
665
666 static const char *mux_pllmcp_clkm[] = {
667 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
668 };
669
670 static const struct clk_div_table pll_re_div_table[] = {
671 { .val = 0, .div = 1 },
672 { .val = 1, .div = 2 },
673 { .val = 2, .div = 3 },
674 { .val = 3, .div = 4 },
675 { .val = 4, .div = 5 },
676 { .val = 5, .div = 6 },
677 { .val = 0, .div = 0 },
678 };
679
680 static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
681 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
682 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
683 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
684 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
685 [tegra_clk_sdmmc2] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
686 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
687 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
688 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
689 [tegra_clk_sdmmc1] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
690 [tegra_clk_sdmmc4] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
691 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
692 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
693 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
694 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
695 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
696 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
697 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
698 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
699 [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
700 [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
701 [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
702 [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
703 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
704 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
705 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
706 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
707 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
708 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
709 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
710 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
711 [tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true },
712 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
713 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
714 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
715 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
716 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
717 [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
718 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
719 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
720 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
721 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
722 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
723 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
724 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
725 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
726 [tegra_clk_sdmmc3] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
727 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
728 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
729 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
730 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
731 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
732 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
733 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
734 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
735 [tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true },
736 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
737 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
738 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
739 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
740 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
741 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
742 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
743 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
744 [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
745 [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
746 [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
747 [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
748 [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
749 [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
750 [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
751 [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
752 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
753 [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
754 [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
755 [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
756 [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
757 [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
758 [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
759 [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
760 [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
761 [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
762 [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
763 [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
764 [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
765 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
766 [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
767 [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
768 [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
769 [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
770 [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
771 [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
772 [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
773 [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
774 [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
775 [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
776 [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
777 [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
778 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
779 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
780 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
781 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA114_CLK_VI_SENSOR, .present = true },
782 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
783 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
784 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
785 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
786 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
787 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
788 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
789 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
790 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
791 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
792 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
793 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
794 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
795 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
796 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
797 [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
798 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
799 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
800 [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
801 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
802 [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
803 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
804 [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
805 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
806 [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
807 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
808 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
809 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
810 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
811 [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
812 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
813 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
814 [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
815 [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
816 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
817 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
818 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
819 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
820 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
821 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
822 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
823 [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
824 [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
825 [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
826 [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
827 [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
828 [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
829 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
830 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
831 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
832 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
833 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
834 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
835 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
836 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
837 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
838 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
839 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
840 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
841 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
842 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
843 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
844 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
845 [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
846 [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
847 [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
848 [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
849 [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
850 [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
851 [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
852 [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
853 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
854 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
855 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
856 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
857 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
858 };
859
860 static struct tegra_devclk devclks[] __initdata = {
861 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
862 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
863 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
864 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
865 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
866 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
867 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
868 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
869 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
870 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
871 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
872 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
873 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
874 { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
875 { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
876 { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
877 { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
878 { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
879 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
880 { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
881 { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
882 { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
883 { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
884 { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
885 { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
886 { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
887 { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
888 { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
889 { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
890 { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
891 { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
892 { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
893 { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
894 { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
895 { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
896 { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
897 { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
898 { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
899 { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
900 { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
901 { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
902 { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
903 { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
904 { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
905 { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
906 { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
907 { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
908 { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
909 { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
910 { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
911 { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
912 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
913 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
914 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
915 { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
916 { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
917 { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
918 { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
919 { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
920 { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
921 { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
922 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
923 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
924 };
925
926 static struct clk **clks;
927
928 static unsigned long osc_freq;
929 static unsigned long pll_ref_freq;
930
931 static int __init tegra114_osc_clk_init(void __iomem *clk_base)
932 {
933 struct clk *clk;
934 u32 val, pll_ref_div;
935
936 val = readl_relaxed(clk_base + OSC_CTRL);
937
938 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
939 if (!osc_freq) {
940 WARN_ON(1);
941 return -EINVAL;
942 }
943
944 /* clk_m */
945 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
946 osc_freq);
947 clks[TEGRA114_CLK_CLK_M] = clk;
948
949 /* pll_ref */
950 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
951 pll_ref_div = 1 << val;
952 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
953 CLK_SET_RATE_PARENT, 1, pll_ref_div);
954 clks[TEGRA114_CLK_PLL_REF] = clk;
955
956 pll_ref_freq = osc_freq / pll_ref_div;
957
958 return 0;
959 }
960
961 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
962 {
963 struct clk *clk;
964
965 /* clk_32k */
966 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
967 32768);
968 clks[TEGRA114_CLK_CLK_32K] = clk;
969
970 /* clk_m_div2 */
971 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
972 CLK_SET_RATE_PARENT, 1, 2);
973 clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
974
975 /* clk_m_div4 */
976 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
977 CLK_SET_RATE_PARENT, 1, 4);
978 clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
979
980 }
981
982 static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
983 {
984 u32 reg;
985 int i;
986
987 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
988 if (osc_freq == utmi_parameters[i].osc_frequency)
989 break;
990 }
991
992 if (i >= ARRAY_SIZE(utmi_parameters)) {
993 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
994 osc_freq);
995 return;
996 }
997
998 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
999
1000 /* Program UTMIP PLL stable and active counts */
1001 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1002 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1003 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1004
1005 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1006
1007 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1008 active_delay_count);
1009
1010 /* Remove power downs from UTMIP PLL control bits */
1011 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1012 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1013 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1014
1015 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1016
1017 /* Program UTMIP PLL delay and oscillator frequency counts */
1018 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1019 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1020
1021 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1022 enable_delay_count);
1023
1024 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1025 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1026 xtal_freq_count);
1027
1028 /* Remove power downs from UTMIP PLL control bits */
1029 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1030 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1031 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1032 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1033 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1034
1035 /* Setup HW control of UTMIPLL */
1036 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1037 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1038 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1039 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1040 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1041
1042 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1043 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1044 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1045 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1046
1047 udelay(1);
1048
1049 /* Setup SW override of UTMIPLL assuming USB2.0
1050 ports are assigned to USB2 */
1051 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1052 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1053 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1054 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1055
1056 udelay(1);
1057
1058 /* Enable HW control UTMIPLL */
1059 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1060 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1061 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1062 }
1063
1064 static void __init tegra114_pll_init(void __iomem *clk_base,
1065 void __iomem *pmc)
1066 {
1067 u32 val;
1068 struct clk *clk;
1069
1070 /* PLLC */
1071 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1072 pmc, 0, &pll_c_params, NULL);
1073 clks[TEGRA114_CLK_PLL_C] = clk;
1074
1075 /* PLLC_OUT1 */
1076 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1077 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1078 8, 8, 1, NULL);
1079 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1080 clk_base + PLLC_OUT, 1, 0,
1081 CLK_SET_RATE_PARENT, 0, NULL);
1082 clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
1083
1084 /* PLLC2 */
1085 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1086 &pll_c2_params, NULL);
1087 clks[TEGRA114_CLK_PLL_C2] = clk;
1088
1089 /* PLLC3 */
1090 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1091 &pll_c3_params, NULL);
1092 clks[TEGRA114_CLK_PLL_C3] = clk;
1093
1094 /* PLLM */
1095 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1096 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1097 &pll_m_params, NULL);
1098 clks[TEGRA114_CLK_PLL_M] = clk;
1099
1100 /* PLLM_OUT1 */
1101 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1102 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1103 8, 8, 1, NULL);
1104 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1105 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1106 CLK_SET_RATE_PARENT, 0, NULL);
1107 clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
1108
1109 /* PLLM_UD */
1110 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1111 CLK_SET_RATE_PARENT, 1, 1);
1112
1113 /* PLLU */
1114 val = readl(clk_base + pll_u_params.base_reg);
1115 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1116 writel(val, clk_base + pll_u_params.base_reg);
1117
1118 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1119 &pll_u_params, &pll_u_lock);
1120 clks[TEGRA114_CLK_PLL_U] = clk;
1121
1122 tegra114_utmi_param_configure(clk_base);
1123
1124 /* PLLU_480M */
1125 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1126 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1127 22, 0, &pll_u_lock);
1128 clks[TEGRA114_CLK_PLL_U_480M] = clk;
1129
1130 /* PLLU_60M */
1131 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1132 CLK_SET_RATE_PARENT, 1, 8);
1133 clks[TEGRA114_CLK_PLL_U_60M] = clk;
1134
1135 /* PLLU_48M */
1136 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1137 CLK_SET_RATE_PARENT, 1, 10);
1138 clks[TEGRA114_CLK_PLL_U_48M] = clk;
1139
1140 /* PLLU_12M */
1141 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1142 CLK_SET_RATE_PARENT, 1, 40);
1143 clks[TEGRA114_CLK_PLL_U_12M] = clk;
1144
1145 /* PLLD */
1146 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1147 &pll_d_params, &pll_d_lock);
1148 clks[TEGRA114_CLK_PLL_D] = clk;
1149
1150 /* PLLD_OUT0 */
1151 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1152 CLK_SET_RATE_PARENT, 1, 2);
1153 clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
1154
1155 /* PLLD2 */
1156 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1157 &pll_d2_params, &pll_d2_lock);
1158 clks[TEGRA114_CLK_PLL_D2] = clk;
1159
1160 /* PLLD2_OUT0 */
1161 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1162 CLK_SET_RATE_PARENT, 1, 2);
1163 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
1164
1165 /* PLLRE */
1166 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1167 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1168 clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
1169
1170 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1171 clk_base + PLLRE_BASE, 16, 4, 0,
1172 pll_re_div_table, &pll_re_lock);
1173 clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
1174
1175 /* PLLE */
1176 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
1177 clk_base, 0, &pll_e_params, NULL);
1178 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1179 }
1180
1181 static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1182 void __iomem *pmc_base)
1183 {
1184 struct clk *clk;
1185 u32 val;
1186
1187 /* xusb_hs_src */
1188 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1189 val |= BIT(25); /* always select PLLU_60M */
1190 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1191
1192 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1193 1, 1);
1194 clks[TEGRA114_CLK_XUSB_HS_SRC] = clk;
1195
1196 /* dsia mux */
1197 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1198 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1199 CLK_SET_RATE_NO_REPARENT,
1200 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1201 clks[TEGRA114_CLK_DSIA_MUX] = clk;
1202
1203 /* dsib mux */
1204 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1205 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1206 CLK_SET_RATE_NO_REPARENT,
1207 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1208 clks[TEGRA114_CLK_DSIB_MUX] = clk;
1209
1210 /* emc mux */
1211 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1212 ARRAY_SIZE(mux_pllmcp_clkm),
1213 CLK_SET_RATE_NO_REPARENT,
1214 clk_base + CLK_SOURCE_EMC,
1215 29, 3, 0, NULL);
1216
1217 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1218 &pll_p_params);
1219 }
1220
1221 /* Tegra114 CPU clock and reset control functions */
1222 static void tegra114_wait_cpu_in_reset(u32 cpu)
1223 {
1224 unsigned int reg;
1225
1226 do {
1227 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1228 cpu_relax();
1229 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1230 }
1231 static void tegra114_disable_cpu_clock(u32 cpu)
1232 {
1233 /* flow controller would take care in the power sequence. */
1234 }
1235
1236 #ifdef CONFIG_PM_SLEEP
1237 static void tegra114_cpu_clock_suspend(void)
1238 {
1239 /* switch coresite to clk_m, save off original source */
1240 tegra114_cpu_clk_sctx.clk_csite_src =
1241 readl(clk_base + CLK_SOURCE_CSITE);
1242 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1243
1244 tegra114_cpu_clk_sctx.cclkg_burst =
1245 readl(clk_base + CCLKG_BURST_POLICY);
1246 tegra114_cpu_clk_sctx.cclkg_divider =
1247 readl(clk_base + CCLKG_BURST_POLICY + 4);
1248 }
1249
1250 static void tegra114_cpu_clock_resume(void)
1251 {
1252 writel(tegra114_cpu_clk_sctx.clk_csite_src,
1253 clk_base + CLK_SOURCE_CSITE);
1254
1255 writel(tegra114_cpu_clk_sctx.cclkg_burst,
1256 clk_base + CCLKG_BURST_POLICY);
1257 writel(tegra114_cpu_clk_sctx.cclkg_divider,
1258 clk_base + CCLKG_BURST_POLICY + 4);
1259 }
1260 #endif
1261
1262 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1263 .wait_for_reset = tegra114_wait_cpu_in_reset,
1264 .disable_clock = tegra114_disable_cpu_clock,
1265 #ifdef CONFIG_PM_SLEEP
1266 .suspend = tegra114_cpu_clock_suspend,
1267 .resume = tegra114_cpu_clock_resume,
1268 #endif
1269 };
1270
1271 static const struct of_device_id pmc_match[] __initconst = {
1272 { .compatible = "nvidia,tegra114-pmc" },
1273 {},
1274 };
1275
1276 /*
1277 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
1278 * breaks
1279 */
1280 static struct tegra_clk_init_table init_table[] __initdata = {
1281 {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0},
1282 {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0},
1283 {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0},
1284 {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0},
1285 {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1},
1286 {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1},
1287 {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1},
1288 {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1},
1289 {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1},
1290 {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1291 {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1292 {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1293 {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1294 {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
1295 {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
1296 {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
1297 {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
1298 {TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
1299 {TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
1300 {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1301 {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1302 {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
1303 {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
1304
1305 /* This MUST be the last entry. */
1306 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
1307 };
1308
1309 static void __init tegra114_clock_apply_init_table(void)
1310 {
1311 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
1312 }
1313
1314
1315 /**
1316 * tegra114_car_barrier - wait for pending writes to the CAR to complete
1317 *
1318 * Wait for any outstanding writes to the CAR MMIO space from this CPU
1319 * to complete before continuing execution. No return value.
1320 */
1321 static void tegra114_car_barrier(void)
1322 {
1323 wmb(); /* probably unnecessary */
1324 readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
1325 }
1326
1327 /**
1328 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1329 *
1330 * When the CPU rail voltage is in the high-voltage range, use the
1331 * built-in hardwired clock propagation delays in the CPU clock
1332 * shaper. No return value.
1333 */
1334 void tegra114_clock_tune_cpu_trimmers_high(void)
1335 {
1336 u32 select = 0;
1337
1338 /* Use hardwired rise->rise & fall->fall clock propagation delays */
1339 select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1340 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1341 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1342 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1343
1344 tegra114_car_barrier();
1345 }
1346 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
1347
1348 /**
1349 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1350 *
1351 * When the CPU rail voltage is in the low-voltage range, use the
1352 * extended clock propagation delays set by
1353 * tegra114_clock_tune_cpu_trimmers_init(). The intention is to
1354 * maintain the input clock duty cycle that the FCPU subsystem
1355 * expects. No return value.
1356 */
1357 void tegra114_clock_tune_cpu_trimmers_low(void)
1358 {
1359 u32 select = 0;
1360
1361 /*
1362 * Use software-specified rise->rise & fall->fall clock
1363 * propagation delays (from
1364 * tegra114_clock_tune_cpu_trimmers_init()
1365 */
1366 select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1367 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1368 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1369 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1370
1371 tegra114_car_barrier();
1372 }
1373 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
1374
1375 /**
1376 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1377 *
1378 * Program extended clock propagation delays into the FCPU clock
1379 * shaper and enable them. XXX Define the purpose - peak current
1380 * reduction? No return value.
1381 */
1382 /* XXX Initial voltage rail state assumption issues? */
1383 void tegra114_clock_tune_cpu_trimmers_init(void)
1384 {
1385 u32 dr = 0, r = 0;
1386
1387 /* Increment the rise->rise clock delay by four steps */
1388 r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
1389 CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
1390 CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
1391 writel_relaxed(r, clk_base + CPU_FINETRIM_R);
1392
1393 /*
1394 * Use the rise->rise clock propagation delay specified in the
1395 * r field
1396 */
1397 dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1398 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1399 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1400 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
1401
1402 tegra114_clock_tune_cpu_trimmers_low();
1403 }
1404 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
1405
1406 /**
1407 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1408 *
1409 * Assert the reset line of the DFLL's DVCO. No return value.
1410 */
1411 void tegra114_clock_assert_dfll_dvco_reset(void)
1412 {
1413 u32 v;
1414
1415 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1416 v |= (1 << DVFS_DFLL_RESET_SHIFT);
1417 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1418 tegra114_car_barrier();
1419 }
1420 EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
1421
1422 /**
1423 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1424 *
1425 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1426 * operate. No return value.
1427 */
1428 void tegra114_clock_deassert_dfll_dvco_reset(void)
1429 {
1430 u32 v;
1431
1432 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1433 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1434 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1435 tegra114_car_barrier();
1436 }
1437 EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
1438
1439 static void __init tegra114_clock_init(struct device_node *np)
1440 {
1441 struct device_node *node;
1442
1443 clk_base = of_iomap(np, 0);
1444 if (!clk_base) {
1445 pr_err("ioremap tegra114 CAR failed\n");
1446 return;
1447 }
1448
1449 node = of_find_matching_node(NULL, pmc_match);
1450 if (!node) {
1451 pr_err("Failed to find pmc node\n");
1452 WARN_ON(1);
1453 return;
1454 }
1455
1456 pmc_base = of_iomap(node, 0);
1457 if (!pmc_base) {
1458 pr_err("Can't map pmc registers\n");
1459 WARN_ON(1);
1460 return;
1461 }
1462
1463 clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1464 TEGRA114_CLK_PERIPH_BANKS);
1465 if (!clks)
1466 return;
1467
1468 if (tegra114_osc_clk_init(clk_base) < 0)
1469 return;
1470
1471 tegra114_fixed_clk_init(clk_base);
1472 tegra114_pll_init(clk_base, pmc_base);
1473 tegra114_periph_clk_init(clk_base, pmc_base);
1474 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
1475 tegra_pmc_clk_init(pmc_base, tegra114_clks);
1476 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1477 &pll_x_params);
1478
1479 tegra_add_of_provider(np);
1480 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1481
1482 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1483
1484 tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1485 }
1486 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
Linux with added FPC-III support