drivers/clocksource/time-armada-370-xp.c

   1 /*
   2  * Marvell Armada 370/XP SoC timer handling.
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * Timer 0 is used as free-running clocksource, while timer 1 is
  15  * used as clock_event_device.
  16  *
  17  * ---
  18  * Clocksource driver for Armada 370 and Armada XP SoC.
  19  * This driver implements one compatible string for each SoC, given
  20  * each has its own characteristics:
  21  *
  22  *   * Armada 370 has no 25 MHz fixed timer.
  23  *
  24  *   * Armada XP cannot work properly without such 25 MHz fixed timer as
  25  *     doing otherwise leads to using a clocksource whose frequency varies
  26  *     when doing cpufreq frequency changes.
  27  *
  28  * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
  29  */
  30
  31 #include <linux/init.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/kernel.h>
  34 #include <linux/clk.h>
  35 #include <linux/cpu.h>
  36 #include <linux/timer.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/of.h>
  40 #include <linux/of_irq.h>
  41 #include <linux/of_address.h>
  42 #include <linux/irq.h>
  43 #include <linux/module.h>
  44 #include <linux/sched_clock.h>
  45 #include <linux/percpu.h>
  46
  47 /*
  48  * Timer block registers.
  49  */
  50 #define TIMER_CTRL_OFF          0x0000
  51 #define  TIMER0_EN               BIT(0)
  52 #define  TIMER0_RELOAD_EN        BIT(1)
  53 #define  TIMER0_25MHZ            BIT(11)
  54 #define  TIMER0_DIV(div)         ((div) << 19)
  55 #define  TIMER1_EN               BIT(2)
  56 #define  TIMER1_RELOAD_EN        BIT(3)
  57 #define  TIMER1_25MHZ            BIT(12)
  58 #define  TIMER1_DIV(div)         ((div) << 22)
  59 #define TIMER_EVENTS_STATUS     0x0004
  60 #define  TIMER0_CLR_MASK         (~0x1)
  61 #define  TIMER1_CLR_MASK         (~0x100)
  62 #define TIMER0_RELOAD_OFF       0x0010
  63 #define TIMER0_VAL_OFF          0x0014
  64 #define TIMER1_RELOAD_OFF       0x0018
  65 #define TIMER1_VAL_OFF          0x001c
  66
  67 #define LCL_TIMER_EVENTS_STATUS 0x0028
  68 /* Global timers are connected to the coherency fabric clock, and the
  69    below divider reduces their incrementing frequency. */
  70 #define TIMER_DIVIDER_SHIFT     5
  71 #define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)
  72
  73 /*
  74  * SoC-specific data.
  75  */
  76 static void __iomem *timer_base, *local_base;
  77 static unsigned int timer_clk;
  78 static bool timer25Mhz = true;
  79 static u32 enable_mask;
  80
  81 /*
  82  * Number of timer ticks per jiffy.
  83  */
  84 static u32 ticks_per_jiffy;
  85
  86 static struct clock_event_device __percpu *armada_370_xp_evt;
  87
  88 static void timer_ctrl_clrset(u32 clr, u32 set)
  89 {
  90         writel((readl(timer_base + TIMER_CTRL_OFF) & ~clr) | set,
  91                 timer_base + TIMER_CTRL_OFF);
  92 }
  93
  94 static void local_timer_ctrl_clrset(u32 clr, u32 set)
  95 {
  96         writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
  97                 local_base + TIMER_CTRL_OFF);
  98 }
  99
 100 static u64 notrace armada_370_xp_read_sched_clock(void)
 101 {
 102         return ~readl(timer_base + TIMER0_VAL_OFF);
 103 }
 104
 105 /*
 106  * Clockevent handling.
 107  */
 108 static int
 109 armada_370_xp_clkevt_next_event(unsigned long delta,
 110                                 struct clock_event_device *dev)
 111 {
 112         /*
 113          * Clear clockevent timer interrupt.
 114          */
 115         writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 116
 117         /*
 118          * Setup new clockevent timer value.
 119          */
 120         writel(delta, local_base + TIMER0_VAL_OFF);
 121
 122         /*
 123          * Enable the timer.
 124          */
 125         local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
 126         return 0;
 127 }
 128
 129 static void
 130 armada_370_xp_clkevt_mode(enum clock_event_mode mode,
 131                           struct clock_event_device *dev)
 132 {
 133         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 134
 135                 /*
 136                  * Setup timer to fire at 1/HZ intervals.
 137                  */
 138                 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
 139                 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
 140
 141                 /*
 142                  * Enable timer.
 143                  */
 144                 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
 145         } else {
 146                 /*
 147                  * Disable timer.
 148                  */
 149                 local_timer_ctrl_clrset(TIMER0_EN, 0);
 150
 151                 /*
 152                  * ACK pending timer interrupt.
 153                  */
 154                 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 155         }
 156 }
 157
 158 static int armada_370_xp_clkevt_irq;
 159
 160 static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
 161 {
 162         /*
 163          * ACK timer interrupt and call event handler.
 164          */
 165         struct clock_event_device *evt = dev_id;
 166
 167         writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
 168         evt->event_handler(evt);
 169
 170         return IRQ_HANDLED;
 171 }
 172
 173 /*
 174  * Setup the local clock events for a CPU.
 175  */
 176 static int armada_370_xp_timer_setup(struct clock_event_device *evt)
 177 {
 178         u32 clr = 0, set = 0;
 179         int cpu = smp_processor_id();
 180
 181         if (timer25Mhz)
 182                 set = TIMER0_25MHZ;
 183         else
 184                 clr = TIMER0_25MHZ;
 185         local_timer_ctrl_clrset(clr, set);
 186
 187         evt->name               = "armada_370_xp_per_cpu_tick",
 188         evt->features           = CLOCK_EVT_FEAT_ONESHOT |
 189                                   CLOCK_EVT_FEAT_PERIODIC;
 190         evt->shift              = 32,
 191         evt->rating             = 300,
 192         evt->set_next_event     = armada_370_xp_clkevt_next_event,
 193         evt->set_mode           = armada_370_xp_clkevt_mode,
 194         evt->irq                = armada_370_xp_clkevt_irq;
 195         evt->cpumask            = cpumask_of(cpu);
 196
 197         clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
 198         enable_percpu_irq(evt->irq, 0);
 199
 200         return 0;
 201 }
 202
 203 static void armada_370_xp_timer_stop(struct clock_event_device *evt)
 204 {
 205         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
 206         disable_percpu_irq(evt->irq);
 207 }
 208
 209 static int armada_370_xp_timer_cpu_notify(struct notifier_block *self,
 210                                            unsigned long action, void *hcpu)
 211 {
 212         /*
 213          * Grab cpu pointer in each case to avoid spurious
 214          * preemptible warnings
 215          */
 216         switch (action & ~CPU_TASKS_FROZEN) {
 217         case CPU_STARTING:
 218                 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
 219                 break;
 220         case CPU_DYING:
 221                 armada_370_xp_timer_stop(this_cpu_ptr(armada_370_xp_evt));
 222                 break;
 223         }
 224
 225         return NOTIFY_OK;
 226 }
 227
 228 static struct notifier_block armada_370_xp_timer_cpu_nb = {
 229         .notifier_call = armada_370_xp_timer_cpu_notify,
 230 };
 231
 232 static void __init armada_370_xp_timer_common_init(struct device_node *np)
 233 {
 234         u32 clr = 0, set = 0;
 235         int res;
 236
 237         timer_base = of_iomap(np, 0);
 238         WARN_ON(!timer_base);
 239         local_base = of_iomap(np, 1);
 240
 241         if (timer25Mhz) {
 242                 set = TIMER0_25MHZ;
 243                 enable_mask = TIMER0_EN;
 244         } else {
 245                 clr = TIMER0_25MHZ;
 246                 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
 247         }
 248         timer_ctrl_clrset(clr, set);
 249         local_timer_ctrl_clrset(clr, set);
 250
 251         /*
 252          * We use timer 0 as clocksource, and private(local) timer 0
 253          * for clockevents
 254          */
 255         armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
 256
 257         ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
 258
 259         /*
 260          * Setup free-running clocksource timer (interrupts
 261          * disabled).
 262          */
 263         writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
 264         writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 265
 266         timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
 267
 268         /*
 269          * Set scale and timer for sched_clock.
 270          */
 271         sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
 272
 273         clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
 274                               "armada_370_xp_clocksource",
 275                               timer_clk, 300, 32, clocksource_mmio_readl_down);
 276
 277         register_cpu_notifier(&armada_370_xp_timer_cpu_nb);
 278
 279         armada_370_xp_evt = alloc_percpu(struct clock_event_device);
 280
 281
 282         /*
 283          * Setup clockevent timer (interrupt-driven).
 284          */
 285         res = request_percpu_irq(armada_370_xp_clkevt_irq,
 286                                 armada_370_xp_timer_interrupt,
 287                                 "armada_370_xp_per_cpu_tick",
 288                                 armada_370_xp_evt);
 289         /* Immediately configure the timer on the boot CPU */
 290         if (!res)
 291                 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
 292 }
 293
 294 static void __init armada_xp_timer_init(struct device_node *np)
 295 {
 296         struct clk *clk = of_clk_get_by_name(np, "fixed");
 297
 298         /* The 25Mhz fixed clock is mandatory, and must always be available */
 299         BUG_ON(IS_ERR(clk));
 300         timer_clk = clk_get_rate(clk);
 301
 302         armada_370_xp_timer_common_init(np);
 303 }
 304 CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
 305                        armada_xp_timer_init);
 306
 307 static void __init armada_370_timer_init(struct device_node *np)
 308 {
 309         struct clk *clk = of_clk_get(np, 0);
 310
 311         BUG_ON(IS_ERR(clk));
 312         timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
 313         timer25Mhz = false;
 314
 315         armada_370_xp_timer_common_init(np);
 316 }
 317 CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
 318                        armada_370_timer_init);