drivers/crypto/talitos.h

   1 /*
   2  * Freescale SEC (talitos) device register and descriptor header defines
   3  *
   4  * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  */
  30
  31 #define TALITOS_TIMEOUT 100000
  32 #define TALITOS_MAX_DATA_LEN 65535
  33
  34 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
  35 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
  36 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
  37
  38 /* descriptor pointer entry */
  39 struct talitos_ptr {
  40         __be16 len;     /* length */
  41         u8 j_extent;    /* jump to sg link table and/or extent */
  42         u8 eptr;        /* extended address */
  43         __be32 ptr;     /* address */
  44 };
  45
  46 static const struct talitos_ptr zero_entry = {
  47         .len = 0,
  48         .j_extent = 0,
  49         .eptr = 0,
  50         .ptr = 0
  51 };
  52
  53 /* descriptor */
  54 struct talitos_desc {
  55         __be32 hdr;                     /* header high bits */
  56         __be32 hdr_lo;                  /* header low bits */
  57         struct talitos_ptr ptr[7];      /* ptr/len pair array */
  58 };
  59
  60 /**
  61  * talitos_request - descriptor submission request
  62  * @desc: descriptor pointer (kernel virtual)
  63  * @dma_desc: descriptor's physical bus address
  64  * @callback: whom to call when descriptor processing is done
  65  * @context: caller context (optional)
  66  */
  67 struct talitos_request {
  68         struct talitos_desc *desc;
  69         dma_addr_t dma_desc;
  70         void (*callback) (struct device *dev, struct talitos_desc *desc,
  71                           void *context, int error);
  72         void *context;
  73 };
  74
  75 /* per-channel fifo management */
  76 struct talitos_channel {
  77         void __iomem *reg;
  78
  79         /* request fifo */
  80         struct talitos_request *fifo;
  81
  82         /* number of requests pending in channel h/w fifo */
  83         atomic_t submit_count ____cacheline_aligned;
  84
  85         /* request submission (head) lock */
  86         spinlock_t head_lock ____cacheline_aligned;
  87         /* index to next free descriptor request */
  88         int head;
  89
  90         /* request release (tail) lock */
  91         spinlock_t tail_lock ____cacheline_aligned;
  92         /* index to next in-progress/done descriptor request */
  93         int tail;
  94 };
  95
  96 struct talitos_private {
  97         struct device *dev;
  98         struct platform_device *ofdev;
  99         void __iomem *reg;
 100         int irq[2];
 101
 102         /* SEC global registers lock  */
 103         spinlock_t reg_lock ____cacheline_aligned;
 104
 105         /* SEC version geometry (from device tree node) */
 106         unsigned int num_channels;
 107         unsigned int chfifo_len;
 108         unsigned int exec_units;
 109         unsigned int desc_types;
 110
 111         /* SEC Compatibility info */
 112         unsigned long features;
 113
 114         /*
 115          * length of the request fifo
 116          * fifo_len is chfifo_len rounded up to next power of 2
 117          * so we can use bitwise ops to wrap
 118          */
 119         unsigned int fifo_len;
 120
 121         struct talitos_channel *chan;
 122
 123         /* next channel to be assigned next incoming descriptor */
 124         atomic_t last_chan ____cacheline_aligned;
 125
 126         /* request callback tasklet */
 127         struct tasklet_struct done_task[2];
 128
 129         /* list of registered algorithms */
 130         struct list_head alg_list;
 131
 132         /* hwrng device */
 133         struct hwrng rng;
 134 };
 135
 136 extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
 137                           void (*callback)(struct device *dev,
 138                                            struct talitos_desc *desc,
 139                                            void *context, int error),
 140                           void *context);
 141
 142 /* .features flag */
 143 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
 144 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
 145 #define TALITOS_FTR_SHA224_HWINIT 0x00000004
 146 #define TALITOS_FTR_HMAC_OK 0x00000008
 147
 148 /*
 149  * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
 150  */
 151
 152 /* global register offset addresses */
 153 #define TALITOS_MCR                     0x1030  /* master control register */
 154 #define   TALITOS_MCR_RCA0              (1 << 15) /* remap channel 0 */
 155 #define   TALITOS_MCR_RCA1              (1 << 14) /* remap channel 1 */
 156 #define   TALITOS_MCR_RCA2              (1 << 13) /* remap channel 2 */
 157 #define   TALITOS_MCR_RCA3              (1 << 12) /* remap channel 3 */
 158 #define   TALITOS_MCR_SWR               0x1     /* s/w reset */
 159 #define TALITOS_MCR_LO                  0x1034
 160 #define TALITOS_IMR                     0x1008  /* interrupt mask register */
 161 #define   TALITOS_IMR_INIT              0x100ff /* enable channel IRQs */
 162 #define   TALITOS_IMR_DONE              0x00055 /* done IRQs */
 163 #define TALITOS_IMR_LO                  0x100C
 164 #define   TALITOS_IMR_LO_INIT           0x20000 /* allow RNGU error IRQs */
 165 #define TALITOS_ISR                     0x1010  /* interrupt status register */
 166 #define   TALITOS_ISR_4CHERR            0xaa    /* 4 channel errors mask */
 167 #define   TALITOS_ISR_4CHDONE           0x55    /* 4 channel done mask */
 168 #define   TALITOS_ISR_CH_0_2_ERR        0x22    /* channels 0, 2 errors mask */
 169 #define   TALITOS_ISR_CH_0_2_DONE       0x11    /* channels 0, 2 done mask */
 170 #define   TALITOS_ISR_CH_1_3_ERR        0x88    /* channels 1, 3 errors mask */
 171 #define   TALITOS_ISR_CH_1_3_DONE       0x44    /* channels 1, 3 done mask */
 172 #define TALITOS_ISR_LO                  0x1014
 173 #define TALITOS_ICR                     0x1018  /* interrupt clear register */
 174 #define TALITOS_ICR_LO                  0x101C
 175
 176 /* channel register address stride */
 177 #define TALITOS_CH_BASE_OFFSET          0x1000  /* default channel map base */
 178 #define TALITOS_CH_STRIDE               0x100
 179
 180 /* channel configuration register  */
 181 #define TALITOS_CCCR                    0x8
 182 #define   TALITOS_CCCR_CONT             0x2    /* channel continue */
 183 #define   TALITOS_CCCR_RESET            0x1    /* channel reset */
 184 #define TALITOS_CCCR_LO                 0xc
 185 #define   TALITOS_CCCR_LO_IWSE          0x80   /* chan. ICCR writeback enab. */
 186 #define   TALITOS_CCCR_LO_EAE           0x20   /* extended address enable */
 187 #define   TALITOS_CCCR_LO_CDWE          0x10   /* chan. done writeback enab. */
 188 #define   TALITOS_CCCR_LO_NT            0x4    /* notification type */
 189 #define   TALITOS_CCCR_LO_CDIE          0x2    /* channel done IRQ enable */
 190
 191 /* CCPSR: channel pointer status register */
 192 #define TALITOS_CCPSR                   0x10
 193 #define TALITOS_CCPSR_LO                0x14
 194 #define   TALITOS_CCPSR_LO_DOF          0x8000 /* double FF write oflow error */
 195 #define   TALITOS_CCPSR_LO_SOF          0x4000 /* single FF write oflow error */
 196 #define   TALITOS_CCPSR_LO_MDTE         0x2000 /* master data transfer error */
 197 #define   TALITOS_CCPSR_LO_SGDLZ        0x1000 /* s/g data len zero error */
 198 #define   TALITOS_CCPSR_LO_FPZ          0x0800 /* fetch ptr zero error */
 199 #define   TALITOS_CCPSR_LO_IDH          0x0400 /* illegal desc hdr error */
 200 #define   TALITOS_CCPSR_LO_IEU          0x0200 /* invalid EU error */
 201 #define   TALITOS_CCPSR_LO_EU           0x0100 /* EU error detected */
 202 #define   TALITOS_CCPSR_LO_GB           0x0080 /* gather boundary error */
 203 #define   TALITOS_CCPSR_LO_GRL          0x0040 /* gather return/length error */
 204 #define   TALITOS_CCPSR_LO_SB           0x0020 /* scatter boundary error */
 205 #define   TALITOS_CCPSR_LO_SRL          0x0010 /* scatter return/length error */
 206
 207 /* channel fetch fifo register */
 208 #define TALITOS_FF                      0x48
 209 #define TALITOS_FF_LO                   0x4c
 210
 211 /* current descriptor pointer register */
 212 #define TALITOS_CDPR                    0x40
 213 #define TALITOS_CDPR_LO                 0x44
 214
 215 /* descriptor buffer register */
 216 #define TALITOS_DESCBUF                 0x80
 217 #define TALITOS_DESCBUF_LO              0x84
 218
 219 /* gather link table */
 220 #define TALITOS_GATHER                  0xc0
 221 #define TALITOS_GATHER_LO               0xc4
 222
 223 /* scatter link table */
 224 #define TALITOS_SCATTER                 0xe0
 225 #define TALITOS_SCATTER_LO              0xe4
 226
 227 /* execution unit interrupt status registers */
 228 #define TALITOS_DEUISR                  0x2030 /* DES unit */
 229 #define TALITOS_DEUISR_LO               0x2034
 230 #define TALITOS_AESUISR                 0x4030 /* AES unit */
 231 #define TALITOS_AESUISR_LO              0x4034
 232 #define TALITOS_MDEUISR                 0x6030 /* message digest unit */
 233 #define TALITOS_MDEUISR_LO              0x6034
 234 #define TALITOS_MDEUICR                 0x6038 /* interrupt control */
 235 #define TALITOS_MDEUICR_LO              0x603c
 236 #define   TALITOS_MDEUICR_LO_ICE        0x4000 /* integrity check IRQ enable */
 237 #define TALITOS_AFEUISR                 0x8030 /* arc4 unit */
 238 #define TALITOS_AFEUISR_LO              0x8034
 239 #define TALITOS_RNGUISR                 0xa030 /* random number unit */
 240 #define TALITOS_RNGUISR_LO              0xa034
 241 #define TALITOS_RNGUSR                  0xa028 /* rng status */
 242 #define TALITOS_RNGUSR_LO               0xa02c
 243 #define   TALITOS_RNGUSR_LO_RD          0x1     /* reset done */
 244 #define   TALITOS_RNGUSR_LO_OFL         0xff0000/* output FIFO length */
 245 #define TALITOS_RNGUDSR                 0xa010  /* data size */
 246 #define TALITOS_RNGUDSR_LO              0xa014
 247 #define TALITOS_RNGU_FIFO               0xa800  /* output FIFO */
 248 #define TALITOS_RNGU_FIFO_LO            0xa804  /* output FIFO */
 249 #define TALITOS_RNGURCR                 0xa018  /* reset control */
 250 #define TALITOS_RNGURCR_LO              0xa01c
 251 #define   TALITOS_RNGURCR_LO_SR         0x1     /* software reset */
 252 #define TALITOS_PKEUISR                 0xc030 /* public key unit */
 253 #define TALITOS_PKEUISR_LO              0xc034
 254 #define TALITOS_KEUISR                  0xe030 /* kasumi unit */
 255 #define TALITOS_KEUISR_LO               0xe034
 256 #define TALITOS_CRCUISR                 0xf030 /* cyclic redundancy check unit*/
 257 #define TALITOS_CRCUISR_LO              0xf034
 258
 259 #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256       0x28
 260 #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512         0x48
 261
 262 /*
 263  * talitos descriptor header (hdr) bits
 264  */
 265
 266 /* written back when done */
 267 #define DESC_HDR_DONE                   cpu_to_be32(0xff000000)
 268 #define DESC_HDR_LO_ICCR1_MASK          cpu_to_be32(0x00180000)
 269 #define DESC_HDR_LO_ICCR1_PASS          cpu_to_be32(0x00080000)
 270 #define DESC_HDR_LO_ICCR1_FAIL          cpu_to_be32(0x00100000)
 271
 272 /* primary execution unit select */
 273 #define DESC_HDR_SEL0_MASK              cpu_to_be32(0xf0000000)
 274 #define DESC_HDR_SEL0_AFEU              cpu_to_be32(0x10000000)
 275 #define DESC_HDR_SEL0_DEU               cpu_to_be32(0x20000000)
 276 #define DESC_HDR_SEL0_MDEUA             cpu_to_be32(0x30000000)
 277 #define DESC_HDR_SEL0_MDEUB             cpu_to_be32(0xb0000000)
 278 #define DESC_HDR_SEL0_RNG               cpu_to_be32(0x40000000)
 279 #define DESC_HDR_SEL0_PKEU              cpu_to_be32(0x50000000)
 280 #define DESC_HDR_SEL0_AESU              cpu_to_be32(0x60000000)
 281 #define DESC_HDR_SEL0_KEU               cpu_to_be32(0x70000000)
 282 #define DESC_HDR_SEL0_CRCU              cpu_to_be32(0x80000000)
 283
 284 /* primary execution unit mode (MODE0) and derivatives */
 285 #define DESC_HDR_MODE0_ENCRYPT          cpu_to_be32(0x00100000)
 286 #define DESC_HDR_MODE0_AESU_CBC         cpu_to_be32(0x00200000)
 287 #define DESC_HDR_MODE0_DEU_CBC          cpu_to_be32(0x00400000)
 288 #define DESC_HDR_MODE0_DEU_3DES         cpu_to_be32(0x00200000)
 289 #define DESC_HDR_MODE0_MDEU_CONT        cpu_to_be32(0x08000000)
 290 #define DESC_HDR_MODE0_MDEU_INIT        cpu_to_be32(0x01000000)
 291 #define DESC_HDR_MODE0_MDEU_HMAC        cpu_to_be32(0x00800000)
 292 #define DESC_HDR_MODE0_MDEU_PAD         cpu_to_be32(0x00400000)
 293 #define DESC_HDR_MODE0_MDEU_SHA224      cpu_to_be32(0x00300000)
 294 #define DESC_HDR_MODE0_MDEU_MD5         cpu_to_be32(0x00200000)
 295 #define DESC_HDR_MODE0_MDEU_SHA256      cpu_to_be32(0x00100000)
 296 #define DESC_HDR_MODE0_MDEU_SHA1        cpu_to_be32(0x00000000)
 297 #define DESC_HDR_MODE0_MDEUB_SHA384     cpu_to_be32(0x00000000)
 298 #define DESC_HDR_MODE0_MDEUB_SHA512     cpu_to_be32(0x00200000)
 299 #define DESC_HDR_MODE0_MDEU_MD5_HMAC    (DESC_HDR_MODE0_MDEU_MD5 | \
 300                                          DESC_HDR_MODE0_MDEU_HMAC)
 301 #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
 302                                          DESC_HDR_MODE0_MDEU_HMAC)
 303 #define DESC_HDR_MODE0_MDEU_SHA1_HMAC   (DESC_HDR_MODE0_MDEU_SHA1 | \
 304                                          DESC_HDR_MODE0_MDEU_HMAC)
 305
 306 /* secondary execution unit select (SEL1) */
 307 #define DESC_HDR_SEL1_MASK              cpu_to_be32(0x000f0000)
 308 #define DESC_HDR_SEL1_MDEUA             cpu_to_be32(0x00030000)
 309 #define DESC_HDR_SEL1_MDEUB             cpu_to_be32(0x000b0000)
 310 #define DESC_HDR_SEL1_CRCU              cpu_to_be32(0x00080000)
 311
 312 /* secondary execution unit mode (MODE1) and derivatives */
 313 #define DESC_HDR_MODE1_MDEU_CICV        cpu_to_be32(0x00004000)
 314 #define DESC_HDR_MODE1_MDEU_INIT        cpu_to_be32(0x00001000)
 315 #define DESC_HDR_MODE1_MDEU_HMAC        cpu_to_be32(0x00000800)
 316 #define DESC_HDR_MODE1_MDEU_PAD         cpu_to_be32(0x00000400)
 317 #define DESC_HDR_MODE1_MDEU_SHA224      cpu_to_be32(0x00000300)
 318 #define DESC_HDR_MODE1_MDEU_MD5         cpu_to_be32(0x00000200)
 319 #define DESC_HDR_MODE1_MDEU_SHA256      cpu_to_be32(0x00000100)
 320 #define DESC_HDR_MODE1_MDEU_SHA1        cpu_to_be32(0x00000000)
 321 #define DESC_HDR_MODE1_MDEUB_SHA384     cpu_to_be32(0x00000000)
 322 #define DESC_HDR_MODE1_MDEUB_SHA512     cpu_to_be32(0x00000200)
 323 #define DESC_HDR_MODE1_MDEU_MD5_HMAC    (DESC_HDR_MODE1_MDEU_MD5 | \
 324                                          DESC_HDR_MODE1_MDEU_HMAC)
 325 #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
 326                                          DESC_HDR_MODE1_MDEU_HMAC)
 327 #define DESC_HDR_MODE1_MDEU_SHA1_HMAC   (DESC_HDR_MODE1_MDEU_SHA1 | \
 328                                          DESC_HDR_MODE1_MDEU_HMAC)
 329 #define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
 330                                          DESC_HDR_MODE1_MDEU_HMAC)
 331 #define DESC_HDR_MODE1_MDEUB_SHA384_HMAC        (DESC_HDR_MODE1_MDEUB_SHA384 | \
 332                                                  DESC_HDR_MODE1_MDEU_HMAC)
 333 #define DESC_HDR_MODE1_MDEUB_SHA512_HMAC        (DESC_HDR_MODE1_MDEUB_SHA512 | \
 334                                                  DESC_HDR_MODE1_MDEU_HMAC)
 335
 336 /* direction of overall data flow (DIR) */
 337 #define DESC_HDR_DIR_INBOUND            cpu_to_be32(0x00000002)
 338
 339 /* request done notification (DN) */
 340 #define DESC_HDR_DONE_NOTIFY            cpu_to_be32(0x00000001)
 341
 342 /* descriptor types */
 343 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP         cpu_to_be32(0 << 3)
 344 #define DESC_HDR_TYPE_IPSEC_ESP                 cpu_to_be32(1 << 3)
 345 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU   cpu_to_be32(2 << 3)
 346 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU        cpu_to_be32(4 << 3)
 347
 348 /* link table extent field bits */
 349 #define DESC_PTR_LNKTBL_JUMP                    0x80
 350 #define DESC_PTR_LNKTBL_RETURN                  0x02
 351 #define DESC_PTR_LNKTBL_NEXT                    0x01