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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / dma / mmp_tdma.c
blob33f96aaa80c759aff2f8098e2135dd6f1b67b90a
1 /*
2 * Driver For Marvell Two-channel DMA Engine
3 *
4 * Copyright: Marvell International Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 */
11
12 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/interrupt.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/dmaengine.h>
20 #include <linux/platform_device.h>
21 #include <linux/device.h>
22 #include <mach/regs-icu.h>
23 #include <linux/platform_data/dma-mmp_tdma.h>
24 #include <linux/of_device.h>
25
26 #include "dmaengine.h"
27
28 /*
29 * Two-Channel DMA registers
30 */
31 #define TDBCR 0x00 /* Byte Count */
32 #define TDSAR 0x10 /* Src Addr */
33 #define TDDAR 0x20 /* Dst Addr */
34 #define TDNDPR 0x30 /* Next Desc */
35 #define TDCR 0x40 /* Control */
36 #define TDCP 0x60 /* Priority*/
37 #define TDCDPR 0x70 /* Current Desc */
38 #define TDIMR 0x80 /* Int Mask */
39 #define TDISR 0xa0 /* Int Status */
40
41 /* Two-Channel DMA Control Register */
42 #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
43 #define TDCR_SSZ_12_BITS (0x1 << 22)
44 #define TDCR_SSZ_16_BITS (0x2 << 22)
45 #define TDCR_SSZ_20_BITS (0x3 << 22)
46 #define TDCR_SSZ_24_BITS (0x4 << 22)
47 #define TDCR_SSZ_32_BITS (0x5 << 22)
48 #define TDCR_SSZ_SHIFT (0x1 << 22)
49 #define TDCR_SSZ_MASK (0x7 << 22)
50 #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
51 #define TDCR_ABR (0x1 << 20) /* Channel Abort */
52 #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
53 #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
54 #define TDCR_CHANACT (0x1 << 14) /* Channel Active */
55 #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
56 #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
57 #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
58 #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
59 #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
60 #define TDCR_BURSTSZ_4B (0x0 << 6)
61 #define TDCR_BURSTSZ_8B (0x1 << 6)
62 #define TDCR_BURSTSZ_16B (0x3 << 6)
63 #define TDCR_BURSTSZ_32B (0x6 << 6)
64 #define TDCR_BURSTSZ_64B (0x7 << 6)
65 #define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
66 #define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
67 #define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
68 #define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
69 #define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
70 #define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
71 #define TDCR_BURSTSZ_128B (0x5 << 6)
72 #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
73 #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
74 #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
75 #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
76 #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
77 #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
78 #define TDCR_DSTDESCCONT (0x1 << 1)
79 #define TDCR_SRCDESTCONT (0x1 << 0)
80
81 /* Two-Channel DMA Int Mask Register */
82 #define TDIMR_COMP (0x1 << 0)
83
84 /* Two-Channel DMA Int Status Register */
85 #define TDISR_COMP (0x1 << 0)
86
87 /*
88 * Two-Channel DMA Descriptor Struct
89 * NOTE: desc's buf must be aligned to 16 bytes.
90 */
91 struct mmp_tdma_desc {
92 u32 byte_cnt;
93 u32 src_addr;
94 u32 dst_addr;
95 u32 nxt_desc;
96 };
97
98 enum mmp_tdma_type {
99 MMP_AUD_TDMA = 0,
100 PXA910_SQU,
101 };
102
103 #define TDMA_ALIGNMENT 3
104 #define TDMA_MAX_XFER_BYTES SZ_64K
105
106 struct mmp_tdma_chan {
107 struct device *dev;
108 struct dma_chan chan;
109 struct dma_async_tx_descriptor desc;
110 struct tasklet_struct tasklet;
111
112 struct mmp_tdma_desc *desc_arr;
113 phys_addr_t desc_arr_phys;
114 int desc_num;
115 enum dma_transfer_direction dir;
116 dma_addr_t dev_addr;
117 u32 burst_sz;
118 enum dma_slave_buswidth buswidth;
119 enum dma_status status;
120
121 int idx;
122 enum mmp_tdma_type type;
123 int irq;
124 void __iomem *reg_base;
125
126 size_t buf_len;
127 size_t period_len;
128 size_t pos;
129
130 struct gen_pool *pool;
131 };
132
133 #define TDMA_CHANNEL_NUM 2
134 struct mmp_tdma_device {
135 struct device *dev;
136 void __iomem *base;
137 struct dma_device device;
138 struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
139 };
140
141 #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
142
143 static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
144 {
145 writel(phys, tdmac->reg_base + TDNDPR);
146 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
147 tdmac->reg_base + TDCR);
148 }
149
150 static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
151 {
152 /* enable irq */
153 writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
154 /* enable dma chan */
155 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
156 tdmac->reg_base + TDCR);
157 tdmac->status = DMA_IN_PROGRESS;
158 }
159
160 static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac)
161 {
162 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
163 tdmac->reg_base + TDCR);
164
165 /* disable irq */
166 writel(0, tdmac->reg_base + TDIMR);
167
168 tdmac->status = DMA_COMPLETE;
169 }
170
171 static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac)
172 {
173 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
174 tdmac->reg_base + TDCR);
175 tdmac->status = DMA_IN_PROGRESS;
176 }
177
178 static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac)
179 {
180 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
181 tdmac->reg_base + TDCR);
182 tdmac->status = DMA_PAUSED;
183 }
184
185 static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac)
186 {
187 unsigned int tdcr = 0;
188
189 mmp_tdma_disable_chan(tdmac);
190
191 if (tdmac->dir == DMA_MEM_TO_DEV)
192 tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
193 else if (tdmac->dir == DMA_DEV_TO_MEM)
194 tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
195
196 if (tdmac->type == MMP_AUD_TDMA) {
197 tdcr |= TDCR_PACKMOD;
198
199 switch (tdmac->burst_sz) {
200 case 4:
201 tdcr |= TDCR_BURSTSZ_4B;
202 break;
203 case 8:
204 tdcr |= TDCR_BURSTSZ_8B;
205 break;
206 case 16:
207 tdcr |= TDCR_BURSTSZ_16B;
208 break;
209 case 32:
210 tdcr |= TDCR_BURSTSZ_32B;
211 break;
212 case 64:
213 tdcr |= TDCR_BURSTSZ_64B;
214 break;
215 case 128:
216 tdcr |= TDCR_BURSTSZ_128B;
217 break;
218 default:
219 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
220 return -EINVAL;
221 }
222
223 switch (tdmac->buswidth) {
224 case DMA_SLAVE_BUSWIDTH_1_BYTE:
225 tdcr |= TDCR_SSZ_8_BITS;
226 break;
227 case DMA_SLAVE_BUSWIDTH_2_BYTES:
228 tdcr |= TDCR_SSZ_16_BITS;
229 break;
230 case DMA_SLAVE_BUSWIDTH_4_BYTES:
231 tdcr |= TDCR_SSZ_32_BITS;
232 break;
233 default:
234 dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
235 return -EINVAL;
236 }
237 } else if (tdmac->type == PXA910_SQU) {
238 tdcr |= TDCR_SSPMOD;
239
240 switch (tdmac->burst_sz) {
241 case 1:
242 tdcr |= TDCR_BURSTSZ_SQU_1B;
243 break;
244 case 2:
245 tdcr |= TDCR_BURSTSZ_SQU_2B;
246 break;
247 case 4:
248 tdcr |= TDCR_BURSTSZ_SQU_4B;
249 break;
250 case 8:
251 tdcr |= TDCR_BURSTSZ_SQU_8B;
252 break;
253 case 16:
254 tdcr |= TDCR_BURSTSZ_SQU_16B;
255 break;
256 case 32:
257 tdcr |= TDCR_BURSTSZ_SQU_32B;
258 break;
259 default:
260 dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
261 return -EINVAL;
262 }
263 }
264
265 writel(tdcr, tdmac->reg_base + TDCR);
266 return 0;
267 }
268
269 static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
270 {
271 u32 reg = readl(tdmac->reg_base + TDISR);
272
273 if (reg & TDISR_COMP) {
274 /* clear irq */
275 reg &= ~TDISR_COMP;
276 writel(reg, tdmac->reg_base + TDISR);
277
278 return 0;
279 }
280 return -EAGAIN;
281 }
282
283 static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
284 {
285 struct mmp_tdma_chan *tdmac = dev_id;
286
287 if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
288 tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len;
289 tasklet_schedule(&tdmac->tasklet);
290 return IRQ_HANDLED;
291 } else
292 return IRQ_NONE;
293 }
294
295 static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
296 {
297 struct mmp_tdma_device *tdev = dev_id;
298 int i, ret;
299 int irq_num = 0;
300
301 for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
302 struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
303
304 ret = mmp_tdma_chan_handler(irq, tdmac);
305 if (ret == IRQ_HANDLED)
306 irq_num++;
307 }
308
309 if (irq_num)
310 return IRQ_HANDLED;
311 else
312 return IRQ_NONE;
313 }
314
315 static void dma_do_tasklet(unsigned long data)
316 {
317 struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data;
318
319 if (tdmac->desc.callback)
320 tdmac->desc.callback(tdmac->desc.callback_param);
321
322 }
323
324 static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
325 {
326 struct gen_pool *gpool;
327 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
328
329 gpool = tdmac->pool;
330 if (tdmac->desc_arr)
331 gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
332 size);
333 tdmac->desc_arr = NULL;
334
335 return;
336 }
337
338 static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
339 {
340 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
341
342 mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
343
344 return 0;
345 }
346
347 static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
348 {
349 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
350 int ret;
351
352 dma_async_tx_descriptor_init(&tdmac->desc, chan);
353 tdmac->desc.tx_submit = mmp_tdma_tx_submit;
354
355 if (tdmac->irq) {
356 ret = devm_request_irq(tdmac->dev, tdmac->irq,
357 mmp_tdma_chan_handler, 0, "tdma", tdmac);
358 if (ret)
359 return ret;
360 }
361 return 1;
362 }
363
364 static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
365 {
366 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
367
368 if (tdmac->irq)
369 devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
370 mmp_tdma_free_descriptor(tdmac);
371 return;
372 }
373
374 struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
375 {
376 struct gen_pool *gpool;
377 int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
378
379 gpool = tdmac->pool;
380 if (!gpool)
381 return NULL;
382
383 tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
384
385 return tdmac->desc_arr;
386 }
387
388 static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
389 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
390 size_t period_len, enum dma_transfer_direction direction,
391 unsigned long flags, void *context)
392 {
393 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
394 struct mmp_tdma_desc *desc;
395 int num_periods = buf_len / period_len;
396 int i = 0, buf = 0;
397
398 if (tdmac->status != DMA_COMPLETE)
399 return NULL;
400
401 if (period_len > TDMA_MAX_XFER_BYTES) {
402 dev_err(tdmac->dev,
403 "maximum period size exceeded: %d > %d\n",
404 period_len, TDMA_MAX_XFER_BYTES);
405 goto err_out;
406 }
407
408 tdmac->status = DMA_IN_PROGRESS;
409 tdmac->desc_num = num_periods;
410 desc = mmp_tdma_alloc_descriptor(tdmac);
411 if (!desc)
412 goto err_out;
413
414 while (buf < buf_len) {
415 desc = &tdmac->desc_arr[i];
416
417 if (i + 1 == num_periods)
418 desc->nxt_desc = tdmac->desc_arr_phys;
419 else
420 desc->nxt_desc = tdmac->desc_arr_phys +
421 sizeof(*desc) * (i + 1);
422
423 if (direction == DMA_MEM_TO_DEV) {
424 desc->src_addr = dma_addr;
425 desc->dst_addr = tdmac->dev_addr;
426 } else {
427 desc->src_addr = tdmac->dev_addr;
428 desc->dst_addr = dma_addr;
429 }
430 desc->byte_cnt = period_len;
431 dma_addr += period_len;
432 buf += period_len;
433 i++;
434 }
435
436 tdmac->buf_len = buf_len;
437 tdmac->period_len = period_len;
438 tdmac->pos = 0;
439
440 return &tdmac->desc;
441
442 err_out:
443 tdmac->status = DMA_ERROR;
444 return NULL;
445 }
446
447 static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
448 unsigned long arg)
449 {
450 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
451 struct dma_slave_config *dmaengine_cfg = (void *)arg;
452 int ret = 0;
453
454 switch (cmd) {
455 case DMA_TERMINATE_ALL:
456 mmp_tdma_disable_chan(tdmac);
457 break;
458 case DMA_PAUSE:
459 mmp_tdma_pause_chan(tdmac);
460 break;
461 case DMA_RESUME:
462 mmp_tdma_resume_chan(tdmac);
463 break;
464 case DMA_SLAVE_CONFIG:
465 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
466 tdmac->dev_addr = dmaengine_cfg->src_addr;
467 tdmac->burst_sz = dmaengine_cfg->src_maxburst;
468 tdmac->buswidth = dmaengine_cfg->src_addr_width;
469 } else {
470 tdmac->dev_addr = dmaengine_cfg->dst_addr;
471 tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
472 tdmac->buswidth = dmaengine_cfg->dst_addr_width;
473 }
474 tdmac->dir = dmaengine_cfg->direction;
475 return mmp_tdma_config_chan(tdmac);
476 default:
477 ret = -ENOSYS;
478 }
479
480 return ret;
481 }
482
483 static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
484 dma_cookie_t cookie, struct dma_tx_state *txstate)
485 {
486 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
487
488 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
489 tdmac->buf_len - tdmac->pos);
490
491 return tdmac->status;
492 }
493
494 static void mmp_tdma_issue_pending(struct dma_chan *chan)
495 {
496 struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
497
498 mmp_tdma_enable_chan(tdmac);
499 }
500
501 static int mmp_tdma_remove(struct platform_device *pdev)
502 {
503 struct mmp_tdma_device *tdev = platform_get_drvdata(pdev);
504
505 dma_async_device_unregister(&tdev->device);
506 return 0;
507 }
508
509 static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
510 int idx, int irq,
511 int type, struct gen_pool *pool)
512 {
513 struct mmp_tdma_chan *tdmac;
514
515 if (idx >= TDMA_CHANNEL_NUM) {
516 dev_err(tdev->dev, "too many channels for device!\n");
517 return -EINVAL;
518 }
519
520 /* alloc channel */
521 tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
522 if (!tdmac) {
523 dev_err(tdev->dev, "no free memory for DMA channels!\n");
524 return -ENOMEM;
525 }
526 if (irq)
527 tdmac->irq = irq;
528 tdmac->dev = tdev->dev;
529 tdmac->chan.device = &tdev->device;
530 tdmac->idx = idx;
531 tdmac->type = type;
532 tdmac->reg_base = tdev->base + idx * 4;
533 tdmac->pool = pool;
534 tdmac->status = DMA_COMPLETE;
535 tdev->tdmac[tdmac->idx] = tdmac;
536 tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac);
537
538 /* add the channel to tdma_chan list */
539 list_add_tail(&tdmac->chan.device_node,
540 &tdev->device.channels);
541 return 0;
542 }
543
544 static struct of_device_id mmp_tdma_dt_ids[] = {
545 { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
546 { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
547 {}
548 };
549 MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
550
551 static int mmp_tdma_probe(struct platform_device *pdev)
552 {
553 enum mmp_tdma_type type;
554 const struct of_device_id *of_id;
555 struct mmp_tdma_device *tdev;
556 struct resource *iores;
557 int i, ret;
558 int irq = 0, irq_num = 0;
559 int chan_num = TDMA_CHANNEL_NUM;
560 struct gen_pool *pool;
561
562 of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
563 if (of_id)
564 type = (enum mmp_tdma_type) of_id->data;
565 else
566 type = platform_get_device_id(pdev)->driver_data;
567
568 /* always have couple channels */
569 tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
570 if (!tdev)
571 return -ENOMEM;
572
573 tdev->dev = &pdev->dev;
574
575 for (i = 0; i < chan_num; i++) {
576 if (platform_get_irq(pdev, i) > 0)
577 irq_num++;
578 }
579
580 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
581 tdev->base = devm_ioremap_resource(&pdev->dev, iores);
582 if (IS_ERR(tdev->base))
583 return PTR_ERR(tdev->base);
584
585 INIT_LIST_HEAD(&tdev->device.channels);
586
587 if (pdev->dev.of_node)
588 pool = of_get_named_gen_pool(pdev->dev.of_node, "asram", 0);
589 else
590 pool = sram_get_gpool("asram");
591 if (!pool) {
592 dev_err(&pdev->dev, "asram pool not available\n");
593 return -ENOMEM;
594 }
595
596 if (irq_num != chan_num) {
597 irq = platform_get_irq(pdev, 0);
598 ret = devm_request_irq(&pdev->dev, irq,
599 mmp_tdma_int_handler, 0, "tdma", tdev);
600 if (ret)
601 return ret;
602 }
603
604 /* initialize channel parameters */
605 for (i = 0; i < chan_num; i++) {
606 irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
607 ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
608 if (ret)
609 return ret;
610 }
611
612 dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
613 dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
614 tdev->device.dev = &pdev->dev;
615 tdev->device.device_alloc_chan_resources =
616 mmp_tdma_alloc_chan_resources;
617 tdev->device.device_free_chan_resources =
618 mmp_tdma_free_chan_resources;
619 tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
620 tdev->device.device_tx_status = mmp_tdma_tx_status;
621 tdev->device.device_issue_pending = mmp_tdma_issue_pending;
622 tdev->device.device_control = mmp_tdma_control;
623 tdev->device.copy_align = TDMA_ALIGNMENT;
624
625 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
626 platform_set_drvdata(pdev, tdev);
627
628 ret = dma_async_device_register(&tdev->device);
629 if (ret) {
630 dev_err(tdev->device.dev, "unable to register\n");
631 return ret;
632 }
633
634 dev_info(tdev->device.dev, "initialized\n");
635 return 0;
636 }
637
638 static const struct platform_device_id mmp_tdma_id_table[] = {
639 { "mmp-adma", MMP_AUD_TDMA },
640 { "pxa910-squ", PXA910_SQU },
641 { },
642 };
643
644 static struct platform_driver mmp_tdma_driver = {
645 .driver = {
646 .name = "mmp-tdma",
647 .owner = THIS_MODULE,
648 .of_match_table = mmp_tdma_dt_ids,
649 },
650 .id_table = mmp_tdma_id_table,
651 .probe = mmp_tdma_probe,
652 .remove = mmp_tdma_remove,
653 };
654
655 module_platform_driver(mmp_tdma_driver);
656
657 MODULE_LICENSE("GPL");
658 MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
659 MODULE_ALIAS("platform:mmp-tdma");
660 MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
661 MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
Linux with added FPC-III support