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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / gpu / drm / gma500 / psb_drv.h
blob5ad6a03e477eae63aa8cc635981887febca71ac1
1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20 #ifndef _PSB_DRV_H_
21 #define _PSB_DRV_H_
22
23 #include <linux/kref.h>
24
25 #include <drm/drmP.h>
26 #include <drm/drm_global.h>
27 #include <drm/gma_drm.h>
28 #include "psb_reg.h"
29 #include "psb_intel_drv.h"
30 #include "gma_display.h"
31 #include "intel_bios.h"
32 #include "gtt.h"
33 #include "power.h"
34 #include "opregion.h"
35 #include "oaktrail.h"
36
37 /* Append new drm mode definition here, align with libdrm definition */
38 #define DRM_MODE_SCALE_NO_SCALE 2
39
40 enum {
41 CHIP_PSB_8108 = 0, /* Poulsbo */
42 CHIP_PSB_8109 = 1, /* Poulsbo */
43 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
44 CHIP_MFLD_0130 = 3, /* Medfield */
45 };
46
47 #define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108)
48 #define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100)
49 #define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)
50 #define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)
51
52 /*
53 * Driver definitions
54 */
55
56 #define DRIVER_NAME "gma500"
57 #define DRIVER_DESC "DRM driver for the Intel GMA500"
58
59 #define PSB_DRM_DRIVER_DATE "2011-06-06"
60 #define PSB_DRM_DRIVER_MAJOR 1
61 #define PSB_DRM_DRIVER_MINOR 0
62 #define PSB_DRM_DRIVER_PATCHLEVEL 0
63
64 /*
65 * Hardware offsets
66 */
67 #define PSB_VDC_OFFSET 0x00000000
68 #define PSB_VDC_SIZE 0x000080000
69 #define MRST_MMIO_SIZE 0x0000C0000
70 #define MDFLD_MMIO_SIZE 0x000100000
71 #define PSB_SGX_SIZE 0x8000
72 #define PSB_SGX_OFFSET 0x00040000
73 #define MRST_SGX_OFFSET 0x00080000
74 /*
75 * PCI resource identifiers
76 */
77 #define PSB_MMIO_RESOURCE 0
78 #define PSB_AUX_RESOURCE 0
79 #define PSB_GATT_RESOURCE 2
80 #define PSB_GTT_RESOURCE 3
81 /*
82 * PCI configuration
83 */
84 #define PSB_GMCH_CTRL 0x52
85 #define PSB_BSM 0x5C
86 #define _PSB_GMCH_ENABLED 0x4
87 #define PSB_PGETBL_CTL 0x2020
88 #define _PSB_PGETBL_ENABLED 0x00000001
89 #define PSB_SGX_2D_SLAVE_PORT 0x4000
90
91 /* To get rid of */
92 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
93 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
94
95 /*
96 * SGX side MMU definitions (these can probably go)
97 */
98
99 /*
100 * Flags for external memory type field.
101 */
102 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
103 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
104 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
105 /*
106 * PTE's and PDE's
107 */
108 #define PSB_PDE_MASK 0x003FFFFF
109 #define PSB_PDE_SHIFT 22
110 #define PSB_PTE_SHIFT 12
111 /*
112 * Cache control
113 */
114 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
115 #define PSB_PTE_WO 0x0002 /* Write only */
116 #define PSB_PTE_RO 0x0004 /* Read only */
117 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
118
119 /*
120 * VDC registers and bits
121 */
122 #define PSB_MSVDX_CLOCKGATING 0x2064
123 #define PSB_TOPAZ_CLOCKGATING 0x2068
124 #define PSB_HWSTAM 0x2098
125 #define PSB_INSTPM 0x20C0
126 #define PSB_INT_IDENTITY_R 0x20A4
127 #define _PSB_IRQ_ASLE (1<<0)
128 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
129 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
130 #define _PSB_DPST_PIPEB_FLAG (1<<4)
131 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
132 #define _PSB_VSYNC_PIPEB_FLAG (1<<5)
133 #define _PSB_DPST_PIPEA_FLAG (1<<6)
134 #define _PSB_PIPEA_EVENT_FLAG (1<<6)
135 #define _PSB_VSYNC_PIPEA_FLAG (1<<7)
136 #define _MDFLD_MIPIA_FLAG (1<<16)
137 #define _MDFLD_MIPIC_FLAG (1<<17)
138 #define _PSB_IRQ_DISP_HOTSYNC (1<<17)
139 #define _PSB_IRQ_SGX_FLAG (1<<18)
140 #define _PSB_IRQ_MSVDX_FLAG (1<<19)
141 #define _LNC_IRQ_TOPAZ_FLAG (1<<20)
142
143 #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
144 _PSB_VSYNC_PIPEB_FLAG)
145
146 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
147 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
148 _MDFLD_PIPEB_EVENT_FLAG | \
149 _PSB_PIPEA_EVENT_FLAG | \
150 _PSB_VSYNC_PIPEA_FLAG | \
151 _MDFLD_MIPIA_FLAG | \
152 _MDFLD_MIPIC_FLAG)
153 #define PSB_INT_IDENTITY_R 0x20A4
154 #define PSB_INT_MASK_R 0x20A8
155 #define PSB_INT_ENABLE_R 0x20A0
156
157 #define _PSB_MMU_ER_MASK 0x0001FF00
158 #define _PSB_MMU_ER_HOST (1 << 16)
159 #define GPIOA 0x5010
160 #define GPIOB 0x5014
161 #define GPIOC 0x5018
162 #define GPIOD 0x501c
163 #define GPIOE 0x5020
164 #define GPIOF 0x5024
165 #define GPIOG 0x5028
166 #define GPIOH 0x502c
167 #define GPIO_CLOCK_DIR_MASK (1 << 0)
168 #define GPIO_CLOCK_DIR_IN (0 << 1)
169 #define GPIO_CLOCK_DIR_OUT (1 << 1)
170 #define GPIO_CLOCK_VAL_MASK (1 << 2)
171 #define GPIO_CLOCK_VAL_OUT (1 << 3)
172 #define GPIO_CLOCK_VAL_IN (1 << 4)
173 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
174 #define GPIO_DATA_DIR_MASK (1 << 8)
175 #define GPIO_DATA_DIR_IN (0 << 9)
176 #define GPIO_DATA_DIR_OUT (1 << 9)
177 #define GPIO_DATA_VAL_MASK (1 << 10)
178 #define GPIO_DATA_VAL_OUT (1 << 11)
179 #define GPIO_DATA_VAL_IN (1 << 12)
180 #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
181
182 #define VCLK_DIVISOR_VGA0 0x6000
183 #define VCLK_DIVISOR_VGA1 0x6004
184 #define VCLK_POST_DIV 0x6010
185
186 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
187 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
188 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
189 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
190 #define PSB_COMM_USER_IRQ (1024 >> 2)
191 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
192 #define PSB_COMM_FW (2048 >> 2)
193
194 #define PSB_UIRQ_VISTEST 1
195 #define PSB_UIRQ_OOM_REPLY 2
196 #define PSB_UIRQ_FIRE_TA_REPLY 3
197 #define PSB_UIRQ_FIRE_RASTER_REPLY 4
198
199 #define PSB_2D_SIZE (256*1024*1024)
200 #define PSB_MAX_RELOC_PAGES 1024
201
202 #define PSB_LOW_REG_OFFS 0x0204
203 #define PSB_HIGH_REG_OFFS 0x0600
204
205 #define PSB_NUM_VBLANKS 2
206
207
208 #define PSB_2D_SIZE (256*1024*1024)
209 #define PSB_MAX_RELOC_PAGES 1024
210
211 #define PSB_LOW_REG_OFFS 0x0204
212 #define PSB_HIGH_REG_OFFS 0x0600
213
214 #define PSB_NUM_VBLANKS 2
215 #define PSB_WATCHDOG_DELAY (HZ * 2)
216 #define PSB_LID_DELAY (HZ / 10)
217
218 #define MDFLD_PNW_B0 0x04
219 #define MDFLD_PNW_C0 0x08
220
221 #define MDFLD_DSR_2D_3D_0 (1 << 0)
222 #define MDFLD_DSR_2D_3D_2 (1 << 1)
223 #define MDFLD_DSR_CURSOR_0 (1 << 2)
224 #define MDFLD_DSR_CURSOR_2 (1 << 3)
225 #define MDFLD_DSR_OVERLAY_0 (1 << 4)
226 #define MDFLD_DSR_OVERLAY_2 (1 << 5)
227 #define MDFLD_DSR_MIPI_CONTROL (1 << 6)
228 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
229 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
230 #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
231
232 #define MDFLD_DSR_RR 45
233 #define MDFLD_DPU_ENABLE (1 << 31)
234 #define MDFLD_DSR_FULLSCREEN (1 << 30)
235 #define MDFLD_DSR_DELAY (HZ / MDFLD_DSR_RR)
236
237 #define PSB_PWR_STATE_ON 1
238 #define PSB_PWR_STATE_OFF 2
239
240 #define PSB_PMPOLICY_NOPM 0
241 #define PSB_PMPOLICY_CLOCKGATING 1
242 #define PSB_PMPOLICY_POWERDOWN 2
243
244 #define PSB_PMSTATE_POWERUP 0
245 #define PSB_PMSTATE_CLOCKGATED 1
246 #define PSB_PMSTATE_POWERDOWN 2
247 #define PSB_PCIx_MSI_ADDR_LOC 0x94
248 #define PSB_PCIx_MSI_DATA_LOC 0x98
249
250 /* Medfield crystal settings */
251 #define KSEL_CRYSTAL_19 1
252 #define KSEL_BYPASS_19 5
253 #define KSEL_BYPASS_25 6
254 #define KSEL_BYPASS_83_100 7
255
256 struct opregion_header;
257 struct opregion_acpi;
258 struct opregion_swsci;
259 struct opregion_asle;
260
261 struct psb_intel_opregion {
262 struct opregion_header *header;
263 struct opregion_acpi *acpi;
264 struct opregion_swsci *swsci;
265 struct opregion_asle *asle;
266 void *vbt;
267 u32 __iomem *lid_state;
268 };
269
270 struct sdvo_device_mapping {
271 u8 initialized;
272 u8 dvo_port;
273 u8 slave_addr;
274 u8 dvo_wiring;
275 u8 i2c_pin;
276 u8 i2c_speed;
277 u8 ddc_pin;
278 };
279
280 struct intel_gmbus {
281 struct i2c_adapter adapter;
282 struct i2c_adapter *force_bit;
283 u32 reg0;
284 };
285
286 /*
287 * Register offset maps
288 */
289
290 struct psb_offset {
291 u32 fp0;
292 u32 fp1;
293 u32 cntr;
294 u32 conf;
295 u32 src;
296 u32 dpll;
297 u32 dpll_md;
298 u32 htotal;
299 u32 hblank;
300 u32 hsync;
301 u32 vtotal;
302 u32 vblank;
303 u32 vsync;
304 u32 stride;
305 u32 size;
306 u32 pos;
307 u32 surf;
308 u32 addr;
309 u32 base;
310 u32 status;
311 u32 linoff;
312 u32 tileoff;
313 u32 palette;
314 };
315
316 /*
317 * Register save state. This is used to hold the context when the
318 * device is powered off. In the case of Oaktrail this can (but does not
319 * yet) include screen blank. Operations occuring during the save
320 * update the register cache instead.
321 */
322
323 /*
324 * Common status for pipes.
325 */
326 struct psb_pipe {
327 u32 fp0;
328 u32 fp1;
329 u32 cntr;
330 u32 conf;
331 u32 src;
332 u32 dpll;
333 u32 dpll_md;
334 u32 htotal;
335 u32 hblank;
336 u32 hsync;
337 u32 vtotal;
338 u32 vblank;
339 u32 vsync;
340 u32 stride;
341 u32 size;
342 u32 pos;
343 u32 base;
344 u32 surf;
345 u32 addr;
346 u32 status;
347 u32 linoff;
348 u32 tileoff;
349 u32 palette[256];
350 };
351
352 struct psb_state {
353 uint32_t saveVCLK_DIVISOR_VGA0;
354 uint32_t saveVCLK_DIVISOR_VGA1;
355 uint32_t saveVCLK_POST_DIV;
356 uint32_t saveVGACNTRL;
357 uint32_t saveADPA;
358 uint32_t saveLVDS;
359 uint32_t saveDVOA;
360 uint32_t saveDVOB;
361 uint32_t saveDVOC;
362 uint32_t savePP_ON;
363 uint32_t savePP_OFF;
364 uint32_t savePP_CONTROL;
365 uint32_t savePP_CYCLE;
366 uint32_t savePFIT_CONTROL;
367 uint32_t saveCLOCKGATING;
368 uint32_t saveDSPARB;
369 uint32_t savePFIT_AUTO_RATIOS;
370 uint32_t savePFIT_PGM_RATIOS;
371 uint32_t savePP_ON_DELAYS;
372 uint32_t savePP_OFF_DELAYS;
373 uint32_t savePP_DIVISOR;
374 uint32_t saveBCLRPAT_A;
375 uint32_t saveBCLRPAT_B;
376 uint32_t savePERF_MODE;
377 uint32_t saveDSPFW1;
378 uint32_t saveDSPFW2;
379 uint32_t saveDSPFW3;
380 uint32_t saveDSPFW4;
381 uint32_t saveDSPFW5;
382 uint32_t saveDSPFW6;
383 uint32_t saveCHICKENBIT;
384 uint32_t saveDSPACURSOR_CTRL;
385 uint32_t saveDSPBCURSOR_CTRL;
386 uint32_t saveDSPACURSOR_BASE;
387 uint32_t saveDSPBCURSOR_BASE;
388 uint32_t saveDSPACURSOR_POS;
389 uint32_t saveDSPBCURSOR_POS;
390 uint32_t saveOV_OVADD;
391 uint32_t saveOV_OGAMC0;
392 uint32_t saveOV_OGAMC1;
393 uint32_t saveOV_OGAMC2;
394 uint32_t saveOV_OGAMC3;
395 uint32_t saveOV_OGAMC4;
396 uint32_t saveOV_OGAMC5;
397 uint32_t saveOVC_OVADD;
398 uint32_t saveOVC_OGAMC0;
399 uint32_t saveOVC_OGAMC1;
400 uint32_t saveOVC_OGAMC2;
401 uint32_t saveOVC_OGAMC3;
402 uint32_t saveOVC_OGAMC4;
403 uint32_t saveOVC_OGAMC5;
404
405 /* DPST register save */
406 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
407 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
408 uint32_t savePWM_CONTROL_LOGIC;
409 };
410
411 struct medfield_state {
412 uint32_t saveMIPI;
413 uint32_t saveMIPI_C;
414
415 uint32_t savePFIT_CONTROL;
416 uint32_t savePFIT_PGM_RATIOS;
417 uint32_t saveHDMIPHYMISCCTL;
418 uint32_t saveHDMIB_CONTROL;
419 };
420
421 struct cdv_state {
422 uint32_t saveDSPCLK_GATE_D;
423 uint32_t saveRAMCLK_GATE_D;
424 uint32_t saveDSPARB;
425 uint32_t saveDSPFW[6];
426 uint32_t saveADPA;
427 uint32_t savePP_CONTROL;
428 uint32_t savePFIT_PGM_RATIOS;
429 uint32_t saveLVDS;
430 uint32_t savePFIT_CONTROL;
431 uint32_t savePP_ON_DELAYS;
432 uint32_t savePP_OFF_DELAYS;
433 uint32_t savePP_CYCLE;
434 uint32_t saveVGACNTRL;
435 uint32_t saveIER;
436 uint32_t saveIMR;
437 u8 saveLBB;
438 };
439
440 struct psb_save_area {
441 struct psb_pipe pipe[3];
442 uint32_t saveBSM;
443 uint32_t saveVBT;
444 union {
445 struct psb_state psb;
446 struct medfield_state mdfld;
447 struct cdv_state cdv;
448 };
449 uint32_t saveBLC_PWM_CTL2;
450 uint32_t saveBLC_PWM_CTL;
451 };
452
453 struct psb_ops;
454
455 #define PSB_NUM_PIPE 3
456
457 struct drm_psb_private {
458 struct drm_device *dev;
459 struct pci_dev *aux_pdev; /* Currently only used by mrst */
460 const struct psb_ops *ops;
461 const struct psb_offset *regmap;
462
463 struct child_device_config *child_dev;
464 int child_dev_num;
465
466 struct psb_gtt gtt;
467
468 /* GTT Memory manager */
469 struct psb_gtt_mm *gtt_mm;
470 struct page *scratch_page;
471 u32 __iomem *gtt_map;
472 uint32_t stolen_base;
473 u8 __iomem *vram_addr;
474 unsigned long vram_stolen_size;
475 int gtt_initialized;
476 u16 gmch_ctrl; /* Saved GTT setup */
477 u32 pge_ctl;
478
479 struct mutex gtt_mutex;
480 struct resource *gtt_mem; /* Our PCI resource */
481
482 struct psb_mmu_driver *mmu;
483 struct psb_mmu_pd *pf_pd;
484
485 /*
486 * Register base
487 */
488
489 uint8_t __iomem *sgx_reg;
490 uint8_t __iomem *vdc_reg;
491 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
492 uint32_t gatt_free_offset;
493
494 /*
495 * Fencing / irq.
496 */
497
498 uint32_t vdc_irq_mask;
499 uint32_t pipestat[PSB_NUM_PIPE];
500
501 spinlock_t irqmask_lock;
502
503 /*
504 * Power
505 */
506
507 bool suspended;
508 bool display_power;
509 int display_count;
510
511 /*
512 * Modesetting
513 */
514 struct psb_intel_mode_device mode_dev;
515 bool modeset; /* true if we have done the mode_device setup */
516
517 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
518 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
519 uint32_t num_pipe;
520
521 /*
522 * OSPM info (Power management base) (can go ?)
523 */
524 uint32_t ospm_base;
525
526 /*
527 * Sizes info
528 */
529
530 u32 fuse_reg_value;
531 u32 video_device_fuse;
532
533 /* PCI revision ID for B0:D2:F0 */
534 uint8_t platform_rev_id;
535
536 /* gmbus */
537 struct intel_gmbus *gmbus;
538 uint8_t __iomem *gmbus_reg;
539
540 /* Used by SDVO */
541 int crt_ddc_pin;
542 /* FIXME: The mappings should be parsed from bios but for now we can
543 pretend there are no mappings available */
544 struct sdvo_device_mapping sdvo_mappings[2];
545 u32 hotplug_supported_mask;
546 struct drm_property *broadcast_rgb_property;
547 struct drm_property *force_audio_property;
548
549 /*
550 * LVDS info
551 */
552 int backlight_duty_cycle; /* restore backlight to this value */
553 bool panel_wants_dither;
554 struct drm_display_mode *panel_fixed_mode;
555 struct drm_display_mode *lfp_lvds_vbt_mode;
556 struct drm_display_mode *sdvo_lvds_vbt_mode;
557
558 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
559 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
560
561 /* Feature bits from the VBIOS */
562 unsigned int int_tv_support:1;
563 unsigned int lvds_dither:1;
564 unsigned int lvds_vbt:1;
565 unsigned int int_crt_support:1;
566 unsigned int lvds_use_ssc:1;
567 int lvds_ssc_freq;
568 bool is_lvds_on;
569 bool is_mipi_on;
570 u32 mipi_ctrl_display;
571
572 unsigned int core_freq;
573 uint32_t iLVDS_enable;
574
575 /* Runtime PM state */
576 int rpm_enabled;
577
578 /* MID specific */
579 bool has_gct;
580 struct oaktrail_gct_data gct_data;
581
582 /* Oaktrail HDMI state */
583 struct oaktrail_hdmi_dev *hdmi_priv;
584
585 /*
586 * Register state
587 */
588
589 struct psb_save_area regs;
590
591 /* MSI reg save */
592 uint32_t msi_addr;
593 uint32_t msi_data;
594
595 /*
596 * Hotplug handling
597 */
598
599 struct work_struct hotplug_work;
600
601 /*
602 * LID-Switch
603 */
604 spinlock_t lid_lock;
605 struct timer_list lid_timer;
606 struct psb_intel_opregion opregion;
607 u32 lid_last_state;
608
609 /*
610 * Watchdog
611 */
612
613 uint32_t apm_reg;
614 uint16_t apm_base;
615
616 /*
617 * Used for modifying backlight from
618 * xrandr -- consider removing and using HAL instead
619 */
620 struct backlight_device *backlight_device;
621 struct drm_property *backlight_property;
622 bool backlight_enabled;
623 int backlight_level;
624 uint32_t blc_adj1;
625 uint32_t blc_adj2;
626
627 void *fbdev;
628
629 /* 2D acceleration */
630 spinlock_t lock_2d;
631
632 /*
633 * Panel brightness
634 */
635 int brightness;
636 int brightness_adjusted;
637
638 bool dsr_enable;
639 u32 dsr_fb_update;
640 bool dpi_panel_on[3];
641 void *dsi_configs[2];
642 u32 bpp;
643 u32 bpp2;
644
645 u32 pipeconf[3];
646 u32 dspcntr[3];
647
648 int mdfld_panel_id;
649
650 bool dplla_96mhz; /* DPLL data from the VBT */
651
652 struct {
653 int rate;
654 int lanes;
655 int preemphasis;
656 int vswing;
657
658 bool initialized;
659 bool support;
660 int bpp;
661 struct edp_power_seq pps;
662 } edp;
663 uint8_t panel_type;
664 };
665
666
667 /*
668 * Operations for each board type
669 */
670
671 struct psb_ops {
672 const char *name;
673 unsigned int accel_2d:1;
674 int pipes; /* Number of output pipes */
675 int crtcs; /* Number of CRTCs */
676 int sgx_offset; /* Base offset of SGX device */
677 int hdmi_mask; /* Mask of HDMI CRTCs */
678 int lvds_mask; /* Mask of LVDS CRTCs */
679 int sdvo_mask; /* Mask of SDVO CRTCs */
680 int cursor_needs_phys; /* If cursor base reg need physical address */
681
682 /* Sub functions */
683 struct drm_crtc_helper_funcs const *crtc_helper;
684 struct drm_crtc_funcs const *crtc_funcs;
685 const struct gma_clock_funcs *clock_funcs;
686
687 /* Setup hooks */
688 int (*chip_setup)(struct drm_device *dev);
689 void (*chip_teardown)(struct drm_device *dev);
690 /* Optional helper caller after modeset */
691 void (*errata)(struct drm_device *dev);
692
693 /* Display management hooks */
694 int (*output_init)(struct drm_device *dev);
695 int (*hotplug)(struct drm_device *dev);
696 void (*hotplug_enable)(struct drm_device *dev, bool on);
697 /* Power management hooks */
698 void (*init_pm)(struct drm_device *dev);
699 int (*save_regs)(struct drm_device *dev);
700 int (*restore_regs)(struct drm_device *dev);
701 int (*power_up)(struct drm_device *dev);
702 int (*power_down)(struct drm_device *dev);
703 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
704 void (*disable_sr)(struct drm_device *dev);
705
706 void (*lvds_bl_power)(struct drm_device *dev, bool on);
707 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
708 /* Backlight */
709 int (*backlight_init)(struct drm_device *dev);
710 #endif
711 int i2c_bus; /* I2C bus identifier for Moorestown */
712 };
713
714
715
716 struct psb_mmu_driver;
717
718 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
719 extern int drm_pick_crtcs(struct drm_device *dev);
720
721 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
722 {
723 return (struct drm_psb_private *) dev->dev_private;
724 }
725
726 /*
727 * MMU stuff.
728 */
729
730 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
731 int trap_pagefaults,
732 int invalid_type,
733 struct drm_psb_private *dev_priv);
734 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
735 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
736 *driver);
737 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
738 uint32_t gtt_start, uint32_t gtt_pages);
739 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
740 int trap_pagefaults,
741 int invalid_type);
742 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
743 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
744 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
745 unsigned long address,
746 uint32_t num_pages);
747 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
748 uint32_t start_pfn,
749 unsigned long address,
750 uint32_t num_pages, int type);
751 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
752 unsigned long *pfn);
753
754 /*
755 * Enable / disable MMU for different requestors.
756 */
757
758
759 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
760 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
761 unsigned long address, uint32_t num_pages,
762 uint32_t desired_tile_stride,
763 uint32_t hw_tile_stride, int type);
764 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
765 unsigned long address, uint32_t num_pages,
766 uint32_t desired_tile_stride,
767 uint32_t hw_tile_stride);
768 /*
769 *psb_irq.c
770 */
771
772 extern irqreturn_t psb_irq_handler(int irq, void *arg);
773 extern int psb_irq_enable_dpst(struct drm_device *dev);
774 extern int psb_irq_disable_dpst(struct drm_device *dev);
775 extern void psb_irq_preinstall(struct drm_device *dev);
776 extern int psb_irq_postinstall(struct drm_device *dev);
777 extern void psb_irq_uninstall(struct drm_device *dev);
778 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
779 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
780
781 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
782 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
783 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
784 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
785 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
786 void
787 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
788
789 void
790 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
791
792 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
793
794 /*
795 * framebuffer.c
796 */
797 extern int psbfb_probed(struct drm_device *dev);
798 extern int psbfb_remove(struct drm_device *dev,
799 struct drm_framebuffer *fb);
800 /*
801 * accel_2d.c
802 */
803 extern void psbfb_copyarea(struct fb_info *info,
804 const struct fb_copyarea *region);
805 extern int psbfb_sync(struct fb_info *info);
806 extern void psb_spank(struct drm_psb_private *dev_priv);
807
808 /*
809 * psb_reset.c
810 */
811
812 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
813 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
814 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
815
816 /* modesetting */
817 extern void psb_modeset_init(struct drm_device *dev);
818 extern void psb_modeset_cleanup(struct drm_device *dev);
819 extern int psb_fbdev_init(struct drm_device *dev);
820
821 /* backlight.c */
822 int gma_backlight_init(struct drm_device *dev);
823 void gma_backlight_exit(struct drm_device *dev);
824 void gma_backlight_disable(struct drm_device *dev);
825 void gma_backlight_enable(struct drm_device *dev);
826 void gma_backlight_set(struct drm_device *dev, int v);
827
828 /* oaktrail_crtc.c */
829 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
830
831 /* oaktrail_lvds.c */
832 extern void oaktrail_lvds_init(struct drm_device *dev,
833 struct psb_intel_mode_device *mode_dev);
834
835 /* psb_intel_display.c */
836 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
837 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
838
839 /* psb_intel_lvds.c */
840 extern const struct drm_connector_helper_funcs
841 psb_intel_lvds_connector_helper_funcs;
842 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
843
844 /* gem.c */
845 extern void psb_gem_free_object(struct drm_gem_object *obj);
846 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
847 struct drm_file *file);
848 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
849 struct drm_mode_create_dumb *args);
850 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
851 uint32_t handle, uint64_t *offset);
852 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
853 extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
854 struct drm_file *file);
855 extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file);
857
858 /* psb_device.c */
859 extern const struct psb_ops psb_chip_ops;
860
861 /* oaktrail_device.c */
862 extern const struct psb_ops oaktrail_chip_ops;
863
864 /* mdlfd_device.c */
865 extern const struct psb_ops mdfld_chip_ops;
866
867 /* cdv_device.c */
868 extern const struct psb_ops cdv_chip_ops;
869
870 /*
871 * Debug print bits setting
872 */
873 #define PSB_D_GENERAL (1 << 0)
874 #define PSB_D_INIT (1 << 1)
875 #define PSB_D_IRQ (1 << 2)
876 #define PSB_D_ENTRY (1 << 3)
877 /* debug the get H/V BP/FP count */
878 #define PSB_D_HV (1 << 4)
879 #define PSB_D_DBI_BF (1 << 5)
880 #define PSB_D_PM (1 << 6)
881 #define PSB_D_RENDER (1 << 7)
882 #define PSB_D_REG (1 << 8)
883 #define PSB_D_MSVDX (1 << 9)
884 #define PSB_D_TOPAZ (1 << 10)
885
886 extern int drm_idle_check_interval;
887
888 /*
889 * Utilities
890 */
891
892 static inline u32 MRST_MSG_READ32(uint port, uint offset)
893 {
894 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
895 uint32_t ret_val = 0;
896 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
897 pci_write_config_dword(pci_root, 0xD0, mcr);
898 pci_read_config_dword(pci_root, 0xD4, &ret_val);
899 pci_dev_put(pci_root);
900 return ret_val;
901 }
902 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
903 {
904 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
905 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
906 pci_write_config_dword(pci_root, 0xD4, value);
907 pci_write_config_dword(pci_root, 0xD0, mcr);
908 pci_dev_put(pci_root);
909 }
910 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
911 {
912 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
913 uint32_t ret_val = 0;
914 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
915 pci_write_config_dword(pci_root, 0xD0, mcr);
916 pci_read_config_dword(pci_root, 0xD4, &ret_val);
917 pci_dev_put(pci_root);
918 return ret_val;
919 }
920 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
921 {
922 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
923 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
924 pci_write_config_dword(pci_root, 0xD4, value);
925 pci_write_config_dword(pci_root, 0xD0, mcr);
926 pci_dev_put(pci_root);
927 }
928
929 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
930 {
931 struct drm_psb_private *dev_priv = dev->dev_private;
932 return ioread32(dev_priv->vdc_reg + reg);
933 }
934
935 static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
936 {
937 struct drm_psb_private *dev_priv = dev->dev_private;
938 return ioread32(dev_priv->aux_reg + reg);
939 }
940
941 #define REG_READ(reg) REGISTER_READ(dev, (reg))
942 #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
943
944 /* Useful for post reads */
945 static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
946 uint32_t reg, int aux)
947 {
948 uint32_t val;
949
950 if (aux)
951 val = REG_READ_AUX(reg);
952 else
953 val = REG_READ(reg);
954
955 return val;
956 }
957
958 #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
959
960 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
961 uint32_t val)
962 {
963 struct drm_psb_private *dev_priv = dev->dev_private;
964 iowrite32((val), dev_priv->vdc_reg + (reg));
965 }
966
967 static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
968 uint32_t val)
969 {
970 struct drm_psb_private *dev_priv = dev->dev_private;
971 iowrite32((val), dev_priv->aux_reg + (reg));
972 }
973
974 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
975 #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
976
977 static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
978 uint32_t val, int aux)
979 {
980 if (aux)
981 REG_WRITE_AUX(reg, val);
982 else
983 REG_WRITE(reg, val);
984 }
985
986 #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
987
988 static inline void REGISTER_WRITE16(struct drm_device *dev,
989 uint32_t reg, uint32_t val)
990 {
991 struct drm_psb_private *dev_priv = dev->dev_private;
992 iowrite16((val), dev_priv->vdc_reg + (reg));
993 }
994
995 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
996
997 static inline void REGISTER_WRITE8(struct drm_device *dev,
998 uint32_t reg, uint32_t val)
999 {
1000 struct drm_psb_private *dev_priv = dev->dev_private;
1001 iowrite8((val), dev_priv->vdc_reg + (reg));
1002 }
1003
1004 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
1005
1006 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
1007 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
1008
1009 /* #define TRAP_SGX_PM_FAULT 1 */
1010 #ifdef TRAP_SGX_PM_FAULT
1011 #define PSB_RSGX32(_offs) \
1012 ({ \
1013 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
1014 printk(KERN_ERR \
1015 "access sgx when it's off!! (READ) %s, %d\n", \
1016 __FILE__, __LINE__); \
1017 melay(1000); \
1018 } \
1019 ioread32(dev_priv->sgx_reg + (_offs)); \
1020 })
1021 #else
1022 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
1023 #endif
1024 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
1025
1026 #define MSVDX_REG_DUMP 0
1027
1028 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1029 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
1030
1031 #endif
Linux with added FPC-III support