drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/i2c.h>
  29 #include <linux/hdmi.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36
  37 /**
  38  * _wait_for - magic (register) wait macro
  39  *
  40  * Does the right thing for modeset paths when run under kdgb or similar atomic
  41  * contexts. Note that it's important that we check the condition again after
  42  * having timed out, since the timeout could be due to preemption or similar and
  43  * we've never had a chance to check the condition before the timeout.
  44  */
  45 #define _wait_for(COND, MS, W) ({ \
  46         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  47         int ret__ = 0;                                                  \
  48         while (!(COND)) {                                               \
  49                 if (time_after(jiffies, timeout__)) {                   \
  50                         if (!(COND))                                    \
  51                                 ret__ = -ETIMEDOUT;                     \
  52                         break;                                          \
  53                 }                                                       \
  54                 if (W && drm_can_sleep())  {                            \
  55                         msleep(W);                                      \
  56                 } else {                                                \
  57                         cpu_relax();                                    \
  58                 }                                                       \
  59         }                                                               \
  60         ret__;                                                          \
  61 })
  62
  63 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  64 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  65 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  66                                                DIV_ROUND_UP((US), 1000), 0)
  67
  68 #define KHz(x) (1000 * (x))
  69 #define MHz(x) KHz(1000 * (x))
  70
  71 /*
  72  * Display related stuff
  73  */
  74
  75 /* store information about an Ixxx DVO */
  76 /* The i830->i865 use multiple DVOs with multiple i2cs */
  77 /* the i915, i945 have a single sDVO i2c bus - which is different */
  78 #define MAX_OUTPUTS 6
  79 /* maximum connectors per crtcs in the mode set */
  80
  81 #define INTEL_I2C_BUS_DVO 1
  82 #define INTEL_I2C_BUS_SDVO 2
  83
  84 /* these are outputs from the chip - integrated only
  85    external chips are via DVO or SDVO output */
  86 #define INTEL_OUTPUT_UNUSED 0
  87 #define INTEL_OUTPUT_ANALOG 1
  88 #define INTEL_OUTPUT_DVO 2
  89 #define INTEL_OUTPUT_SDVO 3
  90 #define INTEL_OUTPUT_LVDS 4
  91 #define INTEL_OUTPUT_TVOUT 5
  92 #define INTEL_OUTPUT_HDMI 6
  93 #define INTEL_OUTPUT_DISPLAYPORT 7
  94 #define INTEL_OUTPUT_EDP 8
  95 #define INTEL_OUTPUT_DSI 9
  96 #define INTEL_OUTPUT_UNKNOWN 10
  97
  98 #define INTEL_DVO_CHIP_NONE 0
  99 #define INTEL_DVO_CHIP_LVDS 1
 100 #define INTEL_DVO_CHIP_TMDS 2
 101 #define INTEL_DVO_CHIP_TVOUT 4
 102
 103 #define INTEL_DSI_COMMAND_MODE  0
 104 #define INTEL_DSI_VIDEO_MODE    1
 105
 106 struct intel_framebuffer {
 107         struct drm_framebuffer base;
 108         struct drm_i915_gem_object *obj;
 109 };
 110
 111 struct intel_fbdev {
 112         struct drm_fb_helper helper;
 113         struct intel_framebuffer ifb;
 114         struct list_head fbdev_list;
 115         struct drm_display_mode *our_mode;
 116 };
 117
 118 struct intel_encoder {
 119         struct drm_encoder base;
 120         /*
 121          * The new crtc this encoder will be driven from. Only differs from
 122          * base->crtc while a modeset is in progress.
 123          */
 124         struct intel_crtc *new_crtc;
 125
 126         int type;
 127         /*
 128          * Intel hw has only one MUX where encoders could be clone, hence a
 129          * simple flag is enough to compute the possible_clones mask.
 130          */
 131         bool cloneable;
 132         bool connectors_active;
 133         void (*hot_plug)(struct intel_encoder *);
 134         bool (*compute_config)(struct intel_encoder *,
 135                                struct intel_crtc_config *);
 136         void (*pre_pll_enable)(struct intel_encoder *);
 137         void (*pre_enable)(struct intel_encoder *);
 138         void (*enable)(struct intel_encoder *);
 139         void (*mode_set)(struct intel_encoder *intel_encoder);
 140         void (*disable)(struct intel_encoder *);
 141         void (*post_disable)(struct intel_encoder *);
 142         /* Read out the current hw state of this connector, returning true if
 143          * the encoder is active. If the encoder is enabled it also set the pipe
 144          * it is connected to in the pipe parameter. */
 145         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 146         /* Reconstructs the equivalent mode flags for the current hardware
 147          * state. This must be called _after_ display->get_pipe_config has
 148          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 149          * be set correctly before calling this function. */
 150         void (*get_config)(struct intel_encoder *,
 151                            struct intel_crtc_config *pipe_config);
 152         int crtc_mask;
 153         enum hpd_pin hpd_pin;
 154 };
 155
 156 struct intel_panel {
 157         struct drm_display_mode *fixed_mode;
 158         struct drm_display_mode *downclock_mode;
 159         int fitting_mode;
 160
 161         /* backlight */
 162         struct {
 163                 bool present;
 164                 u32 level;
 165                 u32 max;
 166                 bool enabled;
 167                 bool combination_mode;  /* gen 2/4 only */
 168                 bool active_low_pwm;
 169                 struct backlight_device *device;
 170         } backlight;
 171 };
 172
 173 struct intel_connector {
 174         struct drm_connector base;
 175         /*
 176          * The fixed encoder this connector is connected to.
 177          */
 178         struct intel_encoder *encoder;
 179
 180         /*
 181          * The new encoder this connector will be driven. Only differs from
 182          * encoder while a modeset is in progress.
 183          */
 184         struct intel_encoder *new_encoder;
 185
 186         /* Reads out the current hw, returning true if the connector is enabled
 187          * and active (i.e. dpms ON state). */
 188         bool (*get_hw_state)(struct intel_connector *);
 189
 190         /* Panel info for eDP and LVDS */
 191         struct intel_panel panel;
 192
 193         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 194         struct edid *edid;
 195
 196         /* since POLL and HPD connectors may use the same HPD line keep the native
 197            state of connector->polled in case hotplug storm detection changes it */
 198         u8 polled;
 199 };
 200
 201 typedef struct dpll {
 202         /* given values */
 203         int n;
 204         int m1, m2;
 205         int p1, p2;
 206         /* derived values */
 207         int     dot;
 208         int     vco;
 209         int     m;
 210         int     p;
 211 } intel_clock_t;
 212
 213 struct intel_crtc_config {
 214         /**
 215          * quirks - bitfield with hw state readout quirks
 216          *
 217          * For various reasons the hw state readout code might not be able to
 218          * completely faithfully read out the current state. These cases are
 219          * tracked with quirk flags so that fastboot and state checker can act
 220          * accordingly.
 221          */
 222 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
 223         unsigned long quirks;
 224
 225         /* User requested mode, only valid as a starting point to
 226          * compute adjusted_mode, except in the case of (S)DVO where
 227          * it's also for the output timings of the (S)DVO chip.
 228          * adjusted_mode will then correspond to the S(DVO) chip's
 229          * preferred input timings. */
 230         struct drm_display_mode requested_mode;
 231         /* Actual pipe timings ie. what we program into the pipe timing
 232          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
 233         struct drm_display_mode adjusted_mode;
 234
 235         /* Pipe source size (ie. panel fitter input size)
 236          * All planes will be positioned inside this space,
 237          * and get clipped at the edges. */
 238         int pipe_src_w, pipe_src_h;
 239
 240         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 241          * between pch encoders and cpu encoders. */
 242         bool has_pch_encoder;
 243
 244         /* CPU Transcoder for the pipe. Currently this can only differ from the
 245          * pipe on Haswell (where we have a special eDP transcoder). */
 246         enum transcoder cpu_transcoder;
 247
 248         /*
 249          * Use reduced/limited/broadcast rbg range, compressing from the full
 250          * range fed into the crtcs.
 251          */
 252         bool limited_color_range;
 253
 254         /* DP has a bunch of special case unfortunately, so mark the pipe
 255          * accordingly. */
 256         bool has_dp_encoder;
 257
 258         /*
 259          * Enable dithering, used when the selected pipe bpp doesn't match the
 260          * plane bpp.
 261          */
 262         bool dither;
 263
 264         /* Controls for the clock computation, to override various stages. */
 265         bool clock_set;
 266
 267         /* SDVO TV has a bunch of special case. To make multifunction encoders
 268          * work correctly, we need to track this at runtime.*/
 269         bool sdvo_tv_clock;
 270
 271         /*
 272          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 273          * required. This is set in the 2nd loop of calling encoder's
 274          * ->compute_config if the first pick doesn't work out.
 275          */
 276         bool bw_constrained;
 277
 278         /* Settings for the intel dpll used on pretty much everything but
 279          * haswell. */
 280         struct dpll dpll;
 281
 282         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 283         enum intel_dpll_id shared_dpll;
 284
 285         /* Actual register state of the dpll, for shared dpll cross-checking. */
 286         struct intel_dpll_hw_state dpll_hw_state;
 287
 288         int pipe_bpp;
 289         struct intel_link_m_n dp_m_n;
 290
 291         /*
 292          * Frequence the dpll for the port should run at. Differs from the
 293          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 294          * already multiplied by pixel_multiplier.
 295          */
 296         int port_clock;
 297
 298         /* Used by SDVO (and if we ever fix it, HDMI). */
 299         unsigned pixel_multiplier;
 300
 301         /* Panel fitter controls for gen2-gen4 + VLV */
 302         struct {
 303                 u32 control;
 304                 u32 pgm_ratios;
 305                 u32 lvds_border_bits;
 306         } gmch_pfit;
 307
 308         /* Panel fitter placement and size for Ironlake+ */
 309         struct {
 310                 u32 pos;
 311                 u32 size;
 312                 bool enabled;
 313         } pch_pfit;
 314
 315         /* FDI configuration, only valid if has_pch_encoder is set. */
 316         int fdi_lanes;
 317         struct intel_link_m_n fdi_m_n;
 318
 319         bool ips_enabled;
 320
 321         bool double_wide;
 322 };
 323
 324 struct intel_pipe_wm {
 325         struct intel_wm_level wm[5];
 326         uint32_t linetime;
 327         bool fbc_wm_enabled;
 328 };
 329
 330 struct intel_crtc {
 331         struct drm_crtc base;
 332         enum pipe pipe;
 333         enum plane plane;
 334         u8 lut_r[256], lut_g[256], lut_b[256];
 335         /*
 336          * Whether the crtc and the connected output pipeline is active. Implies
 337          * that crtc->enabled is set, i.e. the current mode configuration has
 338          * some outputs connected to this crtc.
 339          */
 340         bool active;
 341         unsigned long enabled_power_domains;
 342         bool eld_vld;
 343         bool primary_enabled; /* is the primary plane (partially) visible? */
 344         bool lowfreq_avail;
 345         struct intel_overlay *overlay;
 346         struct intel_unpin_work *unpin_work;
 347
 348         atomic_t unpin_work_count;
 349
 350         /* Display surface base address adjustement for pageflips. Note that on
 351          * gen4+ this only adjusts up to a tile, offsets within a tile are
 352          * handled in the hw itself (with the TILEOFF register). */
 353         unsigned long dspaddr_offset;
 354
 355         struct drm_i915_gem_object *cursor_bo;
 356         uint32_t cursor_addr;
 357         int16_t cursor_x, cursor_y;
 358         int16_t cursor_width, cursor_height;
 359         bool cursor_visible;
 360
 361         struct intel_crtc_config config;
 362
 363         uint32_t ddi_pll_sel;
 364
 365         /* reset counter value when the last flip was submitted */
 366         unsigned int reset_counter;
 367
 368         /* Access to these should be protected by dev_priv->irq_lock. */
 369         bool cpu_fifo_underrun_disabled;
 370         bool pch_fifo_underrun_disabled;
 371
 372         /* per-pipe watermark state */
 373         struct {
 374                 /* watermarks currently being used  */
 375                 struct intel_pipe_wm active;
 376         } wm;
 377 };
 378
 379 struct intel_plane_wm_parameters {
 380         uint32_t horiz_pixels;
 381         uint8_t bytes_per_pixel;
 382         bool enabled;
 383         bool scaled;
 384 };
 385
 386 struct intel_plane {
 387         struct drm_plane base;
 388         int plane;
 389         enum pipe pipe;
 390         struct drm_i915_gem_object *obj;
 391         bool can_scale;
 392         int max_downscale;
 393         u32 lut_r[1024], lut_g[1024], lut_b[1024];
 394         int crtc_x, crtc_y;
 395         unsigned int crtc_w, crtc_h;
 396         uint32_t src_x, src_y;
 397         uint32_t src_w, src_h;
 398
 399         /* Since we need to change the watermarks before/after
 400          * enabling/disabling the planes, we need to store the parameters here
 401          * as the other pieces of the struct may not reflect the values we want
 402          * for the watermark calculations. Currently only Haswell uses this.
 403          */
 404         struct intel_plane_wm_parameters wm;
 405
 406         void (*update_plane)(struct drm_plane *plane,
 407                              struct drm_crtc *crtc,
 408                              struct drm_framebuffer *fb,
 409                              struct drm_i915_gem_object *obj,
 410                              int crtc_x, int crtc_y,
 411                              unsigned int crtc_w, unsigned int crtc_h,
 412                              uint32_t x, uint32_t y,
 413                              uint32_t src_w, uint32_t src_h);
 414         void (*disable_plane)(struct drm_plane *plane,
 415                               struct drm_crtc *crtc);
 416         int (*update_colorkey)(struct drm_plane *plane,
 417                                struct drm_intel_sprite_colorkey *key);
 418         void (*get_colorkey)(struct drm_plane *plane,
 419                              struct drm_intel_sprite_colorkey *key);
 420 };
 421
 422 struct intel_watermark_params {
 423         unsigned long fifo_size;
 424         unsigned long max_wm;
 425         unsigned long default_wm;
 426         unsigned long guard_size;
 427         unsigned long cacheline_size;
 428 };
 429
 430 struct cxsr_latency {
 431         int is_desktop;
 432         int is_ddr3;
 433         unsigned long fsb_freq;
 434         unsigned long mem_freq;
 435         unsigned long display_sr;
 436         unsigned long display_hpll_disable;
 437         unsigned long cursor_sr;
 438         unsigned long cursor_hpll_disable;
 439 };
 440
 441 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 442 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 443 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 444 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 445 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 446
 447 struct intel_hdmi {
 448         u32 hdmi_reg;
 449         int ddc_bus;
 450         uint32_t color_range;
 451         bool color_range_auto;
 452         bool has_hdmi_sink;
 453         bool has_audio;
 454         enum hdmi_force_audio force_audio;
 455         bool rgb_quant_range_selectable;
 456         void (*write_infoframe)(struct drm_encoder *encoder,
 457                                 enum hdmi_infoframe_type type,
 458                                 const void *frame, ssize_t len);
 459         void (*set_infoframes)(struct drm_encoder *encoder,
 460                                struct drm_display_mode *adjusted_mode);
 461 };
 462
 463 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 464
 465 struct intel_dp {
 466         uint32_t output_reg;
 467         uint32_t aux_ch_ctl_reg;
 468         uint32_t DP;
 469         bool has_audio;
 470         enum hdmi_force_audio force_audio;
 471         uint32_t color_range;
 472         bool color_range_auto;
 473         uint8_t link_bw;
 474         uint8_t lane_count;
 475         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 476         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 477         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 478         struct i2c_adapter adapter;
 479         struct i2c_algo_dp_aux_data algo;
 480         uint8_t train_set[4];
 481         int panel_power_up_delay;
 482         int panel_power_down_delay;
 483         int panel_power_cycle_delay;
 484         int backlight_on_delay;
 485         int backlight_off_delay;
 486         struct delayed_work panel_vdd_work;
 487         bool want_panel_vdd;
 488         bool psr_setup_done;
 489         struct intel_connector *attached_connector;
 490 };
 491
 492 struct intel_digital_port {
 493         struct intel_encoder base;
 494         enum port port;
 495         u32 saved_port_bits;
 496         struct intel_dp dp;
 497         struct intel_hdmi hdmi;
 498 };
 499
 500 static inline int
 501 vlv_dport_to_channel(struct intel_digital_port *dport)
 502 {
 503         switch (dport->port) {
 504         case PORT_B:
 505                 return DPIO_CH0;
 506         case PORT_C:
 507                 return DPIO_CH1;
 508         default:
 509                 BUG();
 510         }
 511 }
 512
 513 static inline struct drm_crtc *
 514 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 515 {
 516         struct drm_i915_private *dev_priv = dev->dev_private;
 517         return dev_priv->pipe_to_crtc_mapping[pipe];
 518 }
 519
 520 static inline struct drm_crtc *
 521 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 522 {
 523         struct drm_i915_private *dev_priv = dev->dev_private;
 524         return dev_priv->plane_to_crtc_mapping[plane];
 525 }
 526
 527 struct intel_unpin_work {
 528         struct work_struct work;
 529         struct drm_crtc *crtc;
 530         struct drm_i915_gem_object *old_fb_obj;
 531         struct drm_i915_gem_object *pending_flip_obj;
 532         struct drm_pending_vblank_event *event;
 533         atomic_t pending;
 534 #define INTEL_FLIP_INACTIVE     0
 535 #define INTEL_FLIP_PENDING      1
 536 #define INTEL_FLIP_COMPLETE     2
 537         bool enable_stall_check;
 538 };
 539
 540 struct intel_set_config {
 541         struct drm_encoder **save_connector_encoders;
 542         struct drm_crtc **save_encoder_crtcs;
 543
 544         bool fb_changed;
 545         bool mode_changed;
 546 };
 547
 548 struct intel_load_detect_pipe {
 549         struct drm_framebuffer *release_fb;
 550         bool load_detect_temp;
 551         int dpms_mode;
 552 };
 553
 554 static inline struct intel_encoder *
 555 intel_attached_encoder(struct drm_connector *connector)
 556 {
 557         return to_intel_connector(connector)->encoder;
 558 }
 559
 560 static inline struct intel_digital_port *
 561 enc_to_dig_port(struct drm_encoder *encoder)
 562 {
 563         return container_of(encoder, struct intel_digital_port, base.base);
 564 }
 565
 566 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 567 {
 568         return &enc_to_dig_port(encoder)->dp;
 569 }
 570
 571 static inline struct intel_digital_port *
 572 dp_to_dig_port(struct intel_dp *intel_dp)
 573 {
 574         return container_of(intel_dp, struct intel_digital_port, dp);
 575 }
 576
 577 static inline struct intel_digital_port *
 578 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 579 {
 580         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 581 }
 582
 583
 584 /* i915_irq.c */
 585 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 586                                            enum pipe pipe, bool enable);
 587 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 588                                            enum transcoder pch_transcoder,
 589                                            bool enable);
 590 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 591 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 592 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 593 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 594 void hsw_pc8_disable_interrupts(struct drm_device *dev);
 595 void hsw_pc8_restore_interrupts(struct drm_device *dev);
 596
 597
 598 /* intel_crt.c */
 599 void intel_crt_init(struct drm_device *dev);
 600
 601
 602 /* intel_ddi.c */
 603 void intel_prepare_ddi(struct drm_device *dev);
 604 void hsw_fdi_link_train(struct drm_crtc *crtc);
 605 void intel_ddi_init(struct drm_device *dev, enum port port);
 606 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 607 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 608 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
 609 void intel_ddi_pll_init(struct drm_device *dev);
 610 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 611 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 612                                        enum transcoder cpu_transcoder);
 613 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 614 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 615 void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
 616 bool intel_ddi_pll_select(struct intel_crtc *crtc);
 617 void intel_ddi_pll_enable(struct intel_crtc *crtc);
 618 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
 619 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 620 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 621 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 622 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 623 void intel_ddi_get_config(struct intel_encoder *encoder,
 624                           struct intel_crtc_config *pipe_config);
 625
 626
 627 /* intel_display.c */
 628 const char *intel_output_name(int output);
 629 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 630 int intel_pch_rawclk(struct drm_device *dev);
 631 void intel_mark_busy(struct drm_device *dev);
 632 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 633                         struct intel_ring_buffer *ring);
 634 void intel_mark_idle(struct drm_device *dev);
 635 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 636 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 637 void intel_encoder_destroy(struct drm_encoder *encoder);
 638 void intel_connector_dpms(struct drm_connector *, int mode);
 639 bool intel_connector_get_hw_state(struct intel_connector *connector);
 640 void intel_modeset_check_state(struct drm_device *dev);
 641 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 642                                 struct intel_digital_port *port);
 643 void intel_connector_attach_encoder(struct intel_connector *connector,
 644                                     struct intel_encoder *encoder);
 645 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 646 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 647                                              struct drm_crtc *crtc);
 648 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 649 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 650                                 struct drm_file *file_priv);
 651 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 652                                              enum pipe pipe);
 653 void intel_wait_for_vblank(struct drm_device *dev, int pipe);
 654 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
 655 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 656 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 657                          struct intel_digital_port *dport);
 658 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 659                                 struct drm_display_mode *mode,
 660                                 struct intel_load_detect_pipe *old);
 661 void intel_release_load_detect_pipe(struct drm_connector *connector,
 662                                     struct intel_load_detect_pipe *old);
 663 int intel_pin_and_fence_fb_obj(struct drm_device *dev,
 664                                struct drm_i915_gem_object *obj,
 665                                struct intel_ring_buffer *pipelined);
 666 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 667 int intel_framebuffer_init(struct drm_device *dev,
 668                            struct intel_framebuffer *ifb,
 669                            struct drm_mode_fb_cmd2 *mode_cmd,
 670                            struct drm_i915_gem_object *obj);
 671 void intel_framebuffer_fini(struct intel_framebuffer *fb);
 672 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 673 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 674 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 675 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
 676 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 677                         struct intel_shared_dpll *pll,
 678                         bool state);
 679 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 680 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
 681 void assert_pll(struct drm_i915_private *dev_priv,
 682                 enum pipe pipe, bool state);
 683 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 684 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 685 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 686                        enum pipe pipe, bool state);
 687 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 688 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 689 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 690 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 691 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 692 void intel_write_eld(struct drm_encoder *encoder,
 693                      struct drm_display_mode *mode);
 694 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
 695                                              unsigned int tiling_mode,
 696                                              unsigned int bpp,
 697                                              unsigned int pitch);
 698 void intel_display_handle_reset(struct drm_device *dev);
 699 void hsw_enable_pc8_work(struct work_struct *__work);
 700 void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
 701 void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
 702 void intel_dp_get_m_n(struct intel_crtc *crtc,
 703                       struct intel_crtc_config *pipe_config);
 704 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 705 void
 706 ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
 707                                 int dotclock);
 708 bool intel_crtc_active(struct drm_crtc *crtc);
 709 void hsw_enable_ips(struct intel_crtc *crtc);
 710 void hsw_disable_ips(struct intel_crtc *crtc);
 711 void intel_display_set_init_power(struct drm_device *dev, bool enable);
 712 int valleyview_get_vco(struct drm_i915_private *dev_priv);
 713
 714 /* intel_dp.c */
 715 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 716 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 717                              struct intel_connector *intel_connector);
 718 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 719 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 720 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 721 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 722 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
 723 void intel_dp_check_link_status(struct intel_dp *intel_dp);
 724 bool intel_dp_compute_config(struct intel_encoder *encoder,
 725                              struct intel_crtc_config *pipe_config);
 726 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 727 void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
 728 void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
 729 void ironlake_edp_panel_on(struct intel_dp *intel_dp);
 730 void ironlake_edp_panel_off(struct intel_dp *intel_dp);
 731 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 732 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 733 void intel_edp_psr_enable(struct intel_dp *intel_dp);
 734 void intel_edp_psr_disable(struct intel_dp *intel_dp);
 735 void intel_edp_psr_update(struct drm_device *dev);
 736
 737
 738 /* intel_dsi.c */
 739 bool intel_dsi_init(struct drm_device *dev);
 740
 741
 742 /* intel_dvo.c */
 743 void intel_dvo_init(struct drm_device *dev);
 744
 745
 746 /* legacy fbdev emulation in intel_fbdev.c */
 747 #ifdef CONFIG_DRM_I915_FBDEV
 748 extern int intel_fbdev_init(struct drm_device *dev);
 749 extern void intel_fbdev_initial_config(struct drm_device *dev);
 750 extern void intel_fbdev_fini(struct drm_device *dev);
 751 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
 752 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
 753 extern void intel_fbdev_restore_mode(struct drm_device *dev);
 754 #else
 755 static inline int intel_fbdev_init(struct drm_device *dev)
 756 {
 757         return 0;
 758 }
 759
 760 static inline void intel_fbdev_initial_config(struct drm_device *dev)
 761 {
 762 }
 763
 764 static inline void intel_fbdev_fini(struct drm_device *dev)
 765 {
 766 }
 767
 768 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
 769 {
 770 }
 771
 772 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
 773 {
 774 }
 775 #endif
 776
 777 /* intel_hdmi.c */
 778 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
 779 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 780                                struct intel_connector *intel_connector);
 781 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
 782 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 783                                struct intel_crtc_config *pipe_config);
 784
 785
 786 /* intel_lvds.c */
 787 void intel_lvds_init(struct drm_device *dev);
 788 bool intel_is_dual_link_lvds(struct drm_device *dev);
 789
 790
 791 /* intel_modes.c */
 792 int intel_connector_update_modes(struct drm_connector *connector,
 793                                  struct edid *edid);
 794 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 795 void intel_attach_force_audio_property(struct drm_connector *connector);
 796 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
 797
 798
 799 /* intel_overlay.c */
 800 void intel_setup_overlay(struct drm_device *dev);
 801 void intel_cleanup_overlay(struct drm_device *dev);
 802 int intel_overlay_switch_off(struct intel_overlay *overlay);
 803 int intel_overlay_put_image(struct drm_device *dev, void *data,
 804                             struct drm_file *file_priv);
 805 int intel_overlay_attrs(struct drm_device *dev, void *data,
 806                         struct drm_file *file_priv);
 807
 808
 809 /* intel_panel.c */
 810 int intel_panel_init(struct intel_panel *panel,
 811                      struct drm_display_mode *fixed_mode);
 812 void intel_panel_fini(struct intel_panel *panel);
 813 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
 814                             struct drm_display_mode *adjusted_mode);
 815 void intel_pch_panel_fitting(struct intel_crtc *crtc,
 816                              struct intel_crtc_config *pipe_config,
 817                              int fitting_mode);
 818 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
 819                               struct intel_crtc_config *pipe_config,
 820                               int fitting_mode);
 821 void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
 822                                u32 max);
 823 int intel_panel_setup_backlight(struct drm_connector *connector);
 824 void intel_panel_enable_backlight(struct intel_connector *connector);
 825 void intel_panel_disable_backlight(struct intel_connector *connector);
 826 void intel_panel_destroy_backlight(struct drm_connector *connector);
 827 void intel_panel_init_backlight_funcs(struct drm_device *dev);
 828 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 829 extern struct drm_display_mode *intel_find_panel_downclock(
 830                                 struct drm_device *dev,
 831                                 struct drm_display_mode *fixed_mode,
 832                                 struct drm_connector *connector);
 833
 834 /* intel_pm.c */
 835 void intel_init_clock_gating(struct drm_device *dev);
 836 void intel_suspend_hw(struct drm_device *dev);
 837 void intel_update_watermarks(struct drm_crtc *crtc);
 838 void intel_update_sprite_watermarks(struct drm_plane *plane,
 839                                     struct drm_crtc *crtc,
 840                                     uint32_t sprite_width, int pixel_size,
 841                                     bool enabled, bool scaled);
 842 void intel_init_pm(struct drm_device *dev);
 843 void intel_pm_setup(struct drm_device *dev);
 844 bool intel_fbc_enabled(struct drm_device *dev);
 845 void intel_update_fbc(struct drm_device *dev);
 846 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 847 void intel_gpu_ips_teardown(void);
 848 int intel_power_domains_init(struct drm_device *dev);
 849 void intel_power_domains_remove(struct drm_device *dev);
 850 bool intel_display_power_enabled(struct drm_device *dev,
 851                                  enum intel_display_power_domain domain);
 852 bool intel_display_power_enabled_sw(struct drm_device *dev,
 853                                     enum intel_display_power_domain domain);
 854 void intel_display_power_get(struct drm_device *dev,
 855                              enum intel_display_power_domain domain);
 856 void intel_display_power_put(struct drm_device *dev,
 857                              enum intel_display_power_domain domain);
 858 void intel_power_domains_init_hw(struct drm_device *dev);
 859 void intel_set_power_well(struct drm_device *dev, bool enable);
 860 void intel_enable_gt_powersave(struct drm_device *dev);
 861 void intel_disable_gt_powersave(struct drm_device *dev);
 862 void ironlake_teardown_rc6(struct drm_device *dev);
 863 void gen6_update_ring_freq(struct drm_device *dev);
 864 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 865 void gen6_rps_boost(struct drm_i915_private *dev_priv);
 866 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
 867 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
 868 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
 869 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
 870 void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
 871 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
 872 void ilk_wm_get_hw_state(struct drm_device *dev);
 873
 874
 875 /* intel_sdvo.c */
 876 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 877
 878
 879 /* intel_sprite.c */
 880 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 881 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 882                                enum plane plane);
 883 void intel_plane_restore(struct drm_plane *plane);
 884 void intel_plane_disable(struct drm_plane *plane);
 885 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 886                               struct drm_file *file_priv);
 887 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 888                               struct drm_file *file_priv);
 889
 890
 891 /* intel_tv.c */
 892 void intel_tv_init(struct drm_device *dev);
 893
 894 #endif /* __INTEL_DRV_H__ */