drivers/gpu/drm/i915/intel_i2c.c

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2008,2010 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *      Eric Anholt <eric@anholt.net>
  27  *      Chris Wilson <chris@chris-wilson.co.uk>
  28  */
  29 #include <linux/i2c.h>
  30 #include <linux/i2c-algo-bit.h>
  31 #include <linux/export.h>
  32 #include <drm/drmP.h>
  33 #include "intel_drv.h"
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36
  37 enum disp_clk {
  38         CDCLK,
  39         CZCLK
  40 };
  41
  42 struct gmbus_port {
  43         const char *name;
  44         int reg;
  45 };
  46
  47 static const struct gmbus_port gmbus_ports[] = {
  48         { "ssc", GPIOB },
  49         { "vga", GPIOA },
  50         { "panel", GPIOC },
  51         { "dpc", GPIOD },
  52         { "dpb", GPIOE },
  53         { "dpd", GPIOF },
  54 };
  55
  56 /* Intel GPIO access functions */
  57
  58 #define I2C_RISEFALL_TIME 10
  59
  60 static inline struct intel_gmbus *
  61 to_intel_gmbus(struct i2c_adapter *i2c)
  62 {
  63         return container_of(i2c, struct intel_gmbus, adapter);
  64 }
  65
  66 static int get_disp_clk_div(struct drm_i915_private *dev_priv,
  67                             enum disp_clk clk)
  68 {
  69         u32 reg_val;
  70         int clk_ratio;
  71
  72         reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
  73
  74         if (clk == CDCLK)
  75                 clk_ratio =
  76                         ((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1;
  77         else
  78                 clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1;
  79
  80         return clk_ratio;
  81 }
  82
  83 static void gmbus_set_freq(struct drm_i915_private *dev_priv)
  84 {
  85         int vco, gmbus_freq = 0, cdclk_div;
  86
  87         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
  88
  89         vco = valleyview_get_vco(dev_priv);
  90
  91         /* Get the CDCLK divide ratio */
  92         cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
  93
  94         /*
  95          * Program the gmbus_freq based on the cdclk frequency.
  96          * BSpec erroneously claims we should aim for 4MHz, but
  97          * in fact 1MHz is the correct frequency.
  98          */
  99         if (cdclk_div)
 100                 gmbus_freq = (vco << 1) / cdclk_div;
 101
 102         if (WARN_ON(gmbus_freq == 0))
 103                 return;
 104
 105         I915_WRITE(GMBUSFREQ_VLV, gmbus_freq);
 106 }
 107
 108 void
 109 intel_i2c_reset(struct drm_device *dev)
 110 {
 111         struct drm_i915_private *dev_priv = dev->dev_private;
 112
 113         /*
 114          * In BIOS-less system, program the correct gmbus frequency
 115          * before reading edid.
 116          */
 117         if (IS_VALLEYVIEW(dev))
 118                 gmbus_set_freq(dev_priv);
 119
 120         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
 121         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
 122 }
 123
 124 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
 125 {
 126         u32 val;
 127
 128         /* When using bit bashing for I2C, this bit needs to be set to 1 */
 129         if (!IS_PINEVIEW(dev_priv->dev))
 130                 return;
 131
 132         val = I915_READ(DSPCLK_GATE_D);
 133         if (enable)
 134                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
 135         else
 136                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
 137         I915_WRITE(DSPCLK_GATE_D, val);
 138 }
 139
 140 static u32 get_reserved(struct intel_gmbus *bus)
 141 {
 142         struct drm_i915_private *dev_priv = bus->dev_priv;
 143         struct drm_device *dev = dev_priv->dev;
 144         u32 reserved = 0;
 145
 146         /* On most chips, these bits must be preserved in software. */
 147         if (!IS_I830(dev) && !IS_845G(dev))
 148                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
 149                                              (GPIO_DATA_PULLUP_DISABLE |
 150                                               GPIO_CLOCK_PULLUP_DISABLE);
 151
 152         return reserved;
 153 }
 154
 155 static int get_clock(void *data)
 156 {
 157         struct intel_gmbus *bus = data;
 158         struct drm_i915_private *dev_priv = bus->dev_priv;
 159         u32 reserved = get_reserved(bus);
 160         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
 161         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 162         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
 163 }
 164
 165 static int get_data(void *data)
 166 {
 167         struct intel_gmbus *bus = data;
 168         struct drm_i915_private *dev_priv = bus->dev_priv;
 169         u32 reserved = get_reserved(bus);
 170         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
 171         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
 172         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
 173 }
 174
 175 static void set_clock(void *data, int state_high)
 176 {
 177         struct intel_gmbus *bus = data;
 178         struct drm_i915_private *dev_priv = bus->dev_priv;
 179         u32 reserved = get_reserved(bus);
 180         u32 clock_bits;
 181
 182         if (state_high)
 183                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 184         else
 185                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 186                         GPIO_CLOCK_VAL_MASK;
 187
 188         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
 189         POSTING_READ(bus->gpio_reg);
 190 }
 191
 192 static void set_data(void *data, int state_high)
 193 {
 194         struct intel_gmbus *bus = data;
 195         struct drm_i915_private *dev_priv = bus->dev_priv;
 196         u32 reserved = get_reserved(bus);
 197         u32 data_bits;
 198
 199         if (state_high)
 200                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 201         else
 202                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 203                         GPIO_DATA_VAL_MASK;
 204
 205         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
 206         POSTING_READ(bus->gpio_reg);
 207 }
 208
 209 static int
 210 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 211 {
 212         struct intel_gmbus *bus = container_of(adapter,
 213                                                struct intel_gmbus,
 214                                                adapter);
 215         struct drm_i915_private *dev_priv = bus->dev_priv;
 216
 217         intel_i2c_reset(dev_priv->dev);
 218         intel_i2c_quirk_set(dev_priv, true);
 219         set_data(bus, 1);
 220         set_clock(bus, 1);
 221         udelay(I2C_RISEFALL_TIME);
 222         return 0;
 223 }
 224
 225 static void
 226 intel_gpio_post_xfer(struct i2c_adapter *adapter)
 227 {
 228         struct intel_gmbus *bus = container_of(adapter,
 229                                                struct intel_gmbus,
 230                                                adapter);
 231         struct drm_i915_private *dev_priv = bus->dev_priv;
 232
 233         set_data(bus, 1);
 234         set_clock(bus, 1);
 235         intel_i2c_quirk_set(dev_priv, false);
 236 }
 237
 238 static void
 239 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
 240 {
 241         struct drm_i915_private *dev_priv = bus->dev_priv;
 242         struct i2c_algo_bit_data *algo;
 243
 244         algo = &bus->bit_algo;
 245
 246         /* -1 to map pin pair to gmbus index */
 247         bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
 248
 249         bus->adapter.algo_data = algo;
 250         algo->setsda = set_data;
 251         algo->setscl = set_clock;
 252         algo->getsda = get_data;
 253         algo->getscl = get_clock;
 254         algo->pre_xfer = intel_gpio_pre_xfer;
 255         algo->post_xfer = intel_gpio_post_xfer;
 256         algo->udelay = I2C_RISEFALL_TIME;
 257         algo->timeout = usecs_to_jiffies(2200);
 258         algo->data = bus;
 259 }
 260
 261 static int
 262 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
 263                      u32 gmbus2_status,
 264                      u32 gmbus4_irq_en)
 265 {
 266         int i;
 267         int reg_offset = dev_priv->gpio_mmio_base;
 268         u32 gmbus2 = 0;
 269         DEFINE_WAIT(wait);
 270
 271         if (!HAS_GMBUS_IRQ(dev_priv->dev))
 272                 gmbus4_irq_en = 0;
 273
 274         /* Important: The hw handles only the first bit, so set only one! Since
 275          * we also need to check for NAKs besides the hw ready/idle signal, we
 276          * need to wake up periodically and check that ourselves. */
 277         I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
 278
 279         for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
 280                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
 281                                 TASK_UNINTERRUPTIBLE);
 282
 283                 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
 284                 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
 285                         break;
 286
 287                 schedule_timeout(1);
 288         }
 289         finish_wait(&dev_priv->gmbus_wait_queue, &wait);
 290
 291         I915_WRITE(GMBUS4 + reg_offset, 0);
 292
 293         if (gmbus2 & GMBUS_SATOER)
 294                 return -ENXIO;
 295         if (gmbus2 & gmbus2_status)
 296                 return 0;
 297         return -ETIMEDOUT;
 298 }
 299
 300 static int
 301 gmbus_wait_idle(struct drm_i915_private *dev_priv)
 302 {
 303         int ret;
 304         int reg_offset = dev_priv->gpio_mmio_base;
 305
 306 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
 307
 308         if (!HAS_GMBUS_IRQ(dev_priv->dev))
 309                 return wait_for(C, 10);
 310
 311         /* Important: The hw handles only the first bit, so set only one! */
 312         I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
 313
 314         ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 315                                  msecs_to_jiffies_timeout(10));
 316
 317         I915_WRITE(GMBUS4 + reg_offset, 0);
 318
 319         if (ret)
 320                 return 0;
 321         else
 322                 return -ETIMEDOUT;
 323 #undef C
 324 }
 325
 326 static int
 327 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
 328                 u32 gmbus1_index)
 329 {
 330         int reg_offset = dev_priv->gpio_mmio_base;
 331         u16 len = msg->len;
 332         u8 *buf = msg->buf;
 333
 334         I915_WRITE(GMBUS1 + reg_offset,
 335                    gmbus1_index |
 336                    GMBUS_CYCLE_WAIT |
 337                    (len << GMBUS_BYTE_COUNT_SHIFT) |
 338                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 339                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 340         while (len) {
 341                 int ret;
 342                 u32 val, loop = 0;
 343
 344                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 345                                            GMBUS_HW_RDY_EN);
 346                 if (ret)
 347                         return ret;
 348
 349                 val = I915_READ(GMBUS3 + reg_offset);
 350                 do {
 351                         *buf++ = val & 0xff;
 352                         val >>= 8;
 353                 } while (--len && ++loop < 4);
 354         }
 355
 356         return 0;
 357 }
 358
 359 static int
 360 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
 361 {
 362         int reg_offset = dev_priv->gpio_mmio_base;
 363         u16 len = msg->len;
 364         u8 *buf = msg->buf;
 365         u32 val, loop;
 366
 367         val = loop = 0;
 368         while (len && loop < 4) {
 369                 val |= *buf++ << (8 * loop++);
 370                 len -= 1;
 371         }
 372
 373         I915_WRITE(GMBUS3 + reg_offset, val);
 374         I915_WRITE(GMBUS1 + reg_offset,
 375                    GMBUS_CYCLE_WAIT |
 376                    (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
 377                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
 378                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 379         while (len) {
 380                 int ret;
 381
 382                 val = loop = 0;
 383                 do {
 384                         val |= *buf++ << (8 * loop);
 385                 } while (--len && ++loop < 4);
 386
 387                 I915_WRITE(GMBUS3 + reg_offset, val);
 388
 389                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
 390                                            GMBUS_HW_RDY_EN);
 391                 if (ret)
 392                         return ret;
 393         }
 394         return 0;
 395 }
 396
 397 /*
 398  * The gmbus controller can combine a 1 or 2 byte write with a read that
 399  * immediately follows it by using an "INDEX" cycle.
 400  */
 401 static bool
 402 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
 403 {
 404         return (i + 1 < num &&
 405                 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
 406                 (msgs[i + 1].flags & I2C_M_RD));
 407 }
 408
 409 static int
 410 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
 411 {
 412         int reg_offset = dev_priv->gpio_mmio_base;
 413         u32 gmbus1_index = 0;
 414         u32 gmbus5 = 0;
 415         int ret;
 416
 417         if (msgs[0].len == 2)
 418                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
 419                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 420         if (msgs[0].len == 1)
 421                 gmbus1_index = GMBUS_CYCLE_INDEX |
 422                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 423
 424         /* GMBUS5 holds 16-bit index */
 425         if (gmbus5)
 426                 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
 427
 428         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
 429
 430         /* Clear GMBUS5 after each index transfer */
 431         if (gmbus5)
 432                 I915_WRITE(GMBUS5 + reg_offset, 0);
 433
 434         return ret;
 435 }
 436
 437 static int
 438 gmbus_xfer(struct i2c_adapter *adapter,
 439            struct i2c_msg *msgs,
 440            int num)
 441 {
 442         struct intel_gmbus *bus = container_of(adapter,
 443                                                struct intel_gmbus,
 444                                                adapter);
 445         struct drm_i915_private *dev_priv = bus->dev_priv;
 446         int i, reg_offset;
 447         int ret = 0;
 448
 449         intel_aux_display_runtime_get(dev_priv);
 450         mutex_lock(&dev_priv->gmbus_mutex);
 451
 452         if (bus->force_bit) {
 453                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 454                 goto out;
 455         }
 456
 457         reg_offset = dev_priv->gpio_mmio_base;
 458
 459         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
 460
 461         for (i = 0; i < num; i++) {
 462                 if (gmbus_is_index_read(msgs, i, num)) {
 463                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
 464                         i += 1;  /* set i to the index of the read xfer */
 465                 } else if (msgs[i].flags & I2C_M_RD) {
 466                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
 467                 } else {
 468                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
 469                 }
 470
 471                 if (ret == -ETIMEDOUT)
 472                         goto timeout;
 473                 if (ret == -ENXIO)
 474                         goto clear_err;
 475
 476                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
 477                                            GMBUS_HW_WAIT_EN);
 478                 if (ret == -ENXIO)
 479                         goto clear_err;
 480                 if (ret)
 481                         goto timeout;
 482         }
 483
 484         /* Generate a STOP condition on the bus. Note that gmbus can't generata
 485          * a STOP on the very first cycle. To simplify the code we
 486          * unconditionally generate the STOP condition with an additional gmbus
 487          * cycle. */
 488         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 489
 490         /* Mark the GMBUS interface as disabled after waiting for idle.
 491          * We will re-enable it at the start of the next xfer,
 492          * till then let it sleep.
 493          */
 494         if (gmbus_wait_idle(dev_priv)) {
 495                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
 496                          adapter->name);
 497                 ret = -ETIMEDOUT;
 498         }
 499         I915_WRITE(GMBUS0 + reg_offset, 0);
 500         ret = ret ?: i;
 501         goto out;
 502
 503 clear_err:
 504         /*
 505          * Wait for bus to IDLE before clearing NAK.
 506          * If we clear the NAK while bus is still active, then it will stay
 507          * active and the next transaction may fail.
 508          *
 509          * If no ACK is received during the address phase of a transaction, the
 510          * adapter must report -ENXIO. It is not clear what to return if no ACK
 511          * is received at other times. But we have to be careful to not return
 512          * spurious -ENXIO because that will prevent i2c and drm edid functions
 513          * from retrying. So return -ENXIO only when gmbus properly quiescents -
 514          * timing out seems to happen when there _is_ a ddc chip present, but
 515          * it's slow responding and only answers on the 2nd retry.
 516          */
 517         ret = -ENXIO;
 518         if (gmbus_wait_idle(dev_priv)) {
 519                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
 520                               adapter->name);
 521                 ret = -ETIMEDOUT;
 522         }
 523
 524         /* Toggle the Software Clear Interrupt bit. This has the effect
 525          * of resetting the GMBUS controller and so clearing the
 526          * BUS_ERROR raised by the slave's NAK.
 527          */
 528         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
 529         I915_WRITE(GMBUS1 + reg_offset, 0);
 530         I915_WRITE(GMBUS0 + reg_offset, 0);
 531
 532         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 533                          adapter->name, msgs[i].addr,
 534                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 535
 536         goto out;
 537
 538 timeout:
 539         DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 540                  bus->adapter.name, bus->reg0 & 0xff);
 541         I915_WRITE(GMBUS0 + reg_offset, 0);
 542
 543         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
 544         bus->force_bit = 1;
 545         ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 546
 547 out:
 548         mutex_unlock(&dev_priv->gmbus_mutex);
 549         intel_aux_display_runtime_put(dev_priv);
 550         return ret;
 551 }
 552
 553 static u32 gmbus_func(struct i2c_adapter *adapter)
 554 {
 555         return i2c_bit_algo.functionality(adapter) &
 556                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 557                 /* I2C_FUNC_10BIT_ADDR | */
 558                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 559                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 560 }
 561
 562 static const struct i2c_algorithm gmbus_algorithm = {
 563         .master_xfer    = gmbus_xfer,
 564         .functionality  = gmbus_func
 565 };
 566
 567 /**
 568  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 569  * @dev: DRM device
 570  */
 571 int intel_setup_gmbus(struct drm_device *dev)
 572 {
 573         struct drm_i915_private *dev_priv = dev->dev_private;
 574         int ret, i;
 575
 576         if (HAS_PCH_NOP(dev))
 577                 return 0;
 578         else if (HAS_PCH_SPLIT(dev))
 579                 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
 580         else if (IS_VALLEYVIEW(dev))
 581                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
 582         else
 583                 dev_priv->gpio_mmio_base = 0;
 584
 585         mutex_init(&dev_priv->gmbus_mutex);
 586         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
 587
 588         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 589                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 590                 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
 591
 592                 bus->adapter.owner = THIS_MODULE;
 593                 bus->adapter.class = I2C_CLASS_DDC;
 594                 snprintf(bus->adapter.name,
 595                          sizeof(bus->adapter.name),
 596                          "i915 gmbus %s",
 597                          gmbus_ports[i].name);
 598
 599                 bus->adapter.dev.parent = &dev->pdev->dev;
 600                 bus->dev_priv = dev_priv;
 601
 602                 bus->adapter.algo = &gmbus_algorithm;
 603
 604                 /* By default use a conservative clock rate */
 605                 bus->reg0 = port | GMBUS_RATE_100KHZ;
 606
 607                 /* gmbus seems to be broken on i830 */
 608                 if (IS_I830(dev))
 609                         bus->force_bit = 1;
 610
 611                 intel_gpio_setup(bus, port);
 612
 613                 ret = i2c_add_adapter(&bus->adapter);
 614                 if (ret)
 615                         goto err;
 616         }
 617
 618         intel_i2c_reset(dev_priv->dev);
 619
 620         return 0;
 621
 622 err:
 623         while (--i) {
 624                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 625                 i2c_del_adapter(&bus->adapter);
 626         }
 627         return ret;
 628 }
 629
 630 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
 631                                             unsigned port)
 632 {
 633         WARN_ON(!intel_gmbus_is_port_valid(port));
 634         /* -1 to map pin pair to gmbus index */
 635         return (intel_gmbus_is_port_valid(port)) ?
 636                 &dev_priv->gmbus[port - 1].adapter : NULL;
 637 }
 638
 639 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
 640 {
 641         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 642
 643         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
 644 }
 645
 646 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 647 {
 648         struct intel_gmbus *bus = to_intel_gmbus(adapter);
 649
 650         bus->force_bit += force_bit ? 1 : -1;
 651         DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
 652                       force_bit ? "en" : "dis", adapter->name,
 653                       bus->force_bit);
 654 }
 655
 656 void intel_teardown_gmbus(struct drm_device *dev)
 657 {
 658         struct drm_i915_private *dev_priv = dev->dev_private;
 659         int i;
 660
 661         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
 662                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
 663                 i2c_del_adapter(&bus->adapter);
 664         }
 665 }