drivers/gpu/drm/msm/adreno/adreno_gpu.h

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __ADRENO_GPU_H__
  19 #define __ADRENO_GPU_H__
  20
  21 #include <linux/firmware.h>
  22
  23 #include "msm_gpu.h"
  24
  25 #include "adreno_common.xml.h"
  26 #include "adreno_pm4.xml.h"
  27
  28 struct adreno_rev {
  29         uint8_t  core;
  30         uint8_t  major;
  31         uint8_t  minor;
  32         uint8_t  patchid;
  33 };
  34
  35 #define ADRENO_REV(core, major, minor, patchid) \
  36         ((struct adreno_rev){ core, major, minor, patchid })
  37
  38 struct adreno_gpu_funcs {
  39         struct msm_gpu_funcs base;
  40 };
  41
  42 struct adreno_info;
  43
  44 struct adreno_rbmemptrs {
  45         volatile uint32_t rptr;
  46         volatile uint32_t wptr;
  47         volatile uint32_t fence;
  48 };
  49
  50 struct adreno_gpu {
  51         struct msm_gpu base;
  52         struct adreno_rev rev;
  53         const struct adreno_info *info;
  54         uint32_t gmem;  /* actual gmem size */
  55         uint32_t revn;  /* numeric revision name */
  56         const struct adreno_gpu_funcs *funcs;
  57
  58         /* firmware: */
  59         const struct firmware *pm4, *pfp;
  60
  61         /* ringbuffer rptr/wptr: */
  62         // TODO should this be in msm_ringbuffer?  I think it would be
  63         // different for z180..
  64         struct adreno_rbmemptrs *memptrs;
  65         struct drm_gem_object *memptrs_bo;
  66         uint32_t memptrs_iova;
  67 };
  68 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
  69
  70 /* platform config data (ie. from DT, or pdata) */
  71 struct adreno_platform_config {
  72         struct adreno_rev rev;
  73         uint32_t fast_rate, slow_rate, bus_freq;
  74 #ifdef CONFIG_MSM_BUS_SCALING
  75         struct msm_bus_scale_pdata *bus_scale_table;
  76 #endif
  77 };
  78
  79 #define ADRENO_IDLE_TIMEOUT (20 * 1000)
  80
  81 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
  82 {
  83         return (gpu->revn >= 300) && (gpu->revn < 400);
  84 }
  85
  86 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
  87 {
  88         return gpu->revn == 305;
  89 }
  90
  91 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
  92 {
  93         return gpu->revn == 320;
  94 }
  95
  96 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
  97 {
  98         return gpu->revn == 330;
  99 }
 100
 101 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
 102 {
 103         return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
 104 }
 105
 106 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
 107 int adreno_hw_init(struct msm_gpu *gpu);
 108 uint32_t adreno_last_fence(struct msm_gpu *gpu);
 109 void adreno_recover(struct msm_gpu *gpu);
 110 int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 111                 struct msm_file_private *ctx);
 112 void adreno_flush(struct msm_gpu *gpu);
 113 void adreno_idle(struct msm_gpu *gpu);
 114 #ifdef CONFIG_DEBUG_FS
 115 void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
 116 #endif
 117 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
 118
 119 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 120                 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
 121                 struct adreno_rev rev);
 122 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
 123
 124
 125 /* ringbuffer helpers (the parts that are adreno specific) */
 126
 127 static inline void
 128 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
 129 {
 130         adreno_wait_ring(ring->gpu, cnt+1);
 131         OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
 132 }
 133
 134 /* no-op packet: */
 135 static inline void
 136 OUT_PKT2(struct msm_ringbuffer *ring)
 137 {
 138         adreno_wait_ring(ring->gpu, 1);
 139         OUT_RING(ring, CP_TYPE2_PKT);
 140 }
 141
 142 static inline void
 143 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
 144 {
 145         adreno_wait_ring(ring->gpu, cnt+1);
 146         OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
 147 }
 148
 149
 150 #endif /* __ADRENO_GPU_H__ */