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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / dispnv04 / tvnv17.c
blobacef48f4a4ea2c62c75172ae38fb7f85646d39fa
1 /*
2 * Copyright (C) 2009 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include <drm/drmP.h>
28 #include <drm/drm_crtc_helper.h>
29 #include "nouveau_drm.h"
30 #include "nouveau_reg.h"
31 #include "nouveau_encoder.h"
32 #include "nouveau_connector.h"
33 #include "nouveau_crtc.h"
34 #include "hw.h"
35 #include "tvnv17.h"
36
37 #include <core/device.h>
38
39 #include <subdev/bios/gpio.h>
40 #include <subdev/gpio.h>
41
42 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
43 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
44 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
45 "\t\tDefault: PAL\n"
46 "\t\t*NOTE* Ignored for cards with external TV encoders.");
47 static char *nouveau_tv_norm;
48 module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
49
50 static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
51 {
52 struct drm_device *dev = encoder->dev;
53 struct nouveau_drm *drm = nouveau_drm(dev);
54 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
55 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
56 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
57 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
58 uint32_t sample = 0;
59 int head;
60
61 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
62 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
63 if (drm->vbios.tvdactestval)
64 testval = drm->vbios.tvdactestval;
65
66 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
67 head = (dacclk & 0x100) >> 8;
68
69 /* Save the previous state. */
70 gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
71 gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
72 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
73 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
74 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
75 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
76 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
77 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
78 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
79 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
80
81 /* Prepare the DAC for load detection. */
82 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true);
83 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true);
84
85 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
86 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
87 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
88 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
89 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
90 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
91 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
92 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
93 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
94
95 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
96
97 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
98 (dacclk & ~0xff) | 0x22);
99 msleep(1);
100 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
101 (dacclk & ~0xff) | 0x21);
102
103 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
104 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
105
106 /* Sample pin 0x4 (usually S-video luma). */
107 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
108 msleep(20);
109 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
110 & 0x4 << 28;
111
112 /* Sample the remaining pins. */
113 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
114 msleep(20);
115 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
116 & 0xa << 28;
117
118 /* Restore the previous state. */
119 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
120 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
121 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
122 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
123 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
124 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
125 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
126 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
127 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
128 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1);
129 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0);
130
131 return sample;
132 }
133
134 static bool
135 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
136 {
137 struct nouveau_drm *drm = nouveau_drm(dev);
138 struct nouveau_object *device = drm->device;
139
140 /* Zotac FX5200 */
141 if (nv_device_match(device, 0x0322, 0x19da, 0x1035) ||
142 nv_device_match(device, 0x0322, 0x19da, 0x2035)) {
143 *pin_mask = 0xc;
144 return false;
145 }
146
147 /* MSI nForce2 IGP */
148 if (nv_device_match(device, 0x01f0, 0x1462, 0x5710)) {
149 *pin_mask = 0xc;
150 return false;
151 }
152
153 return true;
154 }
155
156 static enum drm_connector_status
157 nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
158 {
159 struct drm_device *dev = encoder->dev;
160 struct nouveau_drm *drm = nouveau_drm(dev);
161 struct drm_mode_config *conf = &dev->mode_config;
162 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
163 struct dcb_output *dcb = tv_enc->base.dcb;
164 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
165
166 if (nv04_dac_in_use(encoder))
167 return connector_status_disconnected;
168
169 if (reliable) {
170 if (nv_device(drm->device)->chipset == 0x42 ||
171 nv_device(drm->device)->chipset == 0x43)
172 tv_enc->pin_mask =
173 nv42_tv_sample_load(encoder) >> 28 & 0xe;
174 else
175 tv_enc->pin_mask =
176 nv17_dac_sample_load(encoder) >> 28 & 0xe;
177 }
178
179 switch (tv_enc->pin_mask) {
180 case 0x2:
181 case 0x4:
182 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
183 break;
184 case 0xc:
185 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
186 break;
187 case 0xe:
188 if (dcb->tvconf.has_component_output)
189 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
190 else
191 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
192 break;
193 default:
194 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
195 break;
196 }
197
198 drm_object_property_set_value(&connector->base,
199 conf->tv_subconnector_property,
200 tv_enc->subconnector);
201
202 if (!reliable) {
203 return connector_status_unknown;
204 } else if (tv_enc->subconnector) {
205 NV_INFO(drm, "Load detected on output %c\n",
206 '@' + ffs(dcb->or));
207 return connector_status_connected;
208 } else {
209 return connector_status_disconnected;
210 }
211 }
212
213 static int nv17_tv_get_ld_modes(struct drm_encoder *encoder,
214 struct drm_connector *connector)
215 {
216 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
217 const struct drm_display_mode *tv_mode;
218 int n = 0;
219
220 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
221 struct drm_display_mode *mode;
222
223 mode = drm_mode_duplicate(encoder->dev, tv_mode);
224
225 mode->clock = tv_norm->tv_enc_mode.vrefresh *
226 mode->htotal / 1000 *
227 mode->vtotal / 1000;
228
229 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
230 mode->clock *= 2;
231
232 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
233 mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
234 mode->type |= DRM_MODE_TYPE_PREFERRED;
235
236 drm_mode_probed_add(connector, mode);
237 n++;
238 }
239
240 return n;
241 }
242
243 static int nv17_tv_get_hd_modes(struct drm_encoder *encoder,
244 struct drm_connector *connector)
245 {
246 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
247 struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode;
248 struct drm_display_mode *mode;
249 const struct {
250 int hdisplay;
251 int vdisplay;
252 } modes[] = {
253 { 640, 400 },
254 { 640, 480 },
255 { 720, 480 },
256 { 720, 576 },
257 { 800, 600 },
258 { 1024, 768 },
259 { 1280, 720 },
260 { 1280, 1024 },
261 { 1920, 1080 }
262 };
263 int i, n = 0;
264
265 for (i = 0; i < ARRAY_SIZE(modes); i++) {
266 if (modes[i].hdisplay > output_mode->hdisplay ||
267 modes[i].vdisplay > output_mode->vdisplay)
268 continue;
269
270 if (modes[i].hdisplay == output_mode->hdisplay &&
271 modes[i].vdisplay == output_mode->vdisplay) {
272 mode = drm_mode_duplicate(encoder->dev, output_mode);
273 mode->type |= DRM_MODE_TYPE_PREFERRED;
274
275 } else {
276 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
277 modes[i].vdisplay, 60, false,
278 (output_mode->flags &
279 DRM_MODE_FLAG_INTERLACE), false);
280 }
281
282 /* CVT modes are sometimes unsuitable... */
283 if (output_mode->hdisplay <= 720
284 || output_mode->hdisplay >= 1920) {
285 mode->htotal = output_mode->htotal;
286 mode->hsync_start = (mode->hdisplay + (mode->htotal
287 - mode->hdisplay) * 9 / 10) & ~7;
288 mode->hsync_end = mode->hsync_start + 8;
289 }
290
291 if (output_mode->vdisplay >= 1024) {
292 mode->vtotal = output_mode->vtotal;
293 mode->vsync_start = output_mode->vsync_start;
294 mode->vsync_end = output_mode->vsync_end;
295 }
296
297 mode->type |= DRM_MODE_TYPE_DRIVER;
298 drm_mode_probed_add(connector, mode);
299 n++;
300 }
301
302 return n;
303 }
304
305 static int nv17_tv_get_modes(struct drm_encoder *encoder,
306 struct drm_connector *connector)
307 {
308 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
309
310 if (tv_norm->kind == CTV_ENC_MODE)
311 return nv17_tv_get_hd_modes(encoder, connector);
312 else
313 return nv17_tv_get_ld_modes(encoder, connector);
314 }
315
316 static int nv17_tv_mode_valid(struct drm_encoder *encoder,
317 struct drm_display_mode *mode)
318 {
319 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
320
321 if (tv_norm->kind == CTV_ENC_MODE) {
322 struct drm_display_mode *output_mode =
323 &tv_norm->ctv_enc_mode.mode;
324
325 if (mode->clock > 400000)
326 return MODE_CLOCK_HIGH;
327
328 if (mode->hdisplay > output_mode->hdisplay ||
329 mode->vdisplay > output_mode->vdisplay)
330 return MODE_BAD;
331
332 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
333 (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
334 return MODE_NO_INTERLACE;
335
336 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
337 return MODE_NO_DBLESCAN;
338
339 } else {
340 const int vsync_tolerance = 600;
341
342 if (mode->clock > 70000)
343 return MODE_CLOCK_HIGH;
344
345 if (abs(drm_mode_vrefresh(mode) * 1000 -
346 tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
347 return MODE_VSYNC;
348
349 /* The encoder takes care of the actual interlacing */
350 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
351 return MODE_NO_INTERLACE;
352 }
353
354 return MODE_OK;
355 }
356
357 static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
358 const struct drm_display_mode *mode,
359 struct drm_display_mode *adjusted_mode)
360 {
361 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
362
363 if (nv04_dac_in_use(encoder))
364 return false;
365
366 if (tv_norm->kind == CTV_ENC_MODE)
367 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
368 else
369 adjusted_mode->clock = 90000;
370
371 return true;
372 }
373
374 static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
375 {
376 struct drm_device *dev = encoder->dev;
377 struct nouveau_drm *drm = nouveau_drm(dev);
378 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
379 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
380 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
381
382 if (nouveau_encoder(encoder)->last_dpms == mode)
383 return;
384 nouveau_encoder(encoder)->last_dpms = mode;
385
386 NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n",
387 mode, nouveau_encoder(encoder)->dcb->index);
388
389 regs->ptv_200 &= ~1;
390
391 if (tv_norm->kind == CTV_ENC_MODE) {
392 nv04_dfp_update_fp_control(encoder, mode);
393
394 } else {
395 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
396
397 if (mode == DRM_MODE_DPMS_ON)
398 regs->ptv_200 |= 1;
399 }
400
401 nv_load_ptv(dev, regs, 200);
402
403 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON);
404 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON);
405
406 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
407 }
408
409 static void nv17_tv_prepare(struct drm_encoder *encoder)
410 {
411 struct drm_device *dev = encoder->dev;
412 struct nouveau_drm *drm = nouveau_drm(dev);
413 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
414 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
415 int head = nouveau_crtc(encoder->crtc)->index;
416 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[
417 NV_CIO_CRE_LCD__INDEX];
418 uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
419 nv04_dac_output_offset(encoder);
420 uint32_t dacclk;
421
422 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
423
424 nv04_dfp_disable(dev, head);
425
426 /* Unbind any FP encoders from this head if we need the FP
427 * stuff enabled. */
428 if (tv_norm->kind == CTV_ENC_MODE) {
429 struct drm_encoder *enc;
430
431 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
432 struct dcb_output *dcb = nouveau_encoder(enc)->dcb;
433
434 if ((dcb->type == DCB_OUTPUT_TMDS ||
435 dcb->type == DCB_OUTPUT_LVDS) &&
436 !enc->crtc &&
437 nv04_dfp_get_bound_head(dev, dcb) == head) {
438 nv04_dfp_bind_head(dev, dcb, head ^ 1,
439 drm->vbios.fp.dual_link);
440 }
441 }
442
443 }
444
445 if (tv_norm->kind == CTV_ENC_MODE)
446 *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
447
448 /* Set the DACCLK register */
449 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
450
451 if (nv_device(drm->device)->card_type == NV_40)
452 dacclk |= 0x1a << 16;
453
454 if (tv_norm->kind == CTV_ENC_MODE) {
455 dacclk |= 0x20;
456
457 if (head)
458 dacclk |= 0x100;
459 else
460 dacclk &= ~0x100;
461
462 } else {
463 dacclk |= 0x10;
464
465 }
466
467 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
468 }
469
470 static void nv17_tv_mode_set(struct drm_encoder *encoder,
471 struct drm_display_mode *drm_mode,
472 struct drm_display_mode *adjusted_mode)
473 {
474 struct drm_device *dev = encoder->dev;
475 struct nouveau_drm *drm = nouveau_drm(dev);
476 int head = nouveau_crtc(encoder->crtc)->index;
477 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
478 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
479 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
480 int i;
481
482 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
483 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
484 regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
485 regs->tv_setup = 1;
486 regs->ramdac_8c0 = 0x0;
487
488 if (tv_norm->kind == TV_ENC_MODE) {
489 tv_regs->ptv_200 = 0x13111100;
490 if (head)
491 tv_regs->ptv_200 |= 0x10;
492
493 tv_regs->ptv_20c = 0x808010;
494 tv_regs->ptv_304 = 0x2d00000;
495 tv_regs->ptv_600 = 0x0;
496 tv_regs->ptv_60c = 0x0;
497 tv_regs->ptv_610 = 0x1e00000;
498
499 if (tv_norm->tv_enc_mode.vdisplay == 576) {
500 tv_regs->ptv_508 = 0x1200000;
501 tv_regs->ptv_614 = 0x33;
502
503 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
504 tv_regs->ptv_508 = 0xf00000;
505 tv_regs->ptv_614 = 0x13;
506 }
507
508 if (nv_device(drm->device)->card_type >= NV_30) {
509 tv_regs->ptv_500 = 0xe8e0;
510 tv_regs->ptv_504 = 0x1710;
511 tv_regs->ptv_604 = 0x0;
512 tv_regs->ptv_608 = 0x0;
513 } else {
514 if (tv_norm->tv_enc_mode.vdisplay == 576) {
515 tv_regs->ptv_604 = 0x20;
516 tv_regs->ptv_608 = 0x10;
517 tv_regs->ptv_500 = 0x19710;
518 tv_regs->ptv_504 = 0x68f0;
519
520 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
521 tv_regs->ptv_604 = 0x10;
522 tv_regs->ptv_608 = 0x20;
523 tv_regs->ptv_500 = 0x4b90;
524 tv_regs->ptv_504 = 0x1b480;
525 }
526 }
527
528 for (i = 0; i < 0x40; i++)
529 tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
530
531 } else {
532 struct drm_display_mode *output_mode =
533 &tv_norm->ctv_enc_mode.mode;
534
535 /* The registers in PRAMDAC+0xc00 control some timings and CSC
536 * parameters for the CTV encoder (It's only used for "HD" TV
537 * modes, I don't think I have enough working to guess what
538 * they exactly mean...), it's probably connected at the
539 * output of the FP encoder, but it also needs the analog
540 * encoder in its OR enabled and routed to the head it's
541 * using. It's enabled with the DACCLK register, bits [5:4].
542 */
543 for (i = 0; i < 38; i++)
544 regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
545
546 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
547 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
548 regs->fp_horiz_regs[FP_SYNC_START] =
549 output_mode->hsync_start - 1;
550 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
551 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
552 max((output_mode->hdisplay-600)/40 - 1, 1);
553
554 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
555 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
556 regs->fp_vert_regs[FP_SYNC_START] =
557 output_mode->vsync_start - 1;
558 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
559 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
560
561 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
562 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
563 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
564
565 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
566 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
567 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
568 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
569
570 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
571 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
572 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
573 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
574 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
575 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
576 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
577
578 regs->fp_debug_2 = 0;
579
580 regs->fp_margin_color = 0x801080;
581
582 }
583 }
584
585 static void nv17_tv_commit(struct drm_encoder *encoder)
586 {
587 struct drm_device *dev = encoder->dev;
588 struct nouveau_drm *drm = nouveau_drm(dev);
589 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
590 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
591 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
592
593 if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
594 nv17_tv_update_rescaler(encoder);
595 nv17_tv_update_properties(encoder);
596 } else {
597 nv17_ctv_update_rescaler(encoder);
598 }
599
600 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
601
602 /* This could use refinement for flatpanels, but it should work */
603 if (nv_device(drm->device)->chipset < 0x44)
604 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
605 nv04_dac_output_offset(encoder),
606 0xf0000000);
607 else
608 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
609 nv04_dac_output_offset(encoder),
610 0x00100000);
611
612 helper->dpms(encoder, DRM_MODE_DPMS_ON);
613
614 NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n",
615 drm_get_connector_name(
616 &nouveau_encoder_connector_get(nv_encoder)->base),
617 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
618 }
619
620 static void nv17_tv_save(struct drm_encoder *encoder)
621 {
622 struct drm_device *dev = encoder->dev;
623 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
624
625 nouveau_encoder(encoder)->restore.output =
626 NVReadRAMDAC(dev, 0,
627 NV_PRAMDAC_DACCLK +
628 nv04_dac_output_offset(encoder));
629
630 nv17_tv_state_save(dev, &tv_enc->saved_state);
631
632 tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
633 }
634
635 static void nv17_tv_restore(struct drm_encoder *encoder)
636 {
637 struct drm_device *dev = encoder->dev;
638
639 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
640 nv04_dac_output_offset(encoder),
641 nouveau_encoder(encoder)->restore.output);
642
643 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
644
645 nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
646 }
647
648 static int nv17_tv_create_resources(struct drm_encoder *encoder,
649 struct drm_connector *connector)
650 {
651 struct drm_device *dev = encoder->dev;
652 struct nouveau_drm *drm = nouveau_drm(dev);
653 struct drm_mode_config *conf = &dev->mode_config;
654 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
655 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
656 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
657 NUM_LD_TV_NORMS;
658 int i;
659
660 if (nouveau_tv_norm) {
661 for (i = 0; i < num_tv_norms; i++) {
662 if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
663 tv_enc->tv_norm = i;
664 break;
665 }
666 }
667
668 if (i == num_tv_norms)
669 NV_WARN(drm, "Invalid TV norm setting \"%s\"\n",
670 nouveau_tv_norm);
671 }
672
673 drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
674
675 drm_object_attach_property(&connector->base,
676 conf->tv_select_subconnector_property,
677 tv_enc->select_subconnector);
678 drm_object_attach_property(&connector->base,
679 conf->tv_subconnector_property,
680 tv_enc->subconnector);
681 drm_object_attach_property(&connector->base,
682 conf->tv_mode_property,
683 tv_enc->tv_norm);
684 drm_object_attach_property(&connector->base,
685 conf->tv_flicker_reduction_property,
686 tv_enc->flicker);
687 drm_object_attach_property(&connector->base,
688 conf->tv_saturation_property,
689 tv_enc->saturation);
690 drm_object_attach_property(&connector->base,
691 conf->tv_hue_property,
692 tv_enc->hue);
693 drm_object_attach_property(&connector->base,
694 conf->tv_overscan_property,
695 tv_enc->overscan);
696
697 return 0;
698 }
699
700 static int nv17_tv_set_property(struct drm_encoder *encoder,
701 struct drm_connector *connector,
702 struct drm_property *property,
703 uint64_t val)
704 {
705 struct drm_mode_config *conf = &encoder->dev->mode_config;
706 struct drm_crtc *crtc = encoder->crtc;
707 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
708 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
709 bool modes_changed = false;
710
711 if (property == conf->tv_overscan_property) {
712 tv_enc->overscan = val;
713 if (encoder->crtc) {
714 if (tv_norm->kind == CTV_ENC_MODE)
715 nv17_ctv_update_rescaler(encoder);
716 else
717 nv17_tv_update_rescaler(encoder);
718 }
719
720 } else if (property == conf->tv_saturation_property) {
721 if (tv_norm->kind != TV_ENC_MODE)
722 return -EINVAL;
723
724 tv_enc->saturation = val;
725 nv17_tv_update_properties(encoder);
726
727 } else if (property == conf->tv_hue_property) {
728 if (tv_norm->kind != TV_ENC_MODE)
729 return -EINVAL;
730
731 tv_enc->hue = val;
732 nv17_tv_update_properties(encoder);
733
734 } else if (property == conf->tv_flicker_reduction_property) {
735 if (tv_norm->kind != TV_ENC_MODE)
736 return -EINVAL;
737
738 tv_enc->flicker = val;
739 if (encoder->crtc)
740 nv17_tv_update_rescaler(encoder);
741
742 } else if (property == conf->tv_mode_property) {
743 if (connector->dpms != DRM_MODE_DPMS_OFF)
744 return -EINVAL;
745
746 tv_enc->tv_norm = val;
747
748 modes_changed = true;
749
750 } else if (property == conf->tv_select_subconnector_property) {
751 if (tv_norm->kind != TV_ENC_MODE)
752 return -EINVAL;
753
754 tv_enc->select_subconnector = val;
755 nv17_tv_update_properties(encoder);
756
757 } else {
758 return -EINVAL;
759 }
760
761 if (modes_changed) {
762 drm_helper_probe_single_connector_modes(connector, 0, 0);
763
764 /* Disable the crtc to ensure a full modeset is
765 * performed whenever it's turned on again. */
766 if (crtc) {
767 struct drm_mode_set modeset = {
768 .crtc = crtc,
769 };
770
771 drm_mode_set_config_internal(&modeset);
772 }
773 }
774
775 return 0;
776 }
777
778 static void nv17_tv_destroy(struct drm_encoder *encoder)
779 {
780 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
781
782 drm_encoder_cleanup(encoder);
783 kfree(tv_enc);
784 }
785
786 static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
787 .dpms = nv17_tv_dpms,
788 .save = nv17_tv_save,
789 .restore = nv17_tv_restore,
790 .mode_fixup = nv17_tv_mode_fixup,
791 .prepare = nv17_tv_prepare,
792 .commit = nv17_tv_commit,
793 .mode_set = nv17_tv_mode_set,
794 .detect = nv17_tv_detect,
795 };
796
797 static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
798 .get_modes = nv17_tv_get_modes,
799 .mode_valid = nv17_tv_mode_valid,
800 .create_resources = nv17_tv_create_resources,
801 .set_property = nv17_tv_set_property,
802 };
803
804 static struct drm_encoder_funcs nv17_tv_funcs = {
805 .destroy = nv17_tv_destroy,
806 };
807
808 int
809 nv17_tv_create(struct drm_connector *connector, struct dcb_output *entry)
810 {
811 struct drm_device *dev = connector->dev;
812 struct drm_encoder *encoder;
813 struct nv17_tv_encoder *tv_enc = NULL;
814
815 tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
816 if (!tv_enc)
817 return -ENOMEM;
818
819 tv_enc->overscan = 50;
820 tv_enc->flicker = 50;
821 tv_enc->saturation = 50;
822 tv_enc->hue = 0;
823 tv_enc->tv_norm = TV_NORM_PAL;
824 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
825 tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
826 tv_enc->pin_mask = 0;
827
828 encoder = to_drm_encoder(&tv_enc->base);
829
830 tv_enc->base.dcb = entry;
831 tv_enc->base.or = ffs(entry->or) - 1;
832
833 drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
834 drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
835 to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
836
837 encoder->possible_crtcs = entry->heads;
838 encoder->possible_clones = 0;
839
840 nv17_tv_create_resources(encoder, connector);
841 drm_mode_connector_attach_encoder(connector, encoder);
842 return 0;
843 }
Linux with added FPC-III support