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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
blob488686d490c0c7a96ba016e0f55a4beffcda6e4f
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <core/engine.h>
31 #include <linux/swiotlb.h>
32
33 #include <subdev/fb.h>
34 #include <subdev/vm.h>
35 #include <subdev/bar.h>
36
37 #include "nouveau_drm.h"
38 #include "nouveau_dma.h"
39 #include "nouveau_fence.h"
40
41 #include "nouveau_bo.h"
42 #include "nouveau_ttm.h"
43 #include "nouveau_gem.h"
44
45 /*
46 * NV10-NV40 tiling helpers
47 */
48
49 static void
50 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
51 u32 addr, u32 size, u32 pitch, u32 flags)
52 {
53 struct nouveau_drm *drm = nouveau_drm(dev);
54 int i = reg - drm->tile.reg;
55 struct nouveau_fb *pfb = nouveau_fb(drm->device);
56 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
57 struct nouveau_engine *engine;
58
59 nouveau_fence_unref(&reg->fence);
60
61 if (tile->pitch)
62 pfb->tile.fini(pfb, i, tile);
63
64 if (pitch)
65 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
66
67 pfb->tile.prog(pfb, i, tile);
68
69 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
70 engine->tile_prog(engine, i);
71 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
72 engine->tile_prog(engine, i);
73 }
74
75 static struct nouveau_drm_tile *
76 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 {
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91 }
92
93 static void
94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct nouveau_fence *fence)
96 {
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 tile->fence = nouveau_fence_ref(fence);
102 tile->used = false;
103 spin_unlock(&drm->tile.lock);
104 }
105 }
106
107 static struct nouveau_drm_tile *
108 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
109 u32 size, u32 pitch, u32 flags)
110 {
111 struct nouveau_drm *drm = nouveau_drm(dev);
112 struct nouveau_fb *pfb = nouveau_fb(drm->device);
113 struct nouveau_drm_tile *tile, *found = NULL;
114 int i;
115
116 for (i = 0; i < pfb->tile.regions; i++) {
117 tile = nv10_bo_get_tile_region(dev, i);
118
119 if (pitch && !found) {
120 found = tile;
121 continue;
122
123 } else if (tile && pfb->tile.region[i].pitch) {
124 /* Kill an unused tile region. */
125 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
126 }
127
128 nv10_bo_put_tile_region(dev, tile, NULL);
129 }
130
131 if (found)
132 nv10_bo_update_tile_region(dev, found, addr, size,
133 pitch, flags);
134 return found;
135 }
136
137 static void
138 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
139 {
140 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
141 struct drm_device *dev = drm->dev;
142 struct nouveau_bo *nvbo = nouveau_bo(bo);
143
144 if (unlikely(nvbo->gem.filp))
145 DRM_ERROR("bo %p still attached to GEM object\n", bo);
146 WARN_ON(nvbo->pin_refcnt > 0);
147 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
148 kfree(nvbo);
149 }
150
151 static void
152 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
153 int *align, int *size)
154 {
155 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
156 struct nouveau_device *device = nv_device(drm->device);
157
158 if (device->card_type < NV_50) {
159 if (nvbo->tile_mode) {
160 if (device->chipset >= 0x40) {
161 *align = 65536;
162 *size = roundup(*size, 64 * nvbo->tile_mode);
163
164 } else if (device->chipset >= 0x30) {
165 *align = 32768;
166 *size = roundup(*size, 64 * nvbo->tile_mode);
167
168 } else if (device->chipset >= 0x20) {
169 *align = 16384;
170 *size = roundup(*size, 64 * nvbo->tile_mode);
171
172 } else if (device->chipset >= 0x10) {
173 *align = 16384;
174 *size = roundup(*size, 32 * nvbo->tile_mode);
175 }
176 }
177 } else {
178 *size = roundup(*size, (1 << nvbo->page_shift));
179 *align = max((1 << nvbo->page_shift), *align);
180 }
181
182 *size = roundup(*size, PAGE_SIZE);
183 }
184
185 int
186 nouveau_bo_new(struct drm_device *dev, int size, int align,
187 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
188 struct sg_table *sg,
189 struct nouveau_bo **pnvbo)
190 {
191 struct nouveau_drm *drm = nouveau_drm(dev);
192 struct nouveau_bo *nvbo;
193 size_t acc_size;
194 int ret;
195 int type = ttm_bo_type_device;
196 int lpg_shift = 12;
197 int max_size;
198
199 if (drm->client.base.vm)
200 lpg_shift = drm->client.base.vm->vmm->lpg_shift;
201 max_size = INT_MAX & ~((1 << lpg_shift) - 1);
202
203 if (size <= 0 || size > max_size) {
204 nv_warn(drm, "skipped size %x\n", (u32)size);
205 return -EINVAL;
206 }
207
208 if (sg)
209 type = ttm_bo_type_sg;
210
211 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
212 if (!nvbo)
213 return -ENOMEM;
214 INIT_LIST_HEAD(&nvbo->head);
215 INIT_LIST_HEAD(&nvbo->entry);
216 INIT_LIST_HEAD(&nvbo->vma_list);
217 nvbo->tile_mode = tile_mode;
218 nvbo->tile_flags = tile_flags;
219 nvbo->bo.bdev = &drm->ttm.bdev;
220
221 nvbo->page_shift = 12;
222 if (drm->client.base.vm) {
223 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
224 nvbo->page_shift = drm->client.base.vm->vmm->lpg_shift;
225 }
226
227 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
228 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
229 nouveau_bo_placement_set(nvbo, flags, 0);
230
231 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
232 sizeof(struct nouveau_bo));
233
234 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
235 type, &nvbo->placement,
236 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
237 nouveau_bo_del_ttm);
238 if (ret) {
239 /* ttm will call nouveau_bo_del_ttm if it fails.. */
240 return ret;
241 }
242
243 *pnvbo = nvbo;
244 return 0;
245 }
246
247 static void
248 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
249 {
250 *n = 0;
251
252 if (type & TTM_PL_FLAG_VRAM)
253 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
254 if (type & TTM_PL_FLAG_TT)
255 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
256 if (type & TTM_PL_FLAG_SYSTEM)
257 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
258 }
259
260 static void
261 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
262 {
263 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
264 struct nouveau_fb *pfb = nouveau_fb(drm->device);
265 u32 vram_pages = pfb->ram->size >> PAGE_SHIFT;
266
267 if ((nv_device(drm->device)->card_type == NV_10 ||
268 nv_device(drm->device)->card_type == NV_11) &&
269 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
270 nvbo->bo.mem.num_pages < vram_pages / 4) {
271 /*
272 * Make sure that the color and depth buffers are handled
273 * by independent memory controller units. Up to a 9x
274 * speed up when alpha-blending and depth-test are enabled
275 * at the same time.
276 */
277 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
278 nvbo->placement.fpfn = vram_pages / 2;
279 nvbo->placement.lpfn = ~0;
280 } else {
281 nvbo->placement.fpfn = 0;
282 nvbo->placement.lpfn = vram_pages / 2;
283 }
284 }
285 }
286
287 void
288 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
289 {
290 struct ttm_placement *pl = &nvbo->placement;
291 uint32_t flags = TTM_PL_MASK_CACHING |
292 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
293
294 pl->placement = nvbo->placements;
295 set_placement_list(nvbo->placements, &pl->num_placement,
296 type, flags);
297
298 pl->busy_placement = nvbo->busy_placements;
299 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
300 type | busy, flags);
301
302 set_placement_range(nvbo, type);
303 }
304
305 int
306 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
307 {
308 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
309 struct ttm_buffer_object *bo = &nvbo->bo;
310 int ret;
311
312 ret = ttm_bo_reserve(bo, false, false, false, 0);
313 if (ret)
314 goto out;
315
316 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
317 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
318 1 << bo->mem.mem_type, memtype);
319 ret = -EINVAL;
320 goto out;
321 }
322
323 if (nvbo->pin_refcnt++)
324 goto out;
325
326 nouveau_bo_placement_set(nvbo, memtype, 0);
327
328 ret = nouveau_bo_validate(nvbo, false, false);
329 if (ret == 0) {
330 switch (bo->mem.mem_type) {
331 case TTM_PL_VRAM:
332 drm->gem.vram_available -= bo->mem.size;
333 break;
334 case TTM_PL_TT:
335 drm->gem.gart_available -= bo->mem.size;
336 break;
337 default:
338 break;
339 }
340 }
341 out:
342 ttm_bo_unreserve(bo);
343 return ret;
344 }
345
346 int
347 nouveau_bo_unpin(struct nouveau_bo *nvbo)
348 {
349 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
350 struct ttm_buffer_object *bo = &nvbo->bo;
351 int ret, ref;
352
353 ret = ttm_bo_reserve(bo, false, false, false, 0);
354 if (ret)
355 return ret;
356
357 ref = --nvbo->pin_refcnt;
358 WARN_ON_ONCE(ref < 0);
359 if (ref)
360 goto out;
361
362 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
363
364 ret = nouveau_bo_validate(nvbo, false, false);
365 if (ret == 0) {
366 switch (bo->mem.mem_type) {
367 case TTM_PL_VRAM:
368 drm->gem.vram_available += bo->mem.size;
369 break;
370 case TTM_PL_TT:
371 drm->gem.gart_available += bo->mem.size;
372 break;
373 default:
374 break;
375 }
376 }
377
378 out:
379 ttm_bo_unreserve(bo);
380 return ret;
381 }
382
383 int
384 nouveau_bo_map(struct nouveau_bo *nvbo)
385 {
386 int ret;
387
388 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
389 if (ret)
390 return ret;
391
392 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
393 ttm_bo_unreserve(&nvbo->bo);
394 return ret;
395 }
396
397 void
398 nouveau_bo_unmap(struct nouveau_bo *nvbo)
399 {
400 if (nvbo)
401 ttm_bo_kunmap(&nvbo->kmap);
402 }
403
404 int
405 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
406 bool no_wait_gpu)
407 {
408 int ret;
409
410 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
411 interruptible, no_wait_gpu);
412 if (ret)
413 return ret;
414
415 return 0;
416 }
417
418 u16
419 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
420 {
421 bool is_iomem;
422 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
423 mem = &mem[index];
424 if (is_iomem)
425 return ioread16_native((void __force __iomem *)mem);
426 else
427 return *mem;
428 }
429
430 void
431 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
432 {
433 bool is_iomem;
434 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
435 mem = &mem[index];
436 if (is_iomem)
437 iowrite16_native(val, (void __force __iomem *)mem);
438 else
439 *mem = val;
440 }
441
442 u32
443 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
444 {
445 bool is_iomem;
446 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
447 mem = &mem[index];
448 if (is_iomem)
449 return ioread32_native((void __force __iomem *)mem);
450 else
451 return *mem;
452 }
453
454 void
455 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
456 {
457 bool is_iomem;
458 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
459 mem = &mem[index];
460 if (is_iomem)
461 iowrite32_native(val, (void __force __iomem *)mem);
462 else
463 *mem = val;
464 }
465
466 static struct ttm_tt *
467 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
468 uint32_t page_flags, struct page *dummy_read)
469 {
470 #if __OS_HAS_AGP
471 struct nouveau_drm *drm = nouveau_bdev(bdev);
472 struct drm_device *dev = drm->dev;
473
474 if (drm->agp.stat == ENABLED) {
475 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
476 page_flags, dummy_read);
477 }
478 #endif
479
480 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
481 }
482
483 static int
484 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
485 {
486 /* We'll do this from user space. */
487 return 0;
488 }
489
490 static int
491 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
492 struct ttm_mem_type_manager *man)
493 {
494 struct nouveau_drm *drm = nouveau_bdev(bdev);
495
496 switch (type) {
497 case TTM_PL_SYSTEM:
498 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
499 man->available_caching = TTM_PL_MASK_CACHING;
500 man->default_caching = TTM_PL_FLAG_CACHED;
501 break;
502 case TTM_PL_VRAM:
503 if (nv_device(drm->device)->card_type >= NV_50) {
504 man->func = &nouveau_vram_manager;
505 man->io_reserve_fastpath = false;
506 man->use_io_reserve_lru = true;
507 } else {
508 man->func = &ttm_bo_manager_func;
509 }
510 man->flags = TTM_MEMTYPE_FLAG_FIXED |
511 TTM_MEMTYPE_FLAG_MAPPABLE;
512 man->available_caching = TTM_PL_FLAG_UNCACHED |
513 TTM_PL_FLAG_WC;
514 man->default_caching = TTM_PL_FLAG_WC;
515 break;
516 case TTM_PL_TT:
517 if (nv_device(drm->device)->card_type >= NV_50)
518 man->func = &nouveau_gart_manager;
519 else
520 if (drm->agp.stat != ENABLED)
521 man->func = &nv04_gart_manager;
522 else
523 man->func = &ttm_bo_manager_func;
524
525 if (drm->agp.stat == ENABLED) {
526 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
527 man->available_caching = TTM_PL_FLAG_UNCACHED |
528 TTM_PL_FLAG_WC;
529 man->default_caching = TTM_PL_FLAG_WC;
530 } else {
531 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
532 TTM_MEMTYPE_FLAG_CMA;
533 man->available_caching = TTM_PL_MASK_CACHING;
534 man->default_caching = TTM_PL_FLAG_CACHED;
535 }
536
537 break;
538 default:
539 return -EINVAL;
540 }
541 return 0;
542 }
543
544 static void
545 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
546 {
547 struct nouveau_bo *nvbo = nouveau_bo(bo);
548
549 switch (bo->mem.mem_type) {
550 case TTM_PL_VRAM:
551 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
552 TTM_PL_FLAG_SYSTEM);
553 break;
554 default:
555 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
556 break;
557 }
558
559 *pl = nvbo->placement;
560 }
561
562
563 static int
564 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
565 {
566 int ret = RING_SPACE(chan, 2);
567 if (ret == 0) {
568 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
569 OUT_RING (chan, handle & 0x0000ffff);
570 FIRE_RING (chan);
571 }
572 return ret;
573 }
574
575 static int
576 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
577 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
578 {
579 struct nouveau_mem *node = old_mem->mm_node;
580 int ret = RING_SPACE(chan, 10);
581 if (ret == 0) {
582 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
583 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
584 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
585 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
586 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
587 OUT_RING (chan, PAGE_SIZE);
588 OUT_RING (chan, PAGE_SIZE);
589 OUT_RING (chan, PAGE_SIZE);
590 OUT_RING (chan, new_mem->num_pages);
591 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
592 }
593 return ret;
594 }
595
596 static int
597 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
598 {
599 int ret = RING_SPACE(chan, 2);
600 if (ret == 0) {
601 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
602 OUT_RING (chan, handle);
603 }
604 return ret;
605 }
606
607 static int
608 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
609 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
610 {
611 struct nouveau_mem *node = old_mem->mm_node;
612 u64 src_offset = node->vma[0].offset;
613 u64 dst_offset = node->vma[1].offset;
614 u32 page_count = new_mem->num_pages;
615 int ret;
616
617 page_count = new_mem->num_pages;
618 while (page_count) {
619 int line_count = (page_count > 8191) ? 8191 : page_count;
620
621 ret = RING_SPACE(chan, 11);
622 if (ret)
623 return ret;
624
625 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
626 OUT_RING (chan, upper_32_bits(src_offset));
627 OUT_RING (chan, lower_32_bits(src_offset));
628 OUT_RING (chan, upper_32_bits(dst_offset));
629 OUT_RING (chan, lower_32_bits(dst_offset));
630 OUT_RING (chan, PAGE_SIZE);
631 OUT_RING (chan, PAGE_SIZE);
632 OUT_RING (chan, PAGE_SIZE);
633 OUT_RING (chan, line_count);
634 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
635 OUT_RING (chan, 0x00000110);
636
637 page_count -= line_count;
638 src_offset += (PAGE_SIZE * line_count);
639 dst_offset += (PAGE_SIZE * line_count);
640 }
641
642 return 0;
643 }
644
645 static int
646 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
647 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
648 {
649 struct nouveau_mem *node = old_mem->mm_node;
650 u64 src_offset = node->vma[0].offset;
651 u64 dst_offset = node->vma[1].offset;
652 u32 page_count = new_mem->num_pages;
653 int ret;
654
655 page_count = new_mem->num_pages;
656 while (page_count) {
657 int line_count = (page_count > 2047) ? 2047 : page_count;
658
659 ret = RING_SPACE(chan, 12);
660 if (ret)
661 return ret;
662
663 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
664 OUT_RING (chan, upper_32_bits(dst_offset));
665 OUT_RING (chan, lower_32_bits(dst_offset));
666 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
667 OUT_RING (chan, upper_32_bits(src_offset));
668 OUT_RING (chan, lower_32_bits(src_offset));
669 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
670 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
671 OUT_RING (chan, PAGE_SIZE); /* line_length */
672 OUT_RING (chan, line_count);
673 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
674 OUT_RING (chan, 0x00100110);
675
676 page_count -= line_count;
677 src_offset += (PAGE_SIZE * line_count);
678 dst_offset += (PAGE_SIZE * line_count);
679 }
680
681 return 0;
682 }
683
684 static int
685 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
686 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
687 {
688 struct nouveau_mem *node = old_mem->mm_node;
689 u64 src_offset = node->vma[0].offset;
690 u64 dst_offset = node->vma[1].offset;
691 u32 page_count = new_mem->num_pages;
692 int ret;
693
694 page_count = new_mem->num_pages;
695 while (page_count) {
696 int line_count = (page_count > 8191) ? 8191 : page_count;
697
698 ret = RING_SPACE(chan, 11);
699 if (ret)
700 return ret;
701
702 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
703 OUT_RING (chan, upper_32_bits(src_offset));
704 OUT_RING (chan, lower_32_bits(src_offset));
705 OUT_RING (chan, upper_32_bits(dst_offset));
706 OUT_RING (chan, lower_32_bits(dst_offset));
707 OUT_RING (chan, PAGE_SIZE);
708 OUT_RING (chan, PAGE_SIZE);
709 OUT_RING (chan, PAGE_SIZE);
710 OUT_RING (chan, line_count);
711 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
712 OUT_RING (chan, 0x00000110);
713
714 page_count -= line_count;
715 src_offset += (PAGE_SIZE * line_count);
716 dst_offset += (PAGE_SIZE * line_count);
717 }
718
719 return 0;
720 }
721
722 static int
723 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
724 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
725 {
726 struct nouveau_mem *node = old_mem->mm_node;
727 int ret = RING_SPACE(chan, 7);
728 if (ret == 0) {
729 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
730 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
731 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
732 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
733 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
734 OUT_RING (chan, 0x00000000 /* COPY */);
735 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
736 }
737 return ret;
738 }
739
740 static int
741 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
742 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
743 {
744 struct nouveau_mem *node = old_mem->mm_node;
745 int ret = RING_SPACE(chan, 7);
746 if (ret == 0) {
747 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
748 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
749 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
750 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
751 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
752 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
753 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
754 }
755 return ret;
756 }
757
758 static int
759 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
760 {
761 int ret = RING_SPACE(chan, 6);
762 if (ret == 0) {
763 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
764 OUT_RING (chan, handle);
765 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
766 OUT_RING (chan, NvNotify0);
767 OUT_RING (chan, NvDmaFB);
768 OUT_RING (chan, NvDmaFB);
769 }
770
771 return ret;
772 }
773
774 static int
775 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
776 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
777 {
778 struct nouveau_mem *node = old_mem->mm_node;
779 u64 length = (new_mem->num_pages << PAGE_SHIFT);
780 u64 src_offset = node->vma[0].offset;
781 u64 dst_offset = node->vma[1].offset;
782 int src_tiled = !!node->memtype;
783 int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype;
784 int ret;
785
786 while (length) {
787 u32 amount, stride, height;
788
789 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
790 if (ret)
791 return ret;
792
793 amount = min(length, (u64)(4 * 1024 * 1024));
794 stride = 16 * 4;
795 height = amount / stride;
796
797 if (src_tiled) {
798 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
799 OUT_RING (chan, 0);
800 OUT_RING (chan, 0);
801 OUT_RING (chan, stride);
802 OUT_RING (chan, height);
803 OUT_RING (chan, 1);
804 OUT_RING (chan, 0);
805 OUT_RING (chan, 0);
806 } else {
807 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
808 OUT_RING (chan, 1);
809 }
810 if (dst_tiled) {
811 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
812 OUT_RING (chan, 0);
813 OUT_RING (chan, 0);
814 OUT_RING (chan, stride);
815 OUT_RING (chan, height);
816 OUT_RING (chan, 1);
817 OUT_RING (chan, 0);
818 OUT_RING (chan, 0);
819 } else {
820 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
821 OUT_RING (chan, 1);
822 }
823
824 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
825 OUT_RING (chan, upper_32_bits(src_offset));
826 OUT_RING (chan, upper_32_bits(dst_offset));
827 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
828 OUT_RING (chan, lower_32_bits(src_offset));
829 OUT_RING (chan, lower_32_bits(dst_offset));
830 OUT_RING (chan, stride);
831 OUT_RING (chan, stride);
832 OUT_RING (chan, stride);
833 OUT_RING (chan, height);
834 OUT_RING (chan, 0x00000101);
835 OUT_RING (chan, 0x00000000);
836 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
837 OUT_RING (chan, 0);
838
839 length -= amount;
840 src_offset += amount;
841 dst_offset += amount;
842 }
843
844 return 0;
845 }
846
847 static int
848 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
849 {
850 int ret = RING_SPACE(chan, 4);
851 if (ret == 0) {
852 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
853 OUT_RING (chan, handle);
854 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
855 OUT_RING (chan, NvNotify0);
856 }
857
858 return ret;
859 }
860
861 static inline uint32_t
862 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
863 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
864 {
865 if (mem->mem_type == TTM_PL_TT)
866 return NvDmaTT;
867 return NvDmaFB;
868 }
869
870 static int
871 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
872 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
873 {
874 u32 src_offset = old_mem->start << PAGE_SHIFT;
875 u32 dst_offset = new_mem->start << PAGE_SHIFT;
876 u32 page_count = new_mem->num_pages;
877 int ret;
878
879 ret = RING_SPACE(chan, 3);
880 if (ret)
881 return ret;
882
883 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
884 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
885 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
886
887 page_count = new_mem->num_pages;
888 while (page_count) {
889 int line_count = (page_count > 2047) ? 2047 : page_count;
890
891 ret = RING_SPACE(chan, 11);
892 if (ret)
893 return ret;
894
895 BEGIN_NV04(chan, NvSubCopy,
896 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
897 OUT_RING (chan, src_offset);
898 OUT_RING (chan, dst_offset);
899 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
900 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
901 OUT_RING (chan, PAGE_SIZE); /* line_length */
902 OUT_RING (chan, line_count);
903 OUT_RING (chan, 0x00000101);
904 OUT_RING (chan, 0x00000000);
905 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
906 OUT_RING (chan, 0);
907
908 page_count -= line_count;
909 src_offset += (PAGE_SIZE * line_count);
910 dst_offset += (PAGE_SIZE * line_count);
911 }
912
913 return 0;
914 }
915
916 static int
917 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
918 struct ttm_mem_reg *mem)
919 {
920 struct nouveau_mem *old_node = bo->mem.mm_node;
921 struct nouveau_mem *new_node = mem->mm_node;
922 u64 size = (u64)mem->num_pages << PAGE_SHIFT;
923 int ret;
924
925 ret = nouveau_vm_get(nv_client(drm)->vm, size, old_node->page_shift,
926 NV_MEM_ACCESS_RW, &old_node->vma[0]);
927 if (ret)
928 return ret;
929
930 ret = nouveau_vm_get(nv_client(drm)->vm, size, new_node->page_shift,
931 NV_MEM_ACCESS_RW, &old_node->vma[1]);
932 if (ret) {
933 nouveau_vm_put(&old_node->vma[0]);
934 return ret;
935 }
936
937 nouveau_vm_map(&old_node->vma[0], old_node);
938 nouveau_vm_map(&old_node->vma[1], new_node);
939 return 0;
940 }
941
942 static int
943 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
944 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
945 {
946 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
947 struct nouveau_channel *chan = drm->ttm.chan;
948 struct nouveau_fence *fence;
949 int ret;
950
951 /* create temporary vmas for the transfer and attach them to the
952 * old nouveau_mem node, these will get cleaned up after ttm has
953 * destroyed the ttm_mem_reg
954 */
955 if (nv_device(drm->device)->card_type >= NV_50) {
956 ret = nouveau_bo_move_prep(drm, bo, new_mem);
957 if (ret)
958 return ret;
959 }
960
961 mutex_lock_nested(&chan->cli->mutex, SINGLE_DEPTH_NESTING);
962 ret = nouveau_fence_sync(bo->sync_obj, chan);
963 if (ret == 0) {
964 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
965 if (ret == 0) {
966 ret = nouveau_fence_new(chan, false, &fence);
967 if (ret == 0) {
968 ret = ttm_bo_move_accel_cleanup(bo, fence,
969 evict,
970 no_wait_gpu,
971 new_mem);
972 nouveau_fence_unref(&fence);
973 }
974 }
975 }
976 mutex_unlock(&chan->cli->mutex);
977 return ret;
978 }
979
980 void
981 nouveau_bo_move_init(struct nouveau_drm *drm)
982 {
983 static const struct {
984 const char *name;
985 int engine;
986 u32 oclass;
987 int (*exec)(struct nouveau_channel *,
988 struct ttm_buffer_object *,
989 struct ttm_mem_reg *, struct ttm_mem_reg *);
990 int (*init)(struct nouveau_channel *, u32 handle);
991 } _methods[] = {
992 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
993 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
994 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
995 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
996 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
997 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
998 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
999 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1000 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1001 {},
1002 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1003 }, *mthd = _methods;
1004 const char *name = "CPU";
1005 int ret;
1006
1007 do {
1008 struct nouveau_object *object;
1009 struct nouveau_channel *chan;
1010 u32 handle = (mthd->engine << 16) | mthd->oclass;
1011
1012 if (mthd->engine)
1013 chan = drm->cechan;
1014 else
1015 chan = drm->channel;
1016 if (chan == NULL)
1017 continue;
1018
1019 ret = nouveau_object_new(nv_object(drm), chan->handle, handle,
1020 mthd->oclass, NULL, 0, &object);
1021 if (ret == 0) {
1022 ret = mthd->init(chan, handle);
1023 if (ret) {
1024 nouveau_object_del(nv_object(drm),
1025 chan->handle, handle);
1026 continue;
1027 }
1028
1029 drm->ttm.move = mthd->exec;
1030 drm->ttm.chan = chan;
1031 name = mthd->name;
1032 break;
1033 }
1034 } while ((++mthd)->exec);
1035
1036 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1037 }
1038
1039 static int
1040 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1041 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1042 {
1043 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1044 struct ttm_placement placement;
1045 struct ttm_mem_reg tmp_mem;
1046 int ret;
1047
1048 placement.fpfn = placement.lpfn = 0;
1049 placement.num_placement = placement.num_busy_placement = 1;
1050 placement.placement = placement.busy_placement = &placement_memtype;
1051
1052 tmp_mem = *new_mem;
1053 tmp_mem.mm_node = NULL;
1054 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1055 if (ret)
1056 return ret;
1057
1058 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1059 if (ret)
1060 goto out;
1061
1062 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1063 if (ret)
1064 goto out;
1065
1066 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1067 out:
1068 ttm_bo_mem_put(bo, &tmp_mem);
1069 return ret;
1070 }
1071
1072 static int
1073 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1074 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1075 {
1076 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1077 struct ttm_placement placement;
1078 struct ttm_mem_reg tmp_mem;
1079 int ret;
1080
1081 placement.fpfn = placement.lpfn = 0;
1082 placement.num_placement = placement.num_busy_placement = 1;
1083 placement.placement = placement.busy_placement = &placement_memtype;
1084
1085 tmp_mem = *new_mem;
1086 tmp_mem.mm_node = NULL;
1087 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1088 if (ret)
1089 return ret;
1090
1091 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1092 if (ret)
1093 goto out;
1094
1095 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1096 if (ret)
1097 goto out;
1098
1099 out:
1100 ttm_bo_mem_put(bo, &tmp_mem);
1101 return ret;
1102 }
1103
1104 static void
1105 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1106 {
1107 struct nouveau_bo *nvbo = nouveau_bo(bo);
1108 struct nouveau_vma *vma;
1109
1110 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1111 if (bo->destroy != nouveau_bo_del_ttm)
1112 return;
1113
1114 list_for_each_entry(vma, &nvbo->vma_list, head) {
1115 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1116 (new_mem->mem_type == TTM_PL_VRAM ||
1117 nvbo->page_shift != vma->vm->vmm->lpg_shift)) {
1118 nouveau_vm_map(vma, new_mem->mm_node);
1119 } else {
1120 nouveau_vm_unmap(vma);
1121 }
1122 }
1123 }
1124
1125 static int
1126 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1127 struct nouveau_drm_tile **new_tile)
1128 {
1129 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1130 struct drm_device *dev = drm->dev;
1131 struct nouveau_bo *nvbo = nouveau_bo(bo);
1132 u64 offset = new_mem->start << PAGE_SHIFT;
1133
1134 *new_tile = NULL;
1135 if (new_mem->mem_type != TTM_PL_VRAM)
1136 return 0;
1137
1138 if (nv_device(drm->device)->card_type >= NV_10) {
1139 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1140 nvbo->tile_mode,
1141 nvbo->tile_flags);
1142 }
1143
1144 return 0;
1145 }
1146
1147 static void
1148 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1149 struct nouveau_drm_tile *new_tile,
1150 struct nouveau_drm_tile **old_tile)
1151 {
1152 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1153 struct drm_device *dev = drm->dev;
1154
1155 nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj);
1156 *old_tile = new_tile;
1157 }
1158
1159 static int
1160 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1161 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1162 {
1163 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1164 struct nouveau_bo *nvbo = nouveau_bo(bo);
1165 struct ttm_mem_reg *old_mem = &bo->mem;
1166 struct nouveau_drm_tile *new_tile = NULL;
1167 int ret = 0;
1168
1169 if (nv_device(drm->device)->card_type < NV_50) {
1170 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1171 if (ret)
1172 return ret;
1173 }
1174
1175 /* Fake bo copy. */
1176 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1177 BUG_ON(bo->mem.mm_node != NULL);
1178 bo->mem = *new_mem;
1179 new_mem->mm_node = NULL;
1180 goto out;
1181 }
1182
1183 /* Hardware assisted copy. */
1184 if (drm->ttm.move) {
1185 if (new_mem->mem_type == TTM_PL_SYSTEM)
1186 ret = nouveau_bo_move_flipd(bo, evict, intr,
1187 no_wait_gpu, new_mem);
1188 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1189 ret = nouveau_bo_move_flips(bo, evict, intr,
1190 no_wait_gpu, new_mem);
1191 else
1192 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1193 no_wait_gpu, new_mem);
1194 if (!ret)
1195 goto out;
1196 }
1197
1198 /* Fallback to software copy. */
1199 spin_lock(&bo->bdev->fence_lock);
1200 ret = ttm_bo_wait(bo, true, intr, no_wait_gpu);
1201 spin_unlock(&bo->bdev->fence_lock);
1202 if (ret == 0)
1203 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1204
1205 out:
1206 if (nv_device(drm->device)->card_type < NV_50) {
1207 if (ret)
1208 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1209 else
1210 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1211 }
1212
1213 return ret;
1214 }
1215
1216 static int
1217 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1218 {
1219 struct nouveau_bo *nvbo = nouveau_bo(bo);
1220
1221 return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
1222 }
1223
1224 static int
1225 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1226 {
1227 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1228 struct nouveau_drm *drm = nouveau_bdev(bdev);
1229 struct nouveau_mem *node = mem->mm_node;
1230 struct drm_device *dev = drm->dev;
1231 int ret;
1232
1233 mem->bus.addr = NULL;
1234 mem->bus.offset = 0;
1235 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1236 mem->bus.base = 0;
1237 mem->bus.is_iomem = false;
1238 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1239 return -EINVAL;
1240 switch (mem->mem_type) {
1241 case TTM_PL_SYSTEM:
1242 /* System memory */
1243 return 0;
1244 case TTM_PL_TT:
1245 #if __OS_HAS_AGP
1246 if (drm->agp.stat == ENABLED) {
1247 mem->bus.offset = mem->start << PAGE_SHIFT;
1248 mem->bus.base = drm->agp.base;
1249 mem->bus.is_iomem = !dev->agp->cant_use_aperture;
1250 }
1251 #endif
1252 if (!node->memtype)
1253 /* untiled */
1254 break;
1255 /* fallthrough, tiled memory */
1256 case TTM_PL_VRAM:
1257 mem->bus.offset = mem->start << PAGE_SHIFT;
1258 mem->bus.base = pci_resource_start(dev->pdev, 1);
1259 mem->bus.is_iomem = true;
1260 if (nv_device(drm->device)->card_type >= NV_50) {
1261 struct nouveau_bar *bar = nouveau_bar(drm->device);
1262
1263 ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1264 &node->bar_vma);
1265 if (ret)
1266 return ret;
1267
1268 mem->bus.offset = node->bar_vma.offset;
1269 }
1270 break;
1271 default:
1272 return -EINVAL;
1273 }
1274 return 0;
1275 }
1276
1277 static void
1278 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1279 {
1280 struct nouveau_drm *drm = nouveau_bdev(bdev);
1281 struct nouveau_bar *bar = nouveau_bar(drm->device);
1282 struct nouveau_mem *node = mem->mm_node;
1283
1284 if (!node->bar_vma.node)
1285 return;
1286
1287 bar->unmap(bar, &node->bar_vma);
1288 }
1289
1290 static int
1291 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1292 {
1293 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1294 struct nouveau_bo *nvbo = nouveau_bo(bo);
1295 struct nouveau_device *device = nv_device(drm->device);
1296 u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT;
1297 int ret;
1298
1299 /* as long as the bo isn't in vram, and isn't tiled, we've got
1300 * nothing to do here.
1301 */
1302 if (bo->mem.mem_type != TTM_PL_VRAM) {
1303 if (nv_device(drm->device)->card_type < NV_50 ||
1304 !nouveau_bo_tile_layout(nvbo))
1305 return 0;
1306
1307 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1308 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1309
1310 ret = nouveau_bo_validate(nvbo, false, false);
1311 if (ret)
1312 return ret;
1313 }
1314 return 0;
1315 }
1316
1317 /* make sure bo is in mappable vram */
1318 if (nv_device(drm->device)->card_type >= NV_50 ||
1319 bo->mem.start + bo->mem.num_pages < mappable)
1320 return 0;
1321
1322
1323 nvbo->placement.fpfn = 0;
1324 nvbo->placement.lpfn = mappable;
1325 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1326 return nouveau_bo_validate(nvbo, false, false);
1327 }
1328
1329 static int
1330 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1331 {
1332 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1333 struct nouveau_drm *drm;
1334 struct drm_device *dev;
1335 unsigned i;
1336 int r;
1337 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1338
1339 if (ttm->state != tt_unpopulated)
1340 return 0;
1341
1342 if (slave && ttm->sg) {
1343 /* make userspace faulting work */
1344 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1345 ttm_dma->dma_address, ttm->num_pages);
1346 ttm->state = tt_unbound;
1347 return 0;
1348 }
1349
1350 drm = nouveau_bdev(ttm->bdev);
1351 dev = drm->dev;
1352
1353 #if __OS_HAS_AGP
1354 if (drm->agp.stat == ENABLED) {
1355 return ttm_agp_tt_populate(ttm);
1356 }
1357 #endif
1358
1359 #ifdef CONFIG_SWIOTLB
1360 if (swiotlb_nr_tbl()) {
1361 return ttm_dma_populate((void *)ttm, dev->dev);
1362 }
1363 #endif
1364
1365 r = ttm_pool_populate(ttm);
1366 if (r) {
1367 return r;
1368 }
1369
1370 for (i = 0; i < ttm->num_pages; i++) {
1371 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
1372 0, PAGE_SIZE,
1373 PCI_DMA_BIDIRECTIONAL);
1374 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
1375 while (--i) {
1376 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1377 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1378 ttm_dma->dma_address[i] = 0;
1379 }
1380 ttm_pool_unpopulate(ttm);
1381 return -EFAULT;
1382 }
1383 }
1384 return 0;
1385 }
1386
1387 static void
1388 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1389 {
1390 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1391 struct nouveau_drm *drm;
1392 struct drm_device *dev;
1393 unsigned i;
1394 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1395
1396 if (slave)
1397 return;
1398
1399 drm = nouveau_bdev(ttm->bdev);
1400 dev = drm->dev;
1401
1402 #if __OS_HAS_AGP
1403 if (drm->agp.stat == ENABLED) {
1404 ttm_agp_tt_unpopulate(ttm);
1405 return;
1406 }
1407 #endif
1408
1409 #ifdef CONFIG_SWIOTLB
1410 if (swiotlb_nr_tbl()) {
1411 ttm_dma_unpopulate((void *)ttm, dev->dev);
1412 return;
1413 }
1414 #endif
1415
1416 for (i = 0; i < ttm->num_pages; i++) {
1417 if (ttm_dma->dma_address[i]) {
1418 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1419 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1420 }
1421 }
1422
1423 ttm_pool_unpopulate(ttm);
1424 }
1425
1426 void
1427 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1428 {
1429 struct nouveau_fence *new_fence = nouveau_fence_ref(fence);
1430 struct nouveau_fence *old_fence = NULL;
1431
1432 spin_lock(&nvbo->bo.bdev->fence_lock);
1433 old_fence = nvbo->bo.sync_obj;
1434 nvbo->bo.sync_obj = new_fence;
1435 spin_unlock(&nvbo->bo.bdev->fence_lock);
1436
1437 nouveau_fence_unref(&old_fence);
1438 }
1439
1440 static void
1441 nouveau_bo_fence_unref(void **sync_obj)
1442 {
1443 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1444 }
1445
1446 static void *
1447 nouveau_bo_fence_ref(void *sync_obj)
1448 {
1449 return nouveau_fence_ref(sync_obj);
1450 }
1451
1452 static bool
1453 nouveau_bo_fence_signalled(void *sync_obj)
1454 {
1455 return nouveau_fence_done(sync_obj);
1456 }
1457
1458 static int
1459 nouveau_bo_fence_wait(void *sync_obj, bool lazy, bool intr)
1460 {
1461 return nouveau_fence_wait(sync_obj, lazy, intr);
1462 }
1463
1464 static int
1465 nouveau_bo_fence_flush(void *sync_obj)
1466 {
1467 return 0;
1468 }
1469
1470 struct ttm_bo_driver nouveau_bo_driver = {
1471 .ttm_tt_create = &nouveau_ttm_tt_create,
1472 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1473 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1474 .invalidate_caches = nouveau_bo_invalidate_caches,
1475 .init_mem_type = nouveau_bo_init_mem_type,
1476 .evict_flags = nouveau_bo_evict_flags,
1477 .move_notify = nouveau_bo_move_ntfy,
1478 .move = nouveau_bo_move,
1479 .verify_access = nouveau_bo_verify_access,
1480 .sync_obj_signaled = nouveau_bo_fence_signalled,
1481 .sync_obj_wait = nouveau_bo_fence_wait,
1482 .sync_obj_flush = nouveau_bo_fence_flush,
1483 .sync_obj_unref = nouveau_bo_fence_unref,
1484 .sync_obj_ref = nouveau_bo_fence_ref,
1485 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1486 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1487 .io_mem_free = &nouveau_ttm_io_mem_free,
1488 };
1489
1490 struct nouveau_vma *
1491 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1492 {
1493 struct nouveau_vma *vma;
1494 list_for_each_entry(vma, &nvbo->vma_list, head) {
1495 if (vma->vm == vm)
1496 return vma;
1497 }
1498
1499 return NULL;
1500 }
1501
1502 int
1503 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1504 struct nouveau_vma *vma)
1505 {
1506 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1507 int ret;
1508
1509 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1510 NV_MEM_ACCESS_RW, vma);
1511 if (ret)
1512 return ret;
1513
1514 if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1515 (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1516 nvbo->page_shift != vma->vm->vmm->lpg_shift))
1517 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1518
1519 list_add_tail(&vma->head, &nvbo->vma_list);
1520 vma->refcount = 1;
1521 return 0;
1522 }
1523
1524 void
1525 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1526 {
1527 if (vma->node) {
1528 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1529 nouveau_vm_unmap(vma);
1530 nouveau_vm_put(vma);
1531 list_del(&vma->head);
1532 }
1533 }
Linux with added FPC-III support