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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / kv_dpm.c
blob351db361239db1d2800f845b2e9e9d02d541cc2b
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "radeon.h"
26 #include "cikd.h"
27 #include "r600_dpm.h"
28 #include "kv_dpm.h"
29 #include "radeon_asic.h"
30 #include <linux/seq_file.h>
31
32 #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5
33 #define KV_MINIMUM_ENGINE_CLOCK 800
34 #define SMC_RAM_END 0x40000
35
36 static void kv_init_graphics_levels(struct radeon_device *rdev);
37 static int kv_calculate_ds_divider(struct radeon_device *rdev);
38 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
39 static int kv_calculate_dpm_settings(struct radeon_device *rdev);
40 static void kv_enable_new_levels(struct radeon_device *rdev);
41 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
42 struct radeon_ps *new_rps);
43 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
44 static int kv_set_enabled_levels(struct radeon_device *rdev);
45 static int kv_force_dpm_highest(struct radeon_device *rdev);
46 static int kv_force_dpm_lowest(struct radeon_device *rdev);
47 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
48 struct radeon_ps *new_rps,
49 struct radeon_ps *old_rps);
50 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
51 int min_temp, int max_temp);
52 static int kv_init_fps_limits(struct radeon_device *rdev);
53
54 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
55 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
56 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
57 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
58
59 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
60 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
61 extern void cik_update_cg(struct radeon_device *rdev,
62 u32 block, bool enable);
63
64 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
65 {
66 { 0, 4, 1 },
67 { 1, 4, 1 },
68 { 2, 5, 1 },
69 { 3, 4, 2 },
70 { 4, 1, 1 },
71 { 5, 5, 2 },
72 { 6, 6, 1 },
73 { 7, 9, 2 },
74 { 0xffffffff }
75 };
76
77 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
78 {
79 { 0, 4, 1 },
80 { 0xffffffff }
81 };
82
83 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
84 {
85 { 0, 4, 1 },
86 { 0xffffffff }
87 };
88
89 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
90 {
91 { 0, 4, 1 },
92 { 0xffffffff }
93 };
94
95 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
96 {
97 { 0, 4, 1 },
98 { 0xffffffff }
99 };
100
101 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
102 {
103 { 0, 4, 1 },
104 { 1, 4, 1 },
105 { 2, 5, 1 },
106 { 3, 4, 1 },
107 { 4, 1, 1 },
108 { 5, 5, 1 },
109 { 6, 6, 1 },
110 { 7, 9, 1 },
111 { 8, 4, 1 },
112 { 9, 2, 1 },
113 { 10, 3, 1 },
114 { 11, 6, 1 },
115 { 12, 8, 2 },
116 { 13, 1, 1 },
117 { 14, 2, 1 },
118 { 15, 3, 1 },
119 { 16, 1, 1 },
120 { 17, 4, 1 },
121 { 18, 3, 1 },
122 { 19, 1, 1 },
123 { 20, 8, 1 },
124 { 21, 5, 1 },
125 { 22, 1, 1 },
126 { 23, 1, 1 },
127 { 24, 4, 1 },
128 { 27, 6, 1 },
129 { 28, 1, 1 },
130 { 0xffffffff }
131 };
132
133 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
134 {
135 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
136 };
137
138 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
139 {
140 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
141 };
142
143 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
144 {
145 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
146 };
147
148 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
149 {
150 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
151 };
152
153 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
154 {
155 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
156 };
157
158 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
159 {
160 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
161 };
162
163 static const struct kv_pt_config_reg didt_config_kv[] =
164 {
165 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
166 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
167 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
168 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
169 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
170 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
171 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
172 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
173 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
174 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
175 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
176 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
177 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
178 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
179 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
180 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
181 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
182 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
183 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
184 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
185 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
186 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
187 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
188 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
189 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
190 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
191 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
192 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
193 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
194 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
195 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
196 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
197 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
198 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
199 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
200 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
201 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
202 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
203 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
204 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
205 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
206 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
207 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
208 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
209 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
210 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
211 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
212 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
213 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
214 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
215 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
216 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
217 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
218 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
219 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
220 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
221 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
222 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
223 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
224 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
225 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
226 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
227 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
228 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
229 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
230 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
231 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
232 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
233 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
234 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
235 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
236 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
237 { 0xFFFFFFFF }
238 };
239
240 static struct kv_ps *kv_get_ps(struct radeon_ps *rps)
241 {
242 struct kv_ps *ps = rps->ps_priv;
243
244 return ps;
245 }
246
247 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
248 {
249 struct kv_power_info *pi = rdev->pm.dpm.priv;
250
251 return pi;
252 }
253
254 #if 0
255 static void kv_program_local_cac_table(struct radeon_device *rdev,
256 const struct kv_lcac_config_values *local_cac_table,
257 const struct kv_lcac_config_reg *local_cac_reg)
258 {
259 u32 i, count, data;
260 const struct kv_lcac_config_values *values = local_cac_table;
261
262 while (values->block_id != 0xffffffff) {
263 count = values->signal_id;
264 for (i = 0; i < count; i++) {
265 data = ((values->block_id << local_cac_reg->block_shift) &
266 local_cac_reg->block_mask);
267 data |= ((i << local_cac_reg->signal_shift) &
268 local_cac_reg->signal_mask);
269 data |= ((values->t << local_cac_reg->t_shift) &
270 local_cac_reg->t_mask);
271 data |= ((1 << local_cac_reg->enable_shift) &
272 local_cac_reg->enable_mask);
273 WREG32_SMC(local_cac_reg->cntl, data);
274 }
275 values++;
276 }
277 }
278 #endif
279
280 static int kv_program_pt_config_registers(struct radeon_device *rdev,
281 const struct kv_pt_config_reg *cac_config_regs)
282 {
283 const struct kv_pt_config_reg *config_regs = cac_config_regs;
284 u32 data;
285 u32 cache = 0;
286
287 if (config_regs == NULL)
288 return -EINVAL;
289
290 while (config_regs->offset != 0xFFFFFFFF) {
291 if (config_regs->type == KV_CONFIGREG_CACHE) {
292 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
293 } else {
294 switch (config_regs->type) {
295 case KV_CONFIGREG_SMC_IND:
296 data = RREG32_SMC(config_regs->offset);
297 break;
298 case KV_CONFIGREG_DIDT_IND:
299 data = RREG32_DIDT(config_regs->offset);
300 break;
301 default:
302 data = RREG32(config_regs->offset << 2);
303 break;
304 }
305
306 data &= ~config_regs->mask;
307 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
308 data |= cache;
309 cache = 0;
310
311 switch (config_regs->type) {
312 case KV_CONFIGREG_SMC_IND:
313 WREG32_SMC(config_regs->offset, data);
314 break;
315 case KV_CONFIGREG_DIDT_IND:
316 WREG32_DIDT(config_regs->offset, data);
317 break;
318 default:
319 WREG32(config_regs->offset << 2, data);
320 break;
321 }
322 }
323 config_regs++;
324 }
325
326 return 0;
327 }
328
329 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
330 {
331 struct kv_power_info *pi = kv_get_pi(rdev);
332 u32 data;
333
334 if (pi->caps_sq_ramping) {
335 data = RREG32_DIDT(DIDT_SQ_CTRL0);
336 if (enable)
337 data |= DIDT_CTRL_EN;
338 else
339 data &= ~DIDT_CTRL_EN;
340 WREG32_DIDT(DIDT_SQ_CTRL0, data);
341 }
342
343 if (pi->caps_db_ramping) {
344 data = RREG32_DIDT(DIDT_DB_CTRL0);
345 if (enable)
346 data |= DIDT_CTRL_EN;
347 else
348 data &= ~DIDT_CTRL_EN;
349 WREG32_DIDT(DIDT_DB_CTRL0, data);
350 }
351
352 if (pi->caps_td_ramping) {
353 data = RREG32_DIDT(DIDT_TD_CTRL0);
354 if (enable)
355 data |= DIDT_CTRL_EN;
356 else
357 data &= ~DIDT_CTRL_EN;
358 WREG32_DIDT(DIDT_TD_CTRL0, data);
359 }
360
361 if (pi->caps_tcp_ramping) {
362 data = RREG32_DIDT(DIDT_TCP_CTRL0);
363 if (enable)
364 data |= DIDT_CTRL_EN;
365 else
366 data &= ~DIDT_CTRL_EN;
367 WREG32_DIDT(DIDT_TCP_CTRL0, data);
368 }
369 }
370
371 static int kv_enable_didt(struct radeon_device *rdev, bool enable)
372 {
373 struct kv_power_info *pi = kv_get_pi(rdev);
374 int ret;
375
376 if (pi->caps_sq_ramping ||
377 pi->caps_db_ramping ||
378 pi->caps_td_ramping ||
379 pi->caps_tcp_ramping) {
380 cik_enter_rlc_safe_mode(rdev);
381
382 if (enable) {
383 ret = kv_program_pt_config_registers(rdev, didt_config_kv);
384 if (ret) {
385 cik_exit_rlc_safe_mode(rdev);
386 return ret;
387 }
388 }
389
390 kv_do_enable_didt(rdev, enable);
391
392 cik_exit_rlc_safe_mode(rdev);
393 }
394
395 return 0;
396 }
397
398 #if 0
399 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev)
400 {
401 struct kv_power_info *pi = kv_get_pi(rdev);
402
403 if (pi->caps_cac) {
404 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
405 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
406 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
407
408 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
409 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
410 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
411
412 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
413 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
414 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
415
416 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
417 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
418 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
419
420 WREG32_SMC(LCAC_MC3_OVR_SEL, 0);
421 WREG32_SMC(LCAC_MC3_OVR_VAL, 0);
422 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
423
424 WREG32_SMC(LCAC_CPL_OVR_SEL, 0);
425 WREG32_SMC(LCAC_CPL_OVR_VAL, 0);
426 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
427 }
428 }
429 #endif
430
431 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
432 {
433 struct kv_power_info *pi = kv_get_pi(rdev);
434 int ret = 0;
435
436 if (pi->caps_cac) {
437 if (enable) {
438 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
439 if (ret)
440 pi->cac_enabled = false;
441 else
442 pi->cac_enabled = true;
443 } else if (pi->cac_enabled) {
444 kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
445 pi->cac_enabled = false;
446 }
447 }
448
449 return ret;
450 }
451
452 static int kv_process_firmware_header(struct radeon_device *rdev)
453 {
454 struct kv_power_info *pi = kv_get_pi(rdev);
455 u32 tmp;
456 int ret;
457
458 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
459 offsetof(SMU7_Firmware_Header, DpmTable),
460 &tmp, pi->sram_end);
461
462 if (ret == 0)
463 pi->dpm_table_start = tmp;
464
465 ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
466 offsetof(SMU7_Firmware_Header, SoftRegisters),
467 &tmp, pi->sram_end);
468
469 if (ret == 0)
470 pi->soft_regs_start = tmp;
471
472 return ret;
473 }
474
475 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
476 {
477 struct kv_power_info *pi = kv_get_pi(rdev);
478 int ret;
479
480 pi->graphics_voltage_change_enable = 1;
481
482 ret = kv_copy_bytes_to_smc(rdev,
483 pi->dpm_table_start +
484 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
485 &pi->graphics_voltage_change_enable,
486 sizeof(u8), pi->sram_end);
487
488 return ret;
489 }
490
491 static int kv_set_dpm_interval(struct radeon_device *rdev)
492 {
493 struct kv_power_info *pi = kv_get_pi(rdev);
494 int ret;
495
496 pi->graphics_interval = 1;
497
498 ret = kv_copy_bytes_to_smc(rdev,
499 pi->dpm_table_start +
500 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
501 &pi->graphics_interval,
502 sizeof(u8), pi->sram_end);
503
504 return ret;
505 }
506
507 static int kv_set_dpm_boot_state(struct radeon_device *rdev)
508 {
509 struct kv_power_info *pi = kv_get_pi(rdev);
510 int ret;
511
512 ret = kv_copy_bytes_to_smc(rdev,
513 pi->dpm_table_start +
514 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
515 &pi->graphics_boot_level,
516 sizeof(u8), pi->sram_end);
517
518 return ret;
519 }
520
521 static void kv_program_vc(struct radeon_device *rdev)
522 {
523 WREG32_SMC(CG_FTV_0, 0x3FFFC100);
524 }
525
526 static void kv_clear_vc(struct radeon_device *rdev)
527 {
528 WREG32_SMC(CG_FTV_0, 0);
529 }
530
531 static int kv_set_divider_value(struct radeon_device *rdev,
532 u32 index, u32 sclk)
533 {
534 struct kv_power_info *pi = kv_get_pi(rdev);
535 struct atom_clock_dividers dividers;
536 int ret;
537
538 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
539 sclk, false, &dividers);
540 if (ret)
541 return ret;
542
543 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
544 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
545
546 return 0;
547 }
548
549 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
550 u16 voltage)
551 {
552 return 6200 - (voltage * 25);
553 }
554
555 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
556 u32 vid_2bit)
557 {
558 struct kv_power_info *pi = kv_get_pi(rdev);
559 u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev,
560 &pi->sys_info.vid_mapping_table,
561 vid_2bit);
562
563 return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
564 }
565
566
567 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
568 {
569 struct kv_power_info *pi = kv_get_pi(rdev);
570
571 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
572 pi->graphics_level[index].MinVddNb =
573 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
574
575 return 0;
576 }
577
578 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
579 {
580 struct kv_power_info *pi = kv_get_pi(rdev);
581
582 pi->graphics_level[index].AT = cpu_to_be16((u16)at);
583
584 return 0;
585 }
586
587 static void kv_dpm_power_level_enable(struct radeon_device *rdev,
588 u32 index, bool enable)
589 {
590 struct kv_power_info *pi = kv_get_pi(rdev);
591
592 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
593 }
594
595 static void kv_start_dpm(struct radeon_device *rdev)
596 {
597 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
598
599 tmp |= GLOBAL_PWRMGT_EN;
600 WREG32_SMC(GENERAL_PWRMGT, tmp);
601
602 kv_smc_dpm_enable(rdev, true);
603 }
604
605 static void kv_stop_dpm(struct radeon_device *rdev)
606 {
607 kv_smc_dpm_enable(rdev, false);
608 }
609
610 static void kv_start_am(struct radeon_device *rdev)
611 {
612 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
613
614 sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
615 sclk_pwrmgt_cntl |= DYNAMIC_PM_EN;
616
617 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
618 }
619
620 static void kv_reset_am(struct radeon_device *rdev)
621 {
622 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
623
624 sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
625
626 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
627 }
628
629 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
630 {
631 return kv_notify_message_to_smu(rdev, freeze ?
632 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
633 }
634
635 static int kv_force_lowest_valid(struct radeon_device *rdev)
636 {
637 return kv_force_dpm_lowest(rdev);
638 }
639
640 static int kv_unforce_levels(struct radeon_device *rdev)
641 {
642 if (rdev->family == CHIP_KABINI)
643 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
644 else
645 return kv_set_enabled_levels(rdev);
646 }
647
648 static int kv_update_sclk_t(struct radeon_device *rdev)
649 {
650 struct kv_power_info *pi = kv_get_pi(rdev);
651 u32 low_sclk_interrupt_t = 0;
652 int ret = 0;
653
654 if (pi->caps_sclk_throttle_low_notification) {
655 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
656
657 ret = kv_copy_bytes_to_smc(rdev,
658 pi->dpm_table_start +
659 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
660 (u8 *)&low_sclk_interrupt_t,
661 sizeof(u32), pi->sram_end);
662 }
663 return ret;
664 }
665
666 static int kv_program_bootup_state(struct radeon_device *rdev)
667 {
668 struct kv_power_info *pi = kv_get_pi(rdev);
669 u32 i;
670 struct radeon_clock_voltage_dependency_table *table =
671 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
672
673 if (table && table->count) {
674 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
675 if (table->entries[i].clk == pi->boot_pl.sclk)
676 break;
677 }
678
679 pi->graphics_boot_level = (u8)i;
680 kv_dpm_power_level_enable(rdev, i, true);
681 } else {
682 struct sumo_sclk_voltage_mapping_table *table =
683 &pi->sys_info.sclk_voltage_mapping_table;
684
685 if (table->num_max_dpm_entries == 0)
686 return -EINVAL;
687
688 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
689 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
690 break;
691 }
692
693 pi->graphics_boot_level = (u8)i;
694 kv_dpm_power_level_enable(rdev, i, true);
695 }
696 return 0;
697 }
698
699 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
700 {
701 struct kv_power_info *pi = kv_get_pi(rdev);
702 int ret;
703
704 pi->graphics_therm_throttle_enable = 1;
705
706 ret = kv_copy_bytes_to_smc(rdev,
707 pi->dpm_table_start +
708 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
709 &pi->graphics_therm_throttle_enable,
710 sizeof(u8), pi->sram_end);
711
712 return ret;
713 }
714
715 static int kv_upload_dpm_settings(struct radeon_device *rdev)
716 {
717 struct kv_power_info *pi = kv_get_pi(rdev);
718 int ret;
719
720 ret = kv_copy_bytes_to_smc(rdev,
721 pi->dpm_table_start +
722 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
723 (u8 *)&pi->graphics_level,
724 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
725 pi->sram_end);
726
727 if (ret)
728 return ret;
729
730 ret = kv_copy_bytes_to_smc(rdev,
731 pi->dpm_table_start +
732 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
733 &pi->graphics_dpm_level_count,
734 sizeof(u8), pi->sram_end);
735
736 return ret;
737 }
738
739 static u32 kv_get_clock_difference(u32 a, u32 b)
740 {
741 return (a >= b) ? a - b : b - a;
742 }
743
744 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
745 {
746 struct kv_power_info *pi = kv_get_pi(rdev);
747 u32 value;
748
749 if (pi->caps_enable_dfs_bypass) {
750 if (kv_get_clock_difference(clk, 40000) < 200)
751 value = 3;
752 else if (kv_get_clock_difference(clk, 30000) < 200)
753 value = 2;
754 else if (kv_get_clock_difference(clk, 20000) < 200)
755 value = 7;
756 else if (kv_get_clock_difference(clk, 15000) < 200)
757 value = 6;
758 else if (kv_get_clock_difference(clk, 10000) < 200)
759 value = 8;
760 else
761 value = 0;
762 } else {
763 value = 0;
764 }
765
766 return value;
767 }
768
769 static int kv_populate_uvd_table(struct radeon_device *rdev)
770 {
771 struct kv_power_info *pi = kv_get_pi(rdev);
772 struct radeon_uvd_clock_voltage_dependency_table *table =
773 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
774 struct atom_clock_dividers dividers;
775 int ret;
776 u32 i;
777
778 if (table == NULL || table->count == 0)
779 return 0;
780
781 pi->uvd_level_count = 0;
782 for (i = 0; i < table->count; i++) {
783 if (pi->high_voltage_t &&
784 (pi->high_voltage_t < table->entries[i].v))
785 break;
786
787 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
788 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
789 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
790
791 pi->uvd_level[i].VClkBypassCntl =
792 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
793 pi->uvd_level[i].DClkBypassCntl =
794 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
795
796 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
797 table->entries[i].vclk, false, &dividers);
798 if (ret)
799 return ret;
800 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
801
802 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
803 table->entries[i].dclk, false, &dividers);
804 if (ret)
805 return ret;
806 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
807
808 pi->uvd_level_count++;
809 }
810
811 ret = kv_copy_bytes_to_smc(rdev,
812 pi->dpm_table_start +
813 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
814 (u8 *)&pi->uvd_level_count,
815 sizeof(u8), pi->sram_end);
816 if (ret)
817 return ret;
818
819 pi->uvd_interval = 1;
820
821 ret = kv_copy_bytes_to_smc(rdev,
822 pi->dpm_table_start +
823 offsetof(SMU7_Fusion_DpmTable, UVDInterval),
824 &pi->uvd_interval,
825 sizeof(u8), pi->sram_end);
826 if (ret)
827 return ret;
828
829 ret = kv_copy_bytes_to_smc(rdev,
830 pi->dpm_table_start +
831 offsetof(SMU7_Fusion_DpmTable, UvdLevel),
832 (u8 *)&pi->uvd_level,
833 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
834 pi->sram_end);
835
836 return ret;
837
838 }
839
840 static int kv_populate_vce_table(struct radeon_device *rdev)
841 {
842 struct kv_power_info *pi = kv_get_pi(rdev);
843 int ret;
844 u32 i;
845 struct radeon_vce_clock_voltage_dependency_table *table =
846 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
847 struct atom_clock_dividers dividers;
848
849 if (table == NULL || table->count == 0)
850 return 0;
851
852 pi->vce_level_count = 0;
853 for (i = 0; i < table->count; i++) {
854 if (pi->high_voltage_t &&
855 pi->high_voltage_t < table->entries[i].v)
856 break;
857
858 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
859 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
860
861 pi->vce_level[i].ClkBypassCntl =
862 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
863
864 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
865 table->entries[i].evclk, false, &dividers);
866 if (ret)
867 return ret;
868 pi->vce_level[i].Divider = (u8)dividers.post_div;
869
870 pi->vce_level_count++;
871 }
872
873 ret = kv_copy_bytes_to_smc(rdev,
874 pi->dpm_table_start +
875 offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
876 (u8 *)&pi->vce_level_count,
877 sizeof(u8),
878 pi->sram_end);
879 if (ret)
880 return ret;
881
882 pi->vce_interval = 1;
883
884 ret = kv_copy_bytes_to_smc(rdev,
885 pi->dpm_table_start +
886 offsetof(SMU7_Fusion_DpmTable, VCEInterval),
887 (u8 *)&pi->vce_interval,
888 sizeof(u8),
889 pi->sram_end);
890 if (ret)
891 return ret;
892
893 ret = kv_copy_bytes_to_smc(rdev,
894 pi->dpm_table_start +
895 offsetof(SMU7_Fusion_DpmTable, VceLevel),
896 (u8 *)&pi->vce_level,
897 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
898 pi->sram_end);
899
900 return ret;
901 }
902
903 static int kv_populate_samu_table(struct radeon_device *rdev)
904 {
905 struct kv_power_info *pi = kv_get_pi(rdev);
906 struct radeon_clock_voltage_dependency_table *table =
907 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
908 struct atom_clock_dividers dividers;
909 int ret;
910 u32 i;
911
912 if (table == NULL || table->count == 0)
913 return 0;
914
915 pi->samu_level_count = 0;
916 for (i = 0; i < table->count; i++) {
917 if (pi->high_voltage_t &&
918 pi->high_voltage_t < table->entries[i].v)
919 break;
920
921 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
922 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
923
924 pi->samu_level[i].ClkBypassCntl =
925 (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
926
927 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
928 table->entries[i].clk, false, &dividers);
929 if (ret)
930 return ret;
931 pi->samu_level[i].Divider = (u8)dividers.post_div;
932
933 pi->samu_level_count++;
934 }
935
936 ret = kv_copy_bytes_to_smc(rdev,
937 pi->dpm_table_start +
938 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
939 (u8 *)&pi->samu_level_count,
940 sizeof(u8),
941 pi->sram_end);
942 if (ret)
943 return ret;
944
945 pi->samu_interval = 1;
946
947 ret = kv_copy_bytes_to_smc(rdev,
948 pi->dpm_table_start +
949 offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
950 (u8 *)&pi->samu_interval,
951 sizeof(u8),
952 pi->sram_end);
953 if (ret)
954 return ret;
955
956 ret = kv_copy_bytes_to_smc(rdev,
957 pi->dpm_table_start +
958 offsetof(SMU7_Fusion_DpmTable, SamuLevel),
959 (u8 *)&pi->samu_level,
960 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
961 pi->sram_end);
962 if (ret)
963 return ret;
964
965 return ret;
966 }
967
968
969 static int kv_populate_acp_table(struct radeon_device *rdev)
970 {
971 struct kv_power_info *pi = kv_get_pi(rdev);
972 struct radeon_clock_voltage_dependency_table *table =
973 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
974 struct atom_clock_dividers dividers;
975 int ret;
976 u32 i;
977
978 if (table == NULL || table->count == 0)
979 return 0;
980
981 pi->acp_level_count = 0;
982 for (i = 0; i < table->count; i++) {
983 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
984 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
985
986 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
987 table->entries[i].clk, false, &dividers);
988 if (ret)
989 return ret;
990 pi->acp_level[i].Divider = (u8)dividers.post_div;
991
992 pi->acp_level_count++;
993 }
994
995 ret = kv_copy_bytes_to_smc(rdev,
996 pi->dpm_table_start +
997 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
998 (u8 *)&pi->acp_level_count,
999 sizeof(u8),
1000 pi->sram_end);
1001 if (ret)
1002 return ret;
1003
1004 pi->acp_interval = 1;
1005
1006 ret = kv_copy_bytes_to_smc(rdev,
1007 pi->dpm_table_start +
1008 offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1009 (u8 *)&pi->acp_interval,
1010 sizeof(u8),
1011 pi->sram_end);
1012 if (ret)
1013 return ret;
1014
1015 ret = kv_copy_bytes_to_smc(rdev,
1016 pi->dpm_table_start +
1017 offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1018 (u8 *)&pi->acp_level,
1019 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1020 pi->sram_end);
1021 if (ret)
1022 return ret;
1023
1024 return ret;
1025 }
1026
1027 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
1028 {
1029 struct kv_power_info *pi = kv_get_pi(rdev);
1030 u32 i;
1031 struct radeon_clock_voltage_dependency_table *table =
1032 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1033
1034 if (table && table->count) {
1035 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1036 if (pi->caps_enable_dfs_bypass) {
1037 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1038 pi->graphics_level[i].ClkBypassCntl = 3;
1039 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1040 pi->graphics_level[i].ClkBypassCntl = 2;
1041 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1042 pi->graphics_level[i].ClkBypassCntl = 7;
1043 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1044 pi->graphics_level[i].ClkBypassCntl = 6;
1045 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1046 pi->graphics_level[i].ClkBypassCntl = 8;
1047 else
1048 pi->graphics_level[i].ClkBypassCntl = 0;
1049 } else {
1050 pi->graphics_level[i].ClkBypassCntl = 0;
1051 }
1052 }
1053 } else {
1054 struct sumo_sclk_voltage_mapping_table *table =
1055 &pi->sys_info.sclk_voltage_mapping_table;
1056 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1057 if (pi->caps_enable_dfs_bypass) {
1058 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1059 pi->graphics_level[i].ClkBypassCntl = 3;
1060 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1061 pi->graphics_level[i].ClkBypassCntl = 2;
1062 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1063 pi->graphics_level[i].ClkBypassCntl = 7;
1064 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1065 pi->graphics_level[i].ClkBypassCntl = 6;
1066 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1067 pi->graphics_level[i].ClkBypassCntl = 8;
1068 else
1069 pi->graphics_level[i].ClkBypassCntl = 0;
1070 } else {
1071 pi->graphics_level[i].ClkBypassCntl = 0;
1072 }
1073 }
1074 }
1075 }
1076
1077 static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
1078 {
1079 return kv_notify_message_to_smu(rdev, enable ?
1080 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1081 }
1082
1083 static void kv_reset_acp_boot_level(struct radeon_device *rdev)
1084 {
1085 struct kv_power_info *pi = kv_get_pi(rdev);
1086
1087 pi->acp_boot_level = 0xff;
1088 }
1089
1090 static void kv_update_current_ps(struct radeon_device *rdev,
1091 struct radeon_ps *rps)
1092 {
1093 struct kv_ps *new_ps = kv_get_ps(rps);
1094 struct kv_power_info *pi = kv_get_pi(rdev);
1095
1096 pi->current_rps = *rps;
1097 pi->current_ps = *new_ps;
1098 pi->current_rps.ps_priv = &pi->current_ps;
1099 }
1100
1101 static void kv_update_requested_ps(struct radeon_device *rdev,
1102 struct radeon_ps *rps)
1103 {
1104 struct kv_ps *new_ps = kv_get_ps(rps);
1105 struct kv_power_info *pi = kv_get_pi(rdev);
1106
1107 pi->requested_rps = *rps;
1108 pi->requested_ps = *new_ps;
1109 pi->requested_rps.ps_priv = &pi->requested_ps;
1110 }
1111
1112 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1113 {
1114 struct kv_power_info *pi = kv_get_pi(rdev);
1115 int ret;
1116
1117 if (pi->bapm_enable) {
1118 ret = kv_smc_bapm_enable(rdev, enable);
1119 if (ret)
1120 DRM_ERROR("kv_smc_bapm_enable failed\n");
1121 }
1122 }
1123
1124 int kv_dpm_enable(struct radeon_device *rdev)
1125 {
1126 struct kv_power_info *pi = kv_get_pi(rdev);
1127 int ret;
1128
1129 ret = kv_process_firmware_header(rdev);
1130 if (ret) {
1131 DRM_ERROR("kv_process_firmware_header failed\n");
1132 return ret;
1133 }
1134 kv_init_fps_limits(rdev);
1135 kv_init_graphics_levels(rdev);
1136 ret = kv_program_bootup_state(rdev);
1137 if (ret) {
1138 DRM_ERROR("kv_program_bootup_state failed\n");
1139 return ret;
1140 }
1141 kv_calculate_dfs_bypass_settings(rdev);
1142 ret = kv_upload_dpm_settings(rdev);
1143 if (ret) {
1144 DRM_ERROR("kv_upload_dpm_settings failed\n");
1145 return ret;
1146 }
1147 ret = kv_populate_uvd_table(rdev);
1148 if (ret) {
1149 DRM_ERROR("kv_populate_uvd_table failed\n");
1150 return ret;
1151 }
1152 ret = kv_populate_vce_table(rdev);
1153 if (ret) {
1154 DRM_ERROR("kv_populate_vce_table failed\n");
1155 return ret;
1156 }
1157 ret = kv_populate_samu_table(rdev);
1158 if (ret) {
1159 DRM_ERROR("kv_populate_samu_table failed\n");
1160 return ret;
1161 }
1162 ret = kv_populate_acp_table(rdev);
1163 if (ret) {
1164 DRM_ERROR("kv_populate_acp_table failed\n");
1165 return ret;
1166 }
1167 kv_program_vc(rdev);
1168 #if 0
1169 kv_initialize_hardware_cac_manager(rdev);
1170 #endif
1171 kv_start_am(rdev);
1172 if (pi->enable_auto_thermal_throttling) {
1173 ret = kv_enable_auto_thermal_throttling(rdev);
1174 if (ret) {
1175 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1176 return ret;
1177 }
1178 }
1179 ret = kv_enable_dpm_voltage_scaling(rdev);
1180 if (ret) {
1181 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1182 return ret;
1183 }
1184 ret = kv_set_dpm_interval(rdev);
1185 if (ret) {
1186 DRM_ERROR("kv_set_dpm_interval failed\n");
1187 return ret;
1188 }
1189 ret = kv_set_dpm_boot_state(rdev);
1190 if (ret) {
1191 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1192 return ret;
1193 }
1194 ret = kv_enable_ulv(rdev, true);
1195 if (ret) {
1196 DRM_ERROR("kv_enable_ulv failed\n");
1197 return ret;
1198 }
1199 kv_start_dpm(rdev);
1200 ret = kv_enable_didt(rdev, true);
1201 if (ret) {
1202 DRM_ERROR("kv_enable_didt failed\n");
1203 return ret;
1204 }
1205 ret = kv_enable_smc_cac(rdev, true);
1206 if (ret) {
1207 DRM_ERROR("kv_enable_smc_cac failed\n");
1208 return ret;
1209 }
1210
1211 kv_reset_acp_boot_level(rdev);
1212
1213 ret = kv_smc_bapm_enable(rdev, false);
1214 if (ret) {
1215 DRM_ERROR("kv_smc_bapm_enable failed\n");
1216 return ret;
1217 }
1218
1219 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1220
1221 return ret;
1222 }
1223
1224 int kv_dpm_late_enable(struct radeon_device *rdev)
1225 {
1226 int ret = 0;
1227
1228 if (rdev->irq.installed &&
1229 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1230 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1231 if (ret) {
1232 DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1233 return ret;
1234 }
1235 rdev->irq.dpm_thermal = true;
1236 radeon_irq_set(rdev);
1237 }
1238
1239 /* powerdown unused blocks for now */
1240 kv_dpm_powergate_acp(rdev, true);
1241 kv_dpm_powergate_samu(rdev, true);
1242 kv_dpm_powergate_vce(rdev, true);
1243 kv_dpm_powergate_uvd(rdev, true);
1244
1245 return ret;
1246 }
1247
1248 void kv_dpm_disable(struct radeon_device *rdev)
1249 {
1250 kv_smc_bapm_enable(rdev, false);
1251
1252 /* powerup blocks */
1253 kv_dpm_powergate_acp(rdev, false);
1254 kv_dpm_powergate_samu(rdev, false);
1255 kv_dpm_powergate_vce(rdev, false);
1256 kv_dpm_powergate_uvd(rdev, false);
1257
1258 kv_enable_smc_cac(rdev, false);
1259 kv_enable_didt(rdev, false);
1260 kv_clear_vc(rdev);
1261 kv_stop_dpm(rdev);
1262 kv_enable_ulv(rdev, false);
1263 kv_reset_am(rdev);
1264
1265 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1266 }
1267
1268 #if 0
1269 static int kv_write_smc_soft_register(struct radeon_device *rdev,
1270 u16 reg_offset, u32 value)
1271 {
1272 struct kv_power_info *pi = kv_get_pi(rdev);
1273
1274 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1275 (u8 *)&value, sizeof(u16), pi->sram_end);
1276 }
1277
1278 static int kv_read_smc_soft_register(struct radeon_device *rdev,
1279 u16 reg_offset, u32 *value)
1280 {
1281 struct kv_power_info *pi = kv_get_pi(rdev);
1282
1283 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1284 value, pi->sram_end);
1285 }
1286 #endif
1287
1288 static void kv_init_sclk_t(struct radeon_device *rdev)
1289 {
1290 struct kv_power_info *pi = kv_get_pi(rdev);
1291
1292 pi->low_sclk_interrupt_t = 0;
1293 }
1294
1295 static int kv_init_fps_limits(struct radeon_device *rdev)
1296 {
1297 struct kv_power_info *pi = kv_get_pi(rdev);
1298 int ret = 0;
1299
1300 if (pi->caps_fps) {
1301 u16 tmp;
1302
1303 tmp = 45;
1304 pi->fps_high_t = cpu_to_be16(tmp);
1305 ret = kv_copy_bytes_to_smc(rdev,
1306 pi->dpm_table_start +
1307 offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1308 (u8 *)&pi->fps_high_t,
1309 sizeof(u16), pi->sram_end);
1310
1311 tmp = 30;
1312 pi->fps_low_t = cpu_to_be16(tmp);
1313
1314 ret = kv_copy_bytes_to_smc(rdev,
1315 pi->dpm_table_start +
1316 offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1317 (u8 *)&pi->fps_low_t,
1318 sizeof(u16), pi->sram_end);
1319
1320 }
1321 return ret;
1322 }
1323
1324 static void kv_init_powergate_state(struct radeon_device *rdev)
1325 {
1326 struct kv_power_info *pi = kv_get_pi(rdev);
1327
1328 pi->uvd_power_gated = false;
1329 pi->vce_power_gated = false;
1330 pi->samu_power_gated = false;
1331 pi->acp_power_gated = false;
1332
1333 }
1334
1335 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1336 {
1337 return kv_notify_message_to_smu(rdev, enable ?
1338 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1339 }
1340
1341 #if 0
1342 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1343 {
1344 return kv_notify_message_to_smu(rdev, enable ?
1345 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1346 }
1347 #endif
1348
1349 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1350 {
1351 return kv_notify_message_to_smu(rdev, enable ?
1352 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1353 }
1354
1355 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1356 {
1357 return kv_notify_message_to_smu(rdev, enable ?
1358 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1359 }
1360
1361 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1362 {
1363 struct kv_power_info *pi = kv_get_pi(rdev);
1364 struct radeon_uvd_clock_voltage_dependency_table *table =
1365 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1366 int ret;
1367
1368 if (!gate) {
1369 if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state)
1370 pi->uvd_boot_level = table->count - 1;
1371 else
1372 pi->uvd_boot_level = 0;
1373
1374 ret = kv_copy_bytes_to_smc(rdev,
1375 pi->dpm_table_start +
1376 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1377 (uint8_t *)&pi->uvd_boot_level,
1378 sizeof(u8), pi->sram_end);
1379 if (ret)
1380 return ret;
1381
1382 if (!pi->caps_uvd_dpm ||
1383 pi->caps_stable_p_state)
1384 kv_send_msg_to_smc_with_parameter(rdev,
1385 PPSMC_MSG_UVDDPM_SetEnabledMask,
1386 (1 << pi->uvd_boot_level));
1387 }
1388
1389 return kv_enable_uvd_dpm(rdev, !gate);
1390 }
1391
1392 #if 0
1393 static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
1394 {
1395 u8 i;
1396 struct radeon_vce_clock_voltage_dependency_table *table =
1397 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1398
1399 for (i = 0; i < table->count; i++) {
1400 if (table->entries[i].evclk >= 0) /* XXX */
1401 break;
1402 }
1403
1404 return i;
1405 }
1406
1407 static int kv_update_vce_dpm(struct radeon_device *rdev,
1408 struct radeon_ps *radeon_new_state,
1409 struct radeon_ps *radeon_current_state)
1410 {
1411 struct kv_power_info *pi = kv_get_pi(rdev);
1412 struct radeon_vce_clock_voltage_dependency_table *table =
1413 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1414 int ret;
1415
1416 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) {
1417 if (pi->caps_stable_p_state)
1418 pi->vce_boot_level = table->count - 1;
1419 else
1420 pi->vce_boot_level = kv_get_vce_boot_level(rdev);
1421
1422 ret = kv_copy_bytes_to_smc(rdev,
1423 pi->dpm_table_start +
1424 offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1425 (u8 *)&pi->vce_boot_level,
1426 sizeof(u8),
1427 pi->sram_end);
1428 if (ret)
1429 return ret;
1430
1431 if (pi->caps_stable_p_state)
1432 kv_send_msg_to_smc_with_parameter(rdev,
1433 PPSMC_MSG_VCEDPM_SetEnabledMask,
1434 (1 << pi->vce_boot_level));
1435
1436 kv_enable_vce_dpm(rdev, true);
1437 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) {
1438 kv_enable_vce_dpm(rdev, false);
1439 }
1440
1441 return 0;
1442 }
1443 #endif
1444
1445 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1446 {
1447 struct kv_power_info *pi = kv_get_pi(rdev);
1448 struct radeon_clock_voltage_dependency_table *table =
1449 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1450 int ret;
1451
1452 if (!gate) {
1453 if (pi->caps_stable_p_state)
1454 pi->samu_boot_level = table->count - 1;
1455 else
1456 pi->samu_boot_level = 0;
1457
1458 ret = kv_copy_bytes_to_smc(rdev,
1459 pi->dpm_table_start +
1460 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1461 (u8 *)&pi->samu_boot_level,
1462 sizeof(u8),
1463 pi->sram_end);
1464 if (ret)
1465 return ret;
1466
1467 if (pi->caps_stable_p_state)
1468 kv_send_msg_to_smc_with_parameter(rdev,
1469 PPSMC_MSG_SAMUDPM_SetEnabledMask,
1470 (1 << pi->samu_boot_level));
1471 }
1472
1473 return kv_enable_samu_dpm(rdev, !gate);
1474 }
1475
1476 static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
1477 {
1478 u8 i;
1479 struct radeon_clock_voltage_dependency_table *table =
1480 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1481
1482 for (i = 0; i < table->count; i++) {
1483 if (table->entries[i].clk >= 0) /* XXX */
1484 break;
1485 }
1486
1487 if (i >= table->count)
1488 i = table->count - 1;
1489
1490 return i;
1491 }
1492
1493 static void kv_update_acp_boot_level(struct radeon_device *rdev)
1494 {
1495 struct kv_power_info *pi = kv_get_pi(rdev);
1496 u8 acp_boot_level;
1497
1498 if (!pi->caps_stable_p_state) {
1499 acp_boot_level = kv_get_acp_boot_level(rdev);
1500 if (acp_boot_level != pi->acp_boot_level) {
1501 pi->acp_boot_level = acp_boot_level;
1502 kv_send_msg_to_smc_with_parameter(rdev,
1503 PPSMC_MSG_ACPDPM_SetEnabledMask,
1504 (1 << pi->acp_boot_level));
1505 }
1506 }
1507 }
1508
1509 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1510 {
1511 struct kv_power_info *pi = kv_get_pi(rdev);
1512 struct radeon_clock_voltage_dependency_table *table =
1513 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1514 int ret;
1515
1516 if (!gate) {
1517 if (pi->caps_stable_p_state)
1518 pi->acp_boot_level = table->count - 1;
1519 else
1520 pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1521
1522 ret = kv_copy_bytes_to_smc(rdev,
1523 pi->dpm_table_start +
1524 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1525 (u8 *)&pi->acp_boot_level,
1526 sizeof(u8),
1527 pi->sram_end);
1528 if (ret)
1529 return ret;
1530
1531 if (pi->caps_stable_p_state)
1532 kv_send_msg_to_smc_with_parameter(rdev,
1533 PPSMC_MSG_ACPDPM_SetEnabledMask,
1534 (1 << pi->acp_boot_level));
1535 }
1536
1537 return kv_enable_acp_dpm(rdev, !gate);
1538 }
1539
1540 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
1541 {
1542 struct kv_power_info *pi = kv_get_pi(rdev);
1543
1544 if (pi->uvd_power_gated == gate)
1545 return;
1546
1547 pi->uvd_power_gated = gate;
1548
1549 if (gate) {
1550 if (pi->caps_uvd_pg) {
1551 uvd_v1_0_stop(rdev);
1552 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
1553 }
1554 kv_update_uvd_dpm(rdev, gate);
1555 if (pi->caps_uvd_pg)
1556 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1557 } else {
1558 if (pi->caps_uvd_pg) {
1559 kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
1560 uvd_v4_2_resume(rdev);
1561 uvd_v1_0_start(rdev);
1562 cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
1563 }
1564 kv_update_uvd_dpm(rdev, gate);
1565 }
1566 }
1567
1568 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1569 {
1570 struct kv_power_info *pi = kv_get_pi(rdev);
1571
1572 if (pi->vce_power_gated == gate)
1573 return;
1574
1575 pi->vce_power_gated = gate;
1576
1577 if (gate) {
1578 if (pi->caps_vce_pg)
1579 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1580 } else {
1581 if (pi->caps_vce_pg)
1582 kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1583 }
1584 }
1585
1586 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1587 {
1588 struct kv_power_info *pi = kv_get_pi(rdev);
1589
1590 if (pi->samu_power_gated == gate)
1591 return;
1592
1593 pi->samu_power_gated = gate;
1594
1595 if (gate) {
1596 kv_update_samu_dpm(rdev, true);
1597 if (pi->caps_samu_pg)
1598 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1599 } else {
1600 if (pi->caps_samu_pg)
1601 kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1602 kv_update_samu_dpm(rdev, false);
1603 }
1604 }
1605
1606 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1607 {
1608 struct kv_power_info *pi = kv_get_pi(rdev);
1609
1610 if (pi->acp_power_gated == gate)
1611 return;
1612
1613 if (rdev->family == CHIP_KABINI)
1614 return;
1615
1616 pi->acp_power_gated = gate;
1617
1618 if (gate) {
1619 kv_update_acp_dpm(rdev, true);
1620 if (pi->caps_acp_pg)
1621 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1622 } else {
1623 if (pi->caps_acp_pg)
1624 kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1625 kv_update_acp_dpm(rdev, false);
1626 }
1627 }
1628
1629 static void kv_set_valid_clock_range(struct radeon_device *rdev,
1630 struct radeon_ps *new_rps)
1631 {
1632 struct kv_ps *new_ps = kv_get_ps(new_rps);
1633 struct kv_power_info *pi = kv_get_pi(rdev);
1634 u32 i;
1635 struct radeon_clock_voltage_dependency_table *table =
1636 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1637
1638 if (table && table->count) {
1639 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1640 if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1641 (i == (pi->graphics_dpm_level_count - 1))) {
1642 pi->lowest_valid = i;
1643 break;
1644 }
1645 }
1646
1647 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1648 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1649 break;
1650 }
1651 pi->highest_valid = i;
1652
1653 if (pi->lowest_valid > pi->highest_valid) {
1654 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1655 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1656 pi->highest_valid = pi->lowest_valid;
1657 else
1658 pi->lowest_valid = pi->highest_valid;
1659 }
1660 } else {
1661 struct sumo_sclk_voltage_mapping_table *table =
1662 &pi->sys_info.sclk_voltage_mapping_table;
1663
1664 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1665 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1666 i == (int)(pi->graphics_dpm_level_count - 1)) {
1667 pi->lowest_valid = i;
1668 break;
1669 }
1670 }
1671
1672 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1673 if (table->entries[i].sclk_frequency <=
1674 new_ps->levels[new_ps->num_levels - 1].sclk)
1675 break;
1676 }
1677 pi->highest_valid = i;
1678
1679 if (pi->lowest_valid > pi->highest_valid) {
1680 if ((new_ps->levels[0].sclk -
1681 table->entries[pi->highest_valid].sclk_frequency) >
1682 (table->entries[pi->lowest_valid].sclk_frequency -
1683 new_ps->levels[new_ps->num_levels -1].sclk))
1684 pi->highest_valid = pi->lowest_valid;
1685 else
1686 pi->lowest_valid = pi->highest_valid;
1687 }
1688 }
1689 }
1690
1691 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1692 struct radeon_ps *new_rps)
1693 {
1694 struct kv_ps *new_ps = kv_get_ps(new_rps);
1695 struct kv_power_info *pi = kv_get_pi(rdev);
1696 int ret = 0;
1697 u8 clk_bypass_cntl;
1698
1699 if (pi->caps_enable_dfs_bypass) {
1700 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1701 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1702 ret = kv_copy_bytes_to_smc(rdev,
1703 (pi->dpm_table_start +
1704 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1705 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1706 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1707 &clk_bypass_cntl,
1708 sizeof(u8), pi->sram_end);
1709 }
1710
1711 return ret;
1712 }
1713
1714 static int kv_enable_nb_dpm(struct radeon_device *rdev)
1715 {
1716 struct kv_power_info *pi = kv_get_pi(rdev);
1717 int ret = 0;
1718
1719 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1720 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1721 if (ret == 0)
1722 pi->nb_dpm_enabled = true;
1723 }
1724
1725 return ret;
1726 }
1727
1728 int kv_dpm_force_performance_level(struct radeon_device *rdev,
1729 enum radeon_dpm_forced_level level)
1730 {
1731 int ret;
1732
1733 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1734 ret = kv_force_dpm_highest(rdev);
1735 if (ret)
1736 return ret;
1737 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1738 ret = kv_force_dpm_lowest(rdev);
1739 if (ret)
1740 return ret;
1741 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1742 ret = kv_unforce_levels(rdev);
1743 if (ret)
1744 return ret;
1745 }
1746
1747 rdev->pm.dpm.forced_level = level;
1748
1749 return 0;
1750 }
1751
1752 int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1753 {
1754 struct kv_power_info *pi = kv_get_pi(rdev);
1755 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1756 struct radeon_ps *new_ps = &requested_ps;
1757
1758 kv_update_requested_ps(rdev, new_ps);
1759
1760 kv_apply_state_adjust_rules(rdev,
1761 &pi->requested_rps,
1762 &pi->current_rps);
1763
1764 return 0;
1765 }
1766
1767 int kv_dpm_set_power_state(struct radeon_device *rdev)
1768 {
1769 struct kv_power_info *pi = kv_get_pi(rdev);
1770 struct radeon_ps *new_ps = &pi->requested_rps;
1771 /*struct radeon_ps *old_ps = &pi->current_rps;*/
1772 int ret;
1773
1774 if (pi->bapm_enable) {
1775 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1776 if (ret) {
1777 DRM_ERROR("kv_smc_bapm_enable failed\n");
1778 return ret;
1779 }
1780 }
1781
1782 if (rdev->family == CHIP_KABINI) {
1783 if (pi->enable_dpm) {
1784 kv_set_valid_clock_range(rdev, new_ps);
1785 kv_update_dfs_bypass_settings(rdev, new_ps);
1786 ret = kv_calculate_ds_divider(rdev);
1787 if (ret) {
1788 DRM_ERROR("kv_calculate_ds_divider failed\n");
1789 return ret;
1790 }
1791 kv_calculate_nbps_level_settings(rdev);
1792 kv_calculate_dpm_settings(rdev);
1793 kv_force_lowest_valid(rdev);
1794 kv_enable_new_levels(rdev);
1795 kv_upload_dpm_settings(rdev);
1796 kv_program_nbps_index_settings(rdev, new_ps);
1797 kv_unforce_levels(rdev);
1798 kv_set_enabled_levels(rdev);
1799 kv_force_lowest_valid(rdev);
1800 kv_unforce_levels(rdev);
1801 #if 0
1802 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1803 if (ret) {
1804 DRM_ERROR("kv_update_vce_dpm failed\n");
1805 return ret;
1806 }
1807 #endif
1808 kv_update_sclk_t(rdev);
1809 }
1810 } else {
1811 if (pi->enable_dpm) {
1812 kv_set_valid_clock_range(rdev, new_ps);
1813 kv_update_dfs_bypass_settings(rdev, new_ps);
1814 ret = kv_calculate_ds_divider(rdev);
1815 if (ret) {
1816 DRM_ERROR("kv_calculate_ds_divider failed\n");
1817 return ret;
1818 }
1819 kv_calculate_nbps_level_settings(rdev);
1820 kv_calculate_dpm_settings(rdev);
1821 kv_freeze_sclk_dpm(rdev, true);
1822 kv_upload_dpm_settings(rdev);
1823 kv_program_nbps_index_settings(rdev, new_ps);
1824 kv_freeze_sclk_dpm(rdev, false);
1825 kv_set_enabled_levels(rdev);
1826 #if 0
1827 ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1828 if (ret) {
1829 DRM_ERROR("kv_update_vce_dpm failed\n");
1830 return ret;
1831 }
1832 #endif
1833 kv_update_acp_boot_level(rdev);
1834 kv_update_sclk_t(rdev);
1835 kv_enable_nb_dpm(rdev);
1836 }
1837 }
1838
1839 return 0;
1840 }
1841
1842 void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1843 {
1844 struct kv_power_info *pi = kv_get_pi(rdev);
1845 struct radeon_ps *new_ps = &pi->requested_rps;
1846
1847 kv_update_current_ps(rdev, new_ps);
1848 }
1849
1850 void kv_dpm_setup_asic(struct radeon_device *rdev)
1851 {
1852 sumo_take_smu_control(rdev, true);
1853 kv_init_powergate_state(rdev);
1854 kv_init_sclk_t(rdev);
1855 }
1856
1857 void kv_dpm_reset_asic(struct radeon_device *rdev)
1858 {
1859 struct kv_power_info *pi = kv_get_pi(rdev);
1860
1861 if (rdev->family == CHIP_KABINI) {
1862 kv_force_lowest_valid(rdev);
1863 kv_init_graphics_levels(rdev);
1864 kv_program_bootup_state(rdev);
1865 kv_upload_dpm_settings(rdev);
1866 kv_force_lowest_valid(rdev);
1867 kv_unforce_levels(rdev);
1868 } else {
1869 kv_init_graphics_levels(rdev);
1870 kv_program_bootup_state(rdev);
1871 kv_freeze_sclk_dpm(rdev, true);
1872 kv_upload_dpm_settings(rdev);
1873 kv_freeze_sclk_dpm(rdev, false);
1874 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1875 }
1876 }
1877
1878 //XXX use sumo_dpm_display_configuration_changed
1879
1880 static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1881 struct radeon_clock_and_voltage_limits *table)
1882 {
1883 struct kv_power_info *pi = kv_get_pi(rdev);
1884
1885 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
1886 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
1887 table->sclk =
1888 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
1889 table->vddc =
1890 kv_convert_2bit_index_to_voltage(rdev,
1891 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
1892 }
1893
1894 table->mclk = pi->sys_info.nbp_memory_clock[0];
1895 }
1896
1897 static void kv_patch_voltage_values(struct radeon_device *rdev)
1898 {
1899 int i;
1900 struct radeon_uvd_clock_voltage_dependency_table *table =
1901 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1902
1903 if (table->count) {
1904 for (i = 0; i < table->count; i++)
1905 table->entries[i].v =
1906 kv_convert_8bit_index_to_voltage(rdev,
1907 table->entries[i].v);
1908 }
1909
1910 }
1911
1912 static void kv_construct_boot_state(struct radeon_device *rdev)
1913 {
1914 struct kv_power_info *pi = kv_get_pi(rdev);
1915
1916 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1917 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1918 pi->boot_pl.ds_divider_index = 0;
1919 pi->boot_pl.ss_divider_index = 0;
1920 pi->boot_pl.allow_gnb_slow = 1;
1921 pi->boot_pl.force_nbp_state = 0;
1922 pi->boot_pl.display_wm = 0;
1923 pi->boot_pl.vce_wm = 0;
1924 }
1925
1926 static int kv_force_dpm_highest(struct radeon_device *rdev)
1927 {
1928 int ret;
1929 u32 enable_mask, i;
1930
1931 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1932 if (ret)
1933 return ret;
1934
1935 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
1936 if (enable_mask & (1 << i))
1937 break;
1938 }
1939
1940 if (rdev->family == CHIP_KABINI)
1941 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1942 else
1943 return kv_set_enabled_level(rdev, i);
1944 }
1945
1946 static int kv_force_dpm_lowest(struct radeon_device *rdev)
1947 {
1948 int ret;
1949 u32 enable_mask, i;
1950
1951 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1952 if (ret)
1953 return ret;
1954
1955 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
1956 if (enable_mask & (1 << i))
1957 break;
1958 }
1959
1960 if (rdev->family == CHIP_KABINI)
1961 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1962 else
1963 return kv_set_enabled_level(rdev, i);
1964 }
1965
1966 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1967 u32 sclk, u32 min_sclk_in_sr)
1968 {
1969 struct kv_power_info *pi = kv_get_pi(rdev);
1970 u32 i;
1971 u32 temp;
1972 u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?
1973 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK;
1974
1975 if (sclk < min)
1976 return 0;
1977
1978 if (!pi->caps_sclk_ds)
1979 return 0;
1980
1981 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
1982 temp = sclk / sumo_get_sleep_divider_from_id(i);
1983 if (temp >= min)
1984 break;
1985 }
1986
1987 return (u8)i;
1988 }
1989
1990 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
1991 {
1992 struct kv_power_info *pi = kv_get_pi(rdev);
1993 struct radeon_clock_voltage_dependency_table *table =
1994 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1995 int i;
1996
1997 if (table && table->count) {
1998 for (i = table->count - 1; i >= 0; i--) {
1999 if (pi->high_voltage_t &&
2000 (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
2001 pi->high_voltage_t)) {
2002 *limit = i;
2003 return 0;
2004 }
2005 }
2006 } else {
2007 struct sumo_sclk_voltage_mapping_table *table =
2008 &pi->sys_info.sclk_voltage_mapping_table;
2009
2010 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2011 if (pi->high_voltage_t &&
2012 (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
2013 pi->high_voltage_t)) {
2014 *limit = i;
2015 return 0;
2016 }
2017 }
2018 }
2019
2020 *limit = 0;
2021 return 0;
2022 }
2023
2024 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
2025 struct radeon_ps *new_rps,
2026 struct radeon_ps *old_rps)
2027 {
2028 struct kv_ps *ps = kv_get_ps(new_rps);
2029 struct kv_power_info *pi = kv_get_pi(rdev);
2030 u32 min_sclk = 10000; /* ??? */
2031 u32 sclk, mclk = 0;
2032 int i, limit;
2033 bool force_high;
2034 struct radeon_clock_voltage_dependency_table *table =
2035 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2036 u32 stable_p_state_sclk = 0;
2037 struct radeon_clock_and_voltage_limits *max_limits =
2038 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2039
2040 mclk = max_limits->mclk;
2041 sclk = min_sclk;
2042
2043 if (pi->caps_stable_p_state) {
2044 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2045
2046 for (i = table->count - 1; i >= 0; i++) {
2047 if (stable_p_state_sclk >= table->entries[i].clk) {
2048 stable_p_state_sclk = table->entries[i].clk;
2049 break;
2050 }
2051 }
2052
2053 if (i > 0)
2054 stable_p_state_sclk = table->entries[0].clk;
2055
2056 sclk = stable_p_state_sclk;
2057 }
2058
2059 ps->need_dfs_bypass = true;
2060
2061 for (i = 0; i < ps->num_levels; i++) {
2062 if (ps->levels[i].sclk < sclk)
2063 ps->levels[i].sclk = sclk;
2064 }
2065
2066 if (table && table->count) {
2067 for (i = 0; i < ps->num_levels; i++) {
2068 if (pi->high_voltage_t &&
2069 (pi->high_voltage_t <
2070 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2071 kv_get_high_voltage_limit(rdev, &limit);
2072 ps->levels[i].sclk = table->entries[limit].clk;
2073 }
2074 }
2075 } else {
2076 struct sumo_sclk_voltage_mapping_table *table =
2077 &pi->sys_info.sclk_voltage_mapping_table;
2078
2079 for (i = 0; i < ps->num_levels; i++) {
2080 if (pi->high_voltage_t &&
2081 (pi->high_voltage_t <
2082 kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2083 kv_get_high_voltage_limit(rdev, &limit);
2084 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2085 }
2086 }
2087 }
2088
2089 if (pi->caps_stable_p_state) {
2090 for (i = 0; i < ps->num_levels; i++) {
2091 ps->levels[i].sclk = stable_p_state_sclk;
2092 }
2093 }
2094
2095 pi->video_start = new_rps->dclk || new_rps->vclk;
2096
2097 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2098 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2099 pi->battery_state = true;
2100 else
2101 pi->battery_state = false;
2102
2103 if (rdev->family == CHIP_KABINI) {
2104 ps->dpm0_pg_nb_ps_lo = 0x1;
2105 ps->dpm0_pg_nb_ps_hi = 0x0;
2106 ps->dpmx_nb_ps_lo = 0x1;
2107 ps->dpmx_nb_ps_hi = 0x0;
2108 } else {
2109 ps->dpm0_pg_nb_ps_lo = 0x3;
2110 ps->dpm0_pg_nb_ps_hi = 0x0;
2111 ps->dpmx_nb_ps_lo = 0x3;
2112 ps->dpmx_nb_ps_hi = 0x0;
2113
2114 if (pi->sys_info.nb_dpm_enable) {
2115 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2116 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2117 pi->disable_nb_ps3_in_battery;
2118 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2119 ps->dpm0_pg_nb_ps_hi = 0x2;
2120 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2121 ps->dpmx_nb_ps_hi = 0x2;
2122 }
2123 }
2124 }
2125
2126 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2127 u32 index, bool enable)
2128 {
2129 struct kv_power_info *pi = kv_get_pi(rdev);
2130
2131 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2132 }
2133
2134 static int kv_calculate_ds_divider(struct radeon_device *rdev)
2135 {
2136 struct kv_power_info *pi = kv_get_pi(rdev);
2137 u32 sclk_in_sr = 10000; /* ??? */
2138 u32 i;
2139
2140 if (pi->lowest_valid > pi->highest_valid)
2141 return -EINVAL;
2142
2143 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2144 pi->graphics_level[i].DeepSleepDivId =
2145 kv_get_sleep_divider_id_from_clock(rdev,
2146 be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2147 sclk_in_sr);
2148 }
2149 return 0;
2150 }
2151
2152 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2153 {
2154 struct kv_power_info *pi = kv_get_pi(rdev);
2155 u32 i;
2156 bool force_high;
2157 struct radeon_clock_and_voltage_limits *max_limits =
2158 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2159 u32 mclk = max_limits->mclk;
2160
2161 if (pi->lowest_valid > pi->highest_valid)
2162 return -EINVAL;
2163
2164 if (rdev->family == CHIP_KABINI) {
2165 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2166 pi->graphics_level[i].GnbSlow = 1;
2167 pi->graphics_level[i].ForceNbPs1 = 0;
2168 pi->graphics_level[i].UpH = 0;
2169 }
2170
2171 if (!pi->sys_info.nb_dpm_enable)
2172 return 0;
2173
2174 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2175 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2176
2177 if (force_high) {
2178 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2179 pi->graphics_level[i].GnbSlow = 0;
2180 } else {
2181 if (pi->battery_state)
2182 pi->graphics_level[0].ForceNbPs1 = 1;
2183
2184 pi->graphics_level[1].GnbSlow = 0;
2185 pi->graphics_level[2].GnbSlow = 0;
2186 pi->graphics_level[3].GnbSlow = 0;
2187 pi->graphics_level[4].GnbSlow = 0;
2188 }
2189 } else {
2190 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2191 pi->graphics_level[i].GnbSlow = 1;
2192 pi->graphics_level[i].ForceNbPs1 = 0;
2193 pi->graphics_level[i].UpH = 0;
2194 }
2195
2196 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2197 pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2198 pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2199 if (pi->lowest_valid != pi->highest_valid)
2200 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2201 }
2202 }
2203 return 0;
2204 }
2205
2206 static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2207 {
2208 struct kv_power_info *pi = kv_get_pi(rdev);
2209 u32 i;
2210
2211 if (pi->lowest_valid > pi->highest_valid)
2212 return -EINVAL;
2213
2214 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2215 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2216
2217 return 0;
2218 }
2219
2220 static void kv_init_graphics_levels(struct radeon_device *rdev)
2221 {
2222 struct kv_power_info *pi = kv_get_pi(rdev);
2223 u32 i;
2224 struct radeon_clock_voltage_dependency_table *table =
2225 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2226
2227 if (table && table->count) {
2228 u32 vid_2bit;
2229
2230 pi->graphics_dpm_level_count = 0;
2231 for (i = 0; i < table->count; i++) {
2232 if (pi->high_voltage_t &&
2233 (pi->high_voltage_t <
2234 kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2235 break;
2236
2237 kv_set_divider_value(rdev, i, table->entries[i].clk);
2238 vid_2bit = sumo_convert_vid7_to_vid2(rdev,
2239 &pi->sys_info.vid_mapping_table,
2240 table->entries[i].v);
2241 kv_set_vid(rdev, i, vid_2bit);
2242 kv_set_at(rdev, i, pi->at[i]);
2243 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2244 pi->graphics_dpm_level_count++;
2245 }
2246 } else {
2247 struct sumo_sclk_voltage_mapping_table *table =
2248 &pi->sys_info.sclk_voltage_mapping_table;
2249
2250 pi->graphics_dpm_level_count = 0;
2251 for (i = 0; i < table->num_max_dpm_entries; i++) {
2252 if (pi->high_voltage_t &&
2253 pi->high_voltage_t <
2254 kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2255 break;
2256
2257 kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2258 kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2259 kv_set_at(rdev, i, pi->at[i]);
2260 kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2261 pi->graphics_dpm_level_count++;
2262 }
2263 }
2264
2265 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2266 kv_dpm_power_level_enable(rdev, i, false);
2267 }
2268
2269 static void kv_enable_new_levels(struct radeon_device *rdev)
2270 {
2271 struct kv_power_info *pi = kv_get_pi(rdev);
2272 u32 i;
2273
2274 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2275 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2276 kv_dpm_power_level_enable(rdev, i, true);
2277 }
2278 }
2279
2280 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
2281 {
2282 u32 new_mask = (1 << level);
2283
2284 return kv_send_msg_to_smc_with_parameter(rdev,
2285 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2286 new_mask);
2287 }
2288
2289 static int kv_set_enabled_levels(struct radeon_device *rdev)
2290 {
2291 struct kv_power_info *pi = kv_get_pi(rdev);
2292 u32 i, new_mask = 0;
2293
2294 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2295 new_mask |= (1 << i);
2296
2297 return kv_send_msg_to_smc_with_parameter(rdev,
2298 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2299 new_mask);
2300 }
2301
2302 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2303 struct radeon_ps *new_rps)
2304 {
2305 struct kv_ps *new_ps = kv_get_ps(new_rps);
2306 struct kv_power_info *pi = kv_get_pi(rdev);
2307 u32 nbdpmconfig1;
2308
2309 if (rdev->family == CHIP_KABINI)
2310 return;
2311
2312 if (pi->sys_info.nb_dpm_enable) {
2313 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);
2314 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK |
2315 DpmXNbPsLo_MASK | DpmXNbPsHi_MASK);
2316 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) |
2317 Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) |
2318 DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) |
2319 DpmXNbPsHi(new_ps->dpmx_nb_ps_hi));
2320 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1);
2321 }
2322 }
2323
2324 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2325 int min_temp, int max_temp)
2326 {
2327 int low_temp = 0 * 1000;
2328 int high_temp = 255 * 1000;
2329 u32 tmp;
2330
2331 if (low_temp < min_temp)
2332 low_temp = min_temp;
2333 if (high_temp > max_temp)
2334 high_temp = max_temp;
2335 if (high_temp < low_temp) {
2336 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2337 return -EINVAL;
2338 }
2339
2340 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
2341 tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK);
2342 tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) |
2343 DIG_THERM_INTL(49 + (low_temp / 1000)));
2344 WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
2345
2346 rdev->pm.dpm.thermal.min_temp = low_temp;
2347 rdev->pm.dpm.thermal.max_temp = high_temp;
2348
2349 return 0;
2350 }
2351
2352 union igp_info {
2353 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2354 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2355 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2356 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2357 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2358 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2359 };
2360
2361 static int kv_parse_sys_info_table(struct radeon_device *rdev)
2362 {
2363 struct kv_power_info *pi = kv_get_pi(rdev);
2364 struct radeon_mode_info *mode_info = &rdev->mode_info;
2365 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2366 union igp_info *igp_info;
2367 u8 frev, crev;
2368 u16 data_offset;
2369 int i;
2370
2371 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2372 &frev, &crev, &data_offset)) {
2373 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2374 data_offset);
2375
2376 if (crev != 8) {
2377 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2378 return -EINVAL;
2379 }
2380 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2381 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2382 pi->sys_info.bootup_nb_voltage_index =
2383 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2384 if (igp_info->info_8.ucHtcTmpLmt == 0)
2385 pi->sys_info.htc_tmp_lmt = 203;
2386 else
2387 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2388 if (igp_info->info_8.ucHtcHystLmt == 0)
2389 pi->sys_info.htc_hyst_lmt = 5;
2390 else
2391 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2392 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2393 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2394 }
2395
2396 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2397 pi->sys_info.nb_dpm_enable = true;
2398 else
2399 pi->sys_info.nb_dpm_enable = false;
2400
2401 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2402 pi->sys_info.nbp_memory_clock[i] =
2403 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2404 pi->sys_info.nbp_n_clock[i] =
2405 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2406 }
2407 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2408 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2409 pi->caps_enable_dfs_bypass = true;
2410
2411 sumo_construct_sclk_voltage_mapping_table(rdev,
2412 &pi->sys_info.sclk_voltage_mapping_table,
2413 igp_info->info_8.sAvail_SCLK);
2414
2415 sumo_construct_vid_mapping_table(rdev,
2416 &pi->sys_info.vid_mapping_table,
2417 igp_info->info_8.sAvail_SCLK);
2418
2419 kv_construct_max_power_limits_table(rdev,
2420 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2421 }
2422 return 0;
2423 }
2424
2425 union power_info {
2426 struct _ATOM_POWERPLAY_INFO info;
2427 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2428 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2429 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2430 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2431 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2432 };
2433
2434 union pplib_clock_info {
2435 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2436 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2437 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2438 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2439 };
2440
2441 union pplib_power_state {
2442 struct _ATOM_PPLIB_STATE v1;
2443 struct _ATOM_PPLIB_STATE_V2 v2;
2444 };
2445
2446 static void kv_patch_boot_state(struct radeon_device *rdev,
2447 struct kv_ps *ps)
2448 {
2449 struct kv_power_info *pi = kv_get_pi(rdev);
2450
2451 ps->num_levels = 1;
2452 ps->levels[0] = pi->boot_pl;
2453 }
2454
2455 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2456 struct radeon_ps *rps,
2457 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2458 u8 table_rev)
2459 {
2460 struct kv_ps *ps = kv_get_ps(rps);
2461
2462 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2463 rps->class = le16_to_cpu(non_clock_info->usClassification);
2464 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2465
2466 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2467 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2468 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2469 } else {
2470 rps->vclk = 0;
2471 rps->dclk = 0;
2472 }
2473
2474 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2475 rdev->pm.dpm.boot_ps = rps;
2476 kv_patch_boot_state(rdev, ps);
2477 }
2478 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2479 rdev->pm.dpm.uvd_ps = rps;
2480 }
2481
2482 static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2483 struct radeon_ps *rps, int index,
2484 union pplib_clock_info *clock_info)
2485 {
2486 struct kv_power_info *pi = kv_get_pi(rdev);
2487 struct kv_ps *ps = kv_get_ps(rps);
2488 struct kv_pl *pl = &ps->levels[index];
2489 u32 sclk;
2490
2491 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2492 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2493 pl->sclk = sclk;
2494 pl->vddc_index = clock_info->sumo.vddcIndex;
2495
2496 ps->num_levels = index + 1;
2497
2498 if (pi->caps_sclk_ds) {
2499 pl->ds_divider_index = 5;
2500 pl->ss_divider_index = 5;
2501 }
2502 }
2503
2504 static int kv_parse_power_table(struct radeon_device *rdev)
2505 {
2506 struct radeon_mode_info *mode_info = &rdev->mode_info;
2507 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2508 union pplib_power_state *power_state;
2509 int i, j, k, non_clock_array_index, clock_array_index;
2510 union pplib_clock_info *clock_info;
2511 struct _StateArray *state_array;
2512 struct _ClockInfoArray *clock_info_array;
2513 struct _NonClockInfoArray *non_clock_info_array;
2514 union power_info *power_info;
2515 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2516 u16 data_offset;
2517 u8 frev, crev;
2518 u8 *power_state_offset;
2519 struct kv_ps *ps;
2520
2521 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2522 &frev, &crev, &data_offset))
2523 return -EINVAL;
2524 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2525
2526 state_array = (struct _StateArray *)
2527 (mode_info->atom_context->bios + data_offset +
2528 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2529 clock_info_array = (struct _ClockInfoArray *)
2530 (mode_info->atom_context->bios + data_offset +
2531 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2532 non_clock_info_array = (struct _NonClockInfoArray *)
2533 (mode_info->atom_context->bios + data_offset +
2534 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2535
2536 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
2537 state_array->ucNumEntries, GFP_KERNEL);
2538 if (!rdev->pm.dpm.ps)
2539 return -ENOMEM;
2540 power_state_offset = (u8 *)state_array->states;
2541 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
2542 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
2543 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
2544 for (i = 0; i < state_array->ucNumEntries; i++) {
2545 u8 *idx;
2546 power_state = (union pplib_power_state *)power_state_offset;
2547 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2548 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2549 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2550 if (!rdev->pm.power_state[i].clock_info)
2551 return -EINVAL;
2552 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2553 if (ps == NULL) {
2554 kfree(rdev->pm.dpm.ps);
2555 return -ENOMEM;
2556 }
2557 rdev->pm.dpm.ps[i].ps_priv = ps;
2558 k = 0;
2559 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2560 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2561 clock_array_index = idx[j];
2562 if (clock_array_index >= clock_info_array->ucNumEntries)
2563 continue;
2564 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2565 break;
2566 clock_info = (union pplib_clock_info *)
2567 ((u8 *)&clock_info_array->clockInfo[0] +
2568 (clock_array_index * clock_info_array->ucEntrySize));
2569 kv_parse_pplib_clock_info(rdev,
2570 &rdev->pm.dpm.ps[i], k,
2571 clock_info);
2572 k++;
2573 }
2574 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2575 non_clock_info,
2576 non_clock_info_array->ucEntrySize);
2577 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2578 }
2579 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2580 return 0;
2581 }
2582
2583 int kv_dpm_init(struct radeon_device *rdev)
2584 {
2585 struct kv_power_info *pi;
2586 int ret, i;
2587
2588 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2589 if (pi == NULL)
2590 return -ENOMEM;
2591 rdev->pm.dpm.priv = pi;
2592
2593 ret = r600_parse_extended_power_table(rdev);
2594 if (ret)
2595 return ret;
2596
2597 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2598 pi->at[i] = TRINITY_AT_DFLT;
2599
2600 pi->sram_end = SMC_RAM_END;
2601
2602 if (rdev->family == CHIP_KABINI)
2603 pi->high_voltage_t = 4001;
2604
2605 pi->enable_nb_dpm = true;
2606
2607 pi->caps_power_containment = true;
2608 pi->caps_cac = true;
2609 pi->enable_didt = false;
2610 if (pi->enable_didt) {
2611 pi->caps_sq_ramping = true;
2612 pi->caps_db_ramping = true;
2613 pi->caps_td_ramping = true;
2614 pi->caps_tcp_ramping = true;
2615 }
2616
2617 pi->caps_sclk_ds = true;
2618 pi->enable_auto_thermal_throttling = true;
2619 pi->disable_nb_ps3_in_battery = false;
2620 pi->bapm_enable = false;
2621 pi->voltage_drop_t = 0;
2622 pi->caps_sclk_throttle_low_notification = false;
2623 pi->caps_fps = false; /* true? */
2624 pi->caps_uvd_pg = true;
2625 pi->caps_uvd_dpm = true;
2626 pi->caps_vce_pg = false;
2627 pi->caps_samu_pg = false;
2628 pi->caps_acp_pg = false;
2629 pi->caps_stable_p_state = false;
2630
2631 ret = kv_parse_sys_info_table(rdev);
2632 if (ret)
2633 return ret;
2634
2635 kv_patch_voltage_values(rdev);
2636 kv_construct_boot_state(rdev);
2637
2638 ret = kv_parse_power_table(rdev);
2639 if (ret)
2640 return ret;
2641
2642 pi->enable_dpm = true;
2643
2644 return 0;
2645 }
2646
2647 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2648 struct seq_file *m)
2649 {
2650 struct kv_power_info *pi = kv_get_pi(rdev);
2651 u32 current_index =
2652 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
2653 CURR_SCLK_INDEX_SHIFT;
2654 u32 sclk, tmp;
2655 u16 vddc;
2656
2657 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2658 seq_printf(m, "invalid dpm profile %d\n", current_index);
2659 } else {
2660 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2661 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2662 SMU_VOLTAGE_CURRENT_LEVEL_SHIFT;
2663 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2664 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
2665 current_index, sclk, vddc);
2666 }
2667 }
2668
2669 void kv_dpm_print_power_state(struct radeon_device *rdev,
2670 struct radeon_ps *rps)
2671 {
2672 int i;
2673 struct kv_ps *ps = kv_get_ps(rps);
2674
2675 r600_dpm_print_class_info(rps->class, rps->class2);
2676 r600_dpm_print_cap_info(rps->caps);
2677 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2678 for (i = 0; i < ps->num_levels; i++) {
2679 struct kv_pl *pl = &ps->levels[i];
2680 printk("\t\tpower level %d sclk: %u vddc: %u\n",
2681 i, pl->sclk,
2682 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2683 }
2684 r600_dpm_print_ps_status(rdev, rps);
2685 }
2686
2687 void kv_dpm_fini(struct radeon_device *rdev)
2688 {
2689 int i;
2690
2691 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2692 kfree(rdev->pm.dpm.ps[i].ps_priv);
2693 }
2694 kfree(rdev->pm.dpm.ps);
2695 kfree(rdev->pm.dpm.priv);
2696 r600_free_extended_power_table(rdev);
2697 }
2698
2699 void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2700 {
2701
2702 }
2703
2704 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2705 {
2706 struct kv_power_info *pi = kv_get_pi(rdev);
2707 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2708
2709 if (low)
2710 return requested_state->levels[0].sclk;
2711 else
2712 return requested_state->levels[requested_state->num_levels - 1].sclk;
2713 }
2714
2715 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2716 {
2717 struct kv_power_info *pi = kv_get_pi(rdev);
2718
2719 return pi->sys_info.bootup_uma_clk;
2720 }
2721
Linux with added FPC-III support