| blob | d996033c243ee14f4509220a707edf50f9dbe489 |
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #ifndef NI_H
25 #define NI_H
27 #define CAYMAN_MAX_SH_GPRS 256
28 #define CAYMAN_MAX_TEMP_GPRS 16
29 #define CAYMAN_MAX_SH_THREADS 256
30 #define CAYMAN_MAX_SH_STACK_ENTRIES 4096
31 #define CAYMAN_MAX_FRC_EOV_CNT 16384
32 #define CAYMAN_MAX_BACKENDS 8
33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
35 #define CAYMAN_MAX_SIMDS 16
36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
38 #define CAYMAN_MAX_PIPES 8
39 #define CAYMAN_MAX_PIPES_MASK 0xFF
40 #define CAYMAN_MAX_LDS_NUM 0xFFFF
41 #define CAYMAN_MAX_TCC 16
42 #define CAYMAN_MAX_TCC_MASK 0xFF
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
47 #define DMIF_ADDR_CONFIG 0xBD4
49 /* DCE6 only */
50 #define DMIF_ADDR_CALC 0xC00
52 #define SRBM_GFX_CNTL 0x0E44
53 #define RINGID(x) (((x) & 0x3) << 0)
54 #define VMID(x) (((x) & 0x7) << 0)
55 #define SRBM_STATUS 0x0E50
56 #define RLC_RQ_PENDING (1 << 3)
57 #define GRBM_RQ_PENDING (1 << 5)
58 #define VMC_BUSY (1 << 8)
59 #define MCB_BUSY (1 << 9)
60 #define MCB_NON_DISPLAY_BUSY (1 << 10)
61 #define MCC_BUSY (1 << 11)
62 #define MCD_BUSY (1 << 12)
63 #define SEM_BUSY (1 << 14)
64 #define RLC_BUSY (1 << 15)
65 #define IH_BUSY (1 << 17)
67 #define SRBM_SOFT_RESET 0x0E60
68 #define SOFT_RESET_BIF (1 << 1)
69 #define SOFT_RESET_CG (1 << 2)
70 #define SOFT_RESET_DC (1 << 5)
71 #define SOFT_RESET_DMA1 (1 << 6)
72 #define SOFT_RESET_GRBM (1 << 8)
73 #define SOFT_RESET_HDP (1 << 9)
74 #define SOFT_RESET_IH (1 << 10)
75 #define SOFT_RESET_MC (1 << 11)
76 #define SOFT_RESET_RLC (1 << 13)
77 #define SOFT_RESET_ROM (1 << 14)
78 #define SOFT_RESET_SEM (1 << 15)
79 #define SOFT_RESET_VMC (1 << 17)
80 #define SOFT_RESET_DMA (1 << 20)
81 #define SOFT_RESET_TST (1 << 21)
82 #define SOFT_RESET_REGBB (1 << 22)
83 #define SOFT_RESET_ORB (1 << 23)
85 #define SRBM_STATUS2 0x0EC4
86 #define DMA_BUSY (1 << 5)
87 #define DMA1_BUSY (1 << 6)
89 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
90 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
91 #define RESPONSE_TYPE_MASK 0x000000F0
92 #define RESPONSE_TYPE_SHIFT 4
93 #define VM_L2_CNTL 0x1400
94 #define ENABLE_L2_CACHE (1 << 0)
95 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
96 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
97 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
98 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
99 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18)
100 /* CONTEXT1_IDENTITY_ACCESS_MODE
101 * 0 physical = logical
102 * 1 logical via context1 page table
103 * 2 inside identity aperture use translation, outside physical = logical
104 * 3 inside identity aperture physical = logical, outside use translation
105 */
106 #define VM_L2_CNTL2 0x1404
107 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
108 #define INVALIDATE_L2_CACHE (1 << 1)
109 #define VM_L2_CNTL3 0x1408
110 #define BANK_SELECT(x) ((x) << 0)
111 #define CACHE_UPDATE_MODE(x) ((x) << 6)
112 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
113 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
114 #define VM_L2_STATUS 0x140C
115 #define L2_BUSY (1 << 0)
116 #define VM_CONTEXT0_CNTL 0x1410
117 #define ENABLE_CONTEXT (1 << 0)
118 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
119 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
120 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
121 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
122 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
123 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
124 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
125 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
126 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
127 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
128 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
129 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
130 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
131 #define VM_CONTEXT1_CNTL 0x1414
132 #define VM_CONTEXT0_CNTL2 0x1430
133 #define VM_CONTEXT1_CNTL2 0x1434
134 #define VM_INVALIDATE_REQUEST 0x1478
135 #define VM_INVALIDATE_RESPONSE 0x147c
136 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
137 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
138 #define PROTECTIONS_MASK (0xf << 0)
139 #define PROTECTIONS_SHIFT 0
140 /* bit 0: range
141 * bit 2: pde0
142 * bit 3: valid
143 * bit 4: read
144 * bit 5: write
145 */
146 #define MEMORY_CLIENT_ID_MASK (0xff << 12)
147 #define MEMORY_CLIENT_ID_SHIFT 12
148 #define MEMORY_CLIENT_RW_MASK (1 << 24)
149 #define MEMORY_CLIENT_RW_SHIFT 24
150 #define FAULT_VMID_MASK (0x7 << 25)
151 #define FAULT_VMID_SHIFT 25
152 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
153 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
154 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
155 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
156 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
158 #define MC_SHARED_CHMAP 0x2004
159 #define NOOFCHAN_SHIFT 12
160 #define NOOFCHAN_MASK 0x00003000
161 #define MC_SHARED_CHREMAP 0x2008
163 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
164 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
165 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
166 #define MC_VM_MX_L1_TLB_CNTL 0x2064
167 #define ENABLE_L1_TLB (1 << 0)
168 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
169 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
170 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
171 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
172 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
173 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
174 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
175 #define FUS_MC_VM_FB_OFFSET 0x2068
177 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
178 #define MC_ARB_RAMCFG 0x2760
179 #define NOOFBANK_SHIFT 0
180 #define NOOFBANK_MASK 0x00000003
181 #define NOOFRANK_SHIFT 2
182 #define NOOFRANK_MASK 0x00000004
183 #define NOOFROWS_SHIFT 3
184 #define NOOFROWS_MASK 0x00000038
185 #define NOOFCOLS_SHIFT 6
186 #define NOOFCOLS_MASK 0x000000C0
187 #define CHANSIZE_SHIFT 8
188 #define CHANSIZE_MASK 0x00000100
189 #define BURSTLENGTH_SHIFT 9
190 #define BURSTLENGTH_MASK 0x00000200
191 #define CHANSIZE_OVERRIDE (1 << 11)
192 #define MC_SEQ_SUP_CNTL 0x28c8
193 #define RUN_MASK (1 << 0)
194 #define MC_SEQ_SUP_PGM 0x28cc
195 #define MC_IO_PAD_CNTL_D0 0x29d0
196 #define MEM_FALL_OUT_CMD (1 << 8)
197 #define MC_SEQ_MISC0 0x2a00
198 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
199 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
200 #define MC_SEQ_MISC0_GDDR5_VALUE 5
201 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
202 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
204 #define HDP_HOST_PATH_CNTL 0x2C00
205 #define HDP_NONSURFACE_BASE 0x2C04
206 #define HDP_NONSURFACE_INFO 0x2C08
207 #define HDP_NONSURFACE_SIZE 0x2C0C
208 #define HDP_ADDR_CONFIG 0x2F48
209 #define HDP_MISC_CNTL 0x2F4C
210 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
212 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
213 #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
214 #define CGTS_SYS_TCC_DISABLE 0x3F90
215 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
217 #define RLC_GFX_INDEX 0x3FC4
219 #define CONFIG_MEMSIZE 0x5428
221 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
222 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
224 #define GRBM_CNTL 0x8000
225 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
226 #define GRBM_STATUS 0x8010
227 #define CMDFIFO_AVAIL_MASK 0x0000000F
228 #define RING2_RQ_PENDING (1 << 4)
229 #define SRBM_RQ_PENDING (1 << 5)
230 #define RING1_RQ_PENDING (1 << 6)
231 #define CF_RQ_PENDING (1 << 7)
232 #define PF_RQ_PENDING (1 << 8)
233 #define GDS_DMA_RQ_PENDING (1 << 9)
234 #define GRBM_EE_BUSY (1 << 10)
235 #define SX_CLEAN (1 << 11)
236 #define DB_CLEAN (1 << 12)
237 #define CB_CLEAN (1 << 13)
238 #define TA_BUSY (1 << 14)
239 #define GDS_BUSY (1 << 15)
240 #define VGT_BUSY_NO_DMA (1 << 16)
241 #define VGT_BUSY (1 << 17)
242 #define IA_BUSY_NO_DMA (1 << 18)
243 #define IA_BUSY (1 << 19)
244 #define SX_BUSY (1 << 20)
245 #define SH_BUSY (1 << 21)
246 #define SPI_BUSY (1 << 22)
247 #define SC_BUSY (1 << 24)
248 #define PA_BUSY (1 << 25)
249 #define DB_BUSY (1 << 26)
250 #define CP_COHERENCY_BUSY (1 << 28)
251 #define CP_BUSY (1 << 29)
252 #define CB_BUSY (1 << 30)
253 #define GUI_ACTIVE (1 << 31)
254 #define GRBM_STATUS_SE0 0x8014
255 #define GRBM_STATUS_SE1 0x8018
256 #define SE_SX_CLEAN (1 << 0)
257 #define SE_DB_CLEAN (1 << 1)
258 #define SE_CB_CLEAN (1 << 2)
259 #define SE_VGT_BUSY (1 << 23)
260 #define SE_PA_BUSY (1 << 24)
261 #define SE_TA_BUSY (1 << 25)
262 #define SE_SX_BUSY (1 << 26)
263 #define SE_SPI_BUSY (1 << 27)
264 #define SE_SH_BUSY (1 << 28)
265 #define SE_SC_BUSY (1 << 29)
266 #define SE_DB_BUSY (1 << 30)
267 #define SE_CB_BUSY (1 << 31)
268 #define GRBM_SOFT_RESET 0x8020
269 #define SOFT_RESET_CP (1 << 0)
270 #define SOFT_RESET_CB (1 << 1)
271 #define SOFT_RESET_DB (1 << 3)
272 #define SOFT_RESET_GDS (1 << 4)
273 #define SOFT_RESET_PA (1 << 5)
274 #define SOFT_RESET_SC (1 << 6)
275 #define SOFT_RESET_SPI (1 << 8)
276 #define SOFT_RESET_SH (1 << 9)
277 #define SOFT_RESET_SX (1 << 10)
278 #define SOFT_RESET_TC (1 << 11)
279 #define SOFT_RESET_TA (1 << 12)
280 #define SOFT_RESET_VGT (1 << 14)
281 #define SOFT_RESET_IA (1 << 15)
283 #define GRBM_GFX_INDEX 0x802C
284 #define INSTANCE_INDEX(x) ((x) << 0)
285 #define SE_INDEX(x) ((x) << 16)
286 #define INSTANCE_BROADCAST_WRITES (1 << 30)
287 #define SE_BROADCAST_WRITES (1 << 31)
289 #define SCRATCH_REG0 0x8500
290 #define SCRATCH_REG1 0x8504
291 #define SCRATCH_REG2 0x8508
292 #define SCRATCH_REG3 0x850C
293 #define SCRATCH_REG4 0x8510
294 #define SCRATCH_REG5 0x8514
295 #define SCRATCH_REG6 0x8518
296 #define SCRATCH_REG7 0x851C
297 #define SCRATCH_UMSK 0x8540
298 #define SCRATCH_ADDR 0x8544
299 #define CP_SEM_WAIT_TIMER 0x85BC
300 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
301 #define CP_COHER_CNTL2 0x85E8
302 #define CP_STALLED_STAT1 0x8674
303 #define CP_STALLED_STAT2 0x8678
304 #define CP_BUSY_STAT 0x867C
305 #define CP_STAT 0x8680
306 #define CP_ME_CNTL 0x86D8
307 #define CP_ME_HALT (1 << 28)
308 #define CP_PFP_HALT (1 << 26)
309 #define CP_RB2_RPTR 0x86f8
310 #define CP_RB1_RPTR 0x86fc
311 #define CP_RB0_RPTR 0x8700
312 #define CP_RB_WPTR_DELAY 0x8704
313 #define CP_MEQ_THRESHOLDS 0x8764
314 #define MEQ1_START(x) ((x) << 0)
315 #define MEQ2_START(x) ((x) << 8)
316 #define CP_PERFMON_CNTL 0x87FC
318 #define VGT_CACHE_INVALIDATION 0x88C4
319 #define CACHE_INVALIDATION(x) ((x) << 0)
320 #define VC_ONLY 0
321 #define TC_ONLY 1
322 #define VC_AND_TC 2
323 #define AUTO_INVLD_EN(x) ((x) << 6)
324 #define NO_AUTO 0
325 #define ES_AUTO 1
326 #define GS_AUTO 2
327 #define ES_AND_GS_AUTO 3
328 #define VGT_GS_VERTEX_REUSE 0x88D4
330 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
331 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
332 #define INACTIVE_QD_PIPES(x) ((x) << 8)
333 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
334 #define INACTIVE_QD_PIPES_SHIFT 8
335 #define INACTIVE_SIMDS(x) ((x) << 16)
336 #define INACTIVE_SIMDS_MASK 0xFFFF0000
337 #define INACTIVE_SIMDS_SHIFT 16
339 #define VGT_PRIMITIVE_TYPE 0x8958
340 #define VGT_NUM_INSTANCES 0x8974
341 #define VGT_TF_RING_SIZE 0x8988
342 #define VGT_OFFCHIP_LDS_BASE 0x89b4
344 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
345 #define PA_CL_ENHANCE 0x8A14
346 #define CLIP_VTX_REORDER_ENA (1 << 0)
347 #define NUM_CLIP_SEQ(x) ((x) << 1)
348 #define PA_SC_FIFO_SIZE 0x8BCC
349 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
350 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
351 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
352 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
353 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
354 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
356 #define SQ_CONFIG 0x8C00
357 #define VC_ENABLE (1 << 0)
358 #define EXPORT_SRC_C (1 << 1)
359 #define GFX_PRIO(x) ((x) << 2)
360 #define CS1_PRIO(x) ((x) << 4)
361 #define CS2_PRIO(x) ((x) << 6)
362 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
363 #define NUM_PS_GPRS(x) ((x) << 0)
364 #define NUM_VS_GPRS(x) ((x) << 16)
365 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
366 #define SQ_ESGS_RING_SIZE 0x8c44
367 #define SQ_GSVS_RING_SIZE 0x8c4c
368 #define SQ_ESTMP_RING_BASE 0x8c50
369 #define SQ_ESTMP_RING_SIZE 0x8c54
370 #define SQ_GSTMP_RING_BASE 0x8c58
371 #define SQ_GSTMP_RING_SIZE 0x8c5c
372 #define SQ_VSTMP_RING_BASE 0x8c60
373 #define SQ_VSTMP_RING_SIZE 0x8c64
374 #define SQ_PSTMP_RING_BASE 0x8c68
375 #define SQ_PSTMP_RING_SIZE 0x8c6c
376 #define SQ_MS_FIFO_SIZES 0x8CF0
377 #define CACHE_FIFO_SIZE(x) ((x) << 0)
378 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
379 #define DONE_FIFO_HIWATER(x) ((x) << 16)
380 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
381 #define SQ_LSTMP_RING_BASE 0x8e10
382 #define SQ_LSTMP_RING_SIZE 0x8e14
383 #define SQ_HSTMP_RING_BASE 0x8e18
384 #define SQ_HSTMP_RING_SIZE 0x8e1c
385 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
386 #define DYN_GPR_ENABLE (1 << 8)
387 #define SQ_CONST_MEM_BASE 0x8df8
389 #define SX_EXPORT_BUFFER_SIZES 0x900C
390 #define COLOR_BUFFER_SIZE(x) ((x) << 0)
391 #define POSITION_BUFFER_SIZE(x) ((x) << 8)
392 #define SMX_BUFFER_SIZE(x) ((x) << 16)
393 #define SX_DEBUG_1 0x9058
394 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
396 #define SPI_CONFIG_CNTL 0x9100
397 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
398 #define SPI_CONFIG_CNTL_1 0x913C
399 #define VTX_DONE_DELAY(x) ((x) << 0)
400 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
401 #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
403 #define CGTS_TCC_DISABLE 0x9148
404 #define CGTS_USER_TCC_DISABLE 0x914C
405 #define TCC_DISABLE_MASK 0xFFFF0000
406 #define TCC_DISABLE_SHIFT 16
407 #define CGTS_SM_CTRL_REG 0x9150
408 #define OVERRIDE (1 << 21)
410 #define TA_CNTL_AUX 0x9508
411 #define DISABLE_CUBE_WRAP (1 << 0)
412 #define DISABLE_CUBE_ANISO (1 << 1)
414 #define TCP_CHAN_STEER_LO 0x960c
415 #define TCP_CHAN_STEER_HI 0x9610
417 #define CC_RB_BACKEND_DISABLE 0x98F4
418 #define BACKEND_DISABLE(x) ((x) << 16)
419 #define GB_ADDR_CONFIG 0x98F8
420 #define NUM_PIPES(x) ((x) << 0)
421 #define NUM_PIPES_MASK 0x00000007
422 #define NUM_PIPES_SHIFT 0
423 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
424 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
425 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
426 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
427 #define NUM_SHADER_ENGINES(x) ((x) << 12)
428 #define NUM_SHADER_ENGINES_MASK 0x00003000
429 #define NUM_SHADER_ENGINES_SHIFT 12
430 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
431 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
432 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
433 #define NUM_GPUS(x) ((x) << 20)
434 #define NUM_GPUS_MASK 0x00700000
435 #define NUM_GPUS_SHIFT 20
436 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
437 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
438 #define MULTI_GPU_TILE_SIZE_SHIFT 24
439 #define ROW_SIZE(x) ((x) << 28)
440 #define ROW_SIZE_MASK 0x30000000
441 #define ROW_SIZE_SHIFT 28
442 #define NUM_LOWER_PIPES(x) ((x) << 30)
443 #define NUM_LOWER_PIPES_MASK 0x40000000
444 #define NUM_LOWER_PIPES_SHIFT 30
445 #define GB_BACKEND_MAP 0x98FC
447 #define CB_PERF_CTR0_SEL_0 0x9A20
448 #define CB_PERF_CTR0_SEL_1 0x9A24
449 #define CB_PERF_CTR1_SEL_0 0x9A28
450 #define CB_PERF_CTR1_SEL_1 0x9A2C
451 #define CB_PERF_CTR2_SEL_0 0x9A30
452 #define CB_PERF_CTR2_SEL_1 0x9A34
453 #define CB_PERF_CTR3_SEL_0 0x9A38
454 #define CB_PERF_CTR3_SEL_1 0x9A3C
456 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
457 #define BACKEND_DISABLE_MASK 0x00FF0000
458 #define BACKEND_DISABLE_SHIFT 16
460 #define SMX_DC_CTL0 0xA020
461 #define USE_HASH_FUNCTION (1 << 0)
462 #define NUMBER_OF_SETS(x) ((x) << 1)
463 #define FLUSH_ALL_ON_EVENT (1 << 10)
464 #define STALL_ON_EVENT (1 << 11)
465 #define SMX_EVENT_CTL 0xA02C
466 #define ES_FLUSH_CTL(x) ((x) << 0)
467 #define GS_FLUSH_CTL(x) ((x) << 3)
468 #define ACK_FLUSH_CTL(x) ((x) << 6)
469 #define SYNC_FLUSH_CTL (1 << 8)
471 #define CP_RB0_BASE 0xC100
472 #define CP_RB0_CNTL 0xC104
473 #define RB_BUFSZ(x) ((x) << 0)
474 #define RB_BLKSZ(x) ((x) << 8)
475 #define RB_NO_UPDATE (1 << 27)
476 #define RB_RPTR_WR_ENA (1 << 31)
477 #define BUF_SWAP_32BIT (2 << 16)
478 #define CP_RB0_RPTR_ADDR 0xC10C
479 #define CP_RB0_RPTR_ADDR_HI 0xC110
480 #define CP_RB0_WPTR 0xC114
482 #define CP_INT_CNTL 0xC124
483 # define CNTX_BUSY_INT_ENABLE (1 << 19)
484 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
485 # define TIME_STAMP_INT_ENABLE (1 << 26)
487 #define CP_RB1_BASE 0xC180
488 #define CP_RB1_CNTL 0xC184
489 #define CP_RB1_RPTR_ADDR 0xC188
490 #define CP_RB1_RPTR_ADDR_HI 0xC18C
491 #define CP_RB1_WPTR 0xC190
492 #define CP_RB2_BASE 0xC194
493 #define CP_RB2_CNTL 0xC198
494 #define CP_RB2_RPTR_ADDR 0xC19C
495 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
496 #define CP_RB2_WPTR 0xC1A4
497 #define CP_PFP_UCODE_ADDR 0xC150
498 #define CP_PFP_UCODE_DATA 0xC154
499 #define CP_ME_RAM_RADDR 0xC158
500 #define CP_ME_RAM_WADDR 0xC15C
501 #define CP_ME_RAM_DATA 0xC160
502 #define CP_DEBUG 0xC1FC
504 #define VGT_EVENT_INITIATOR 0x28a90
505 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
506 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
508 /* TN SMU registers */
509 #define TN_CURRENT_GNB_TEMP 0x1F390
511 /* pm registers */
512 #define SMC_MSG 0x20c
513 #define HOST_SMC_MSG(x) ((x) << 0)
514 #define HOST_SMC_MSG_MASK (0xff << 0)
515 #define HOST_SMC_MSG_SHIFT 0
516 #define HOST_SMC_RESP(x) ((x) << 8)
517 #define HOST_SMC_RESP_MASK (0xff << 8)
518 #define HOST_SMC_RESP_SHIFT 8
519 #define SMC_HOST_MSG(x) ((x) << 16)
520 #define SMC_HOST_MSG_MASK (0xff << 16)
521 #define SMC_HOST_MSG_SHIFT 16
522 #define SMC_HOST_RESP(x) ((x) << 24)
523 #define SMC_HOST_RESP_MASK (0xff << 24)
524 #define SMC_HOST_RESP_SHIFT 24
526 #define CG_SPLL_FUNC_CNTL 0x600
527 #define SPLL_RESET (1 << 0)
528 #define SPLL_SLEEP (1 << 1)
529 #define SPLL_BYPASS_EN (1 << 3)
530 #define SPLL_REF_DIV(x) ((x) << 4)
531 #define SPLL_REF_DIV_MASK (0x3f << 4)
532 #define SPLL_PDIV_A(x) ((x) << 20)
533 #define SPLL_PDIV_A_MASK (0x7f << 20)
534 #define SPLL_PDIV_A_SHIFT 20
535 #define CG_SPLL_FUNC_CNTL_2 0x604
536 #define SCLK_MUX_SEL(x) ((x) << 0)
537 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
538 #define CG_SPLL_FUNC_CNTL_3 0x608
539 #define SPLL_FB_DIV(x) ((x) << 0)
540 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
541 #define SPLL_FB_DIV_SHIFT 0
542 #define SPLL_DITHEN (1 << 28)
544 #define MPLL_CNTL_MODE 0x61c
545 # define SS_SSEN (1 << 24)
546 # define SS_DSMODE_EN (1 << 25)
548 #define MPLL_AD_FUNC_CNTL 0x624
549 #define CLKF(x) ((x) << 0)
550 #define CLKF_MASK (0x7f << 0)
551 #define CLKR(x) ((x) << 7)
552 #define CLKR_MASK (0x1f << 7)
553 #define CLKFRAC(x) ((x) << 12)
554 #define CLKFRAC_MASK (0x1f << 12)
555 #define YCLK_POST_DIV(x) ((x) << 17)
556 #define YCLK_POST_DIV_MASK (3 << 17)
557 #define IBIAS(x) ((x) << 20)
558 #define IBIAS_MASK (0x3ff << 20)
559 #define RESET (1 << 30)
560 #define PDNB (1 << 31)
561 #define MPLL_AD_FUNC_CNTL_2 0x628
562 #define BYPASS (1 << 19)
563 #define BIAS_GEN_PDNB (1 << 24)
564 #define RESET_EN (1 << 25)
565 #define VCO_MODE (1 << 29)
566 #define MPLL_DQ_FUNC_CNTL 0x62c
567 #define MPLL_DQ_FUNC_CNTL_2 0x630
569 #define GENERAL_PWRMGT 0x63c
570 # define GLOBAL_PWRMGT_EN (1 << 0)
571 # define STATIC_PM_EN (1 << 1)
572 # define THERMAL_PROTECTION_DIS (1 << 2)
573 # define THERMAL_PROTECTION_TYPE (1 << 3)
574 # define ENABLE_GEN2PCIE (1 << 4)
575 # define ENABLE_GEN2XSP (1 << 5)
576 # define SW_SMIO_INDEX(x) ((x) << 6)
577 # define SW_SMIO_INDEX_MASK (3 << 6)
578 # define SW_SMIO_INDEX_SHIFT 6
579 # define LOW_VOLT_D2_ACPI (1 << 8)
580 # define LOW_VOLT_D3_ACPI (1 << 9)
581 # define VOLT_PWRMGT_EN (1 << 10)
582 # define BACKBIAS_PAD_EN (1 << 18)
583 # define BACKBIAS_VALUE (1 << 19)
584 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
585 # define AC_DC_SW (1 << 24)
587 #define SCLK_PWRMGT_CNTL 0x644
588 # define SCLK_PWRMGT_OFF (1 << 0)
589 # define SCLK_LOW_D1 (1 << 1)
590 # define FIR_RESET (1 << 4)
591 # define FIR_FORCE_TREND_SEL (1 << 5)
592 # define FIR_TREND_MODE (1 << 6)
593 # define DYN_GFX_CLK_OFF_EN (1 << 7)
594 # define GFX_CLK_FORCE_ON (1 << 8)
595 # define GFX_CLK_REQUEST_OFF (1 << 9)
596 # define GFX_CLK_FORCE_OFF (1 << 10)
597 # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
598 # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
599 # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
600 # define DYN_LIGHT_SLEEP_EN (1 << 14)
601 #define MCLK_PWRMGT_CNTL 0x648
602 # define DLL_SPEED(x) ((x) << 0)
603 # define DLL_SPEED_MASK (0x1f << 0)
604 # define MPLL_PWRMGT_OFF (1 << 5)
605 # define DLL_READY (1 << 6)
606 # define MC_INT_CNTL (1 << 7)
607 # define MRDCKA0_PDNB (1 << 8)
608 # define MRDCKA1_PDNB (1 << 9)
609 # define MRDCKB0_PDNB (1 << 10)
610 # define MRDCKB1_PDNB (1 << 11)
611 # define MRDCKC0_PDNB (1 << 12)
612 # define MRDCKC1_PDNB (1 << 13)
613 # define MRDCKD0_PDNB (1 << 14)
614 # define MRDCKD1_PDNB (1 << 15)
615 # define MRDCKA0_RESET (1 << 16)
616 # define MRDCKA1_RESET (1 << 17)
617 # define MRDCKB0_RESET (1 << 18)
618 # define MRDCKB1_RESET (1 << 19)
619 # define MRDCKC0_RESET (1 << 20)
620 # define MRDCKC1_RESET (1 << 21)
621 # define MRDCKD0_RESET (1 << 22)
622 # define MRDCKD1_RESET (1 << 23)
623 # define DLL_READY_READ (1 << 24)
624 # define USE_DISPLAY_GAP (1 << 25)
625 # define USE_DISPLAY_URGENT_NORMAL (1 << 26)
626 # define MPLL_TURNOFF_D2 (1 << 28)
627 #define DLL_CNTL 0x64c
628 # define MRDCKA0_BYPASS (1 << 24)
629 # define MRDCKA1_BYPASS (1 << 25)
630 # define MRDCKB0_BYPASS (1 << 26)
631 # define MRDCKB1_BYPASS (1 << 27)
632 # define MRDCKC0_BYPASS (1 << 28)
633 # define MRDCKC1_BYPASS (1 << 29)
634 # define MRDCKD0_BYPASS (1 << 30)
635 # define MRDCKD1_BYPASS (1 << 31)
637 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
638 # define CURRENT_STATE_INDEX_MASK (0xf << 4)
639 # define CURRENT_STATE_INDEX_SHIFT 4
641 #define CG_AT 0x6d4
642 # define CG_R(x) ((x) << 0)
643 # define CG_R_MASK (0xffff << 0)
644 # define CG_L(x) ((x) << 16)
645 # define CG_L_MASK (0xffff << 16)
647 #define CG_BIF_REQ_AND_RSP 0x7f4
648 #define CG_CLIENT_REQ(x) ((x) << 0)
649 #define CG_CLIENT_REQ_MASK (0xff << 0)
650 #define CG_CLIENT_REQ_SHIFT 0
651 #define CG_CLIENT_RESP(x) ((x) << 8)
652 #define CG_CLIENT_RESP_MASK (0xff << 8)
653 #define CG_CLIENT_RESP_SHIFT 8
654 #define CLIENT_CG_REQ(x) ((x) << 16)
655 #define CLIENT_CG_REQ_MASK (0xff << 16)
656 #define CLIENT_CG_REQ_SHIFT 16
657 #define CLIENT_CG_RESP(x) ((x) << 24)
658 #define CLIENT_CG_RESP_MASK (0xff << 24)
659 #define CLIENT_CG_RESP_SHIFT 24
661 #define CG_SPLL_SPREAD_SPECTRUM 0x790
662 #define SSEN (1 << 0)
663 #define CLK_S(x) ((x) << 4)
664 #define CLK_S_MASK (0xfff << 4)
665 #define CLK_S_SHIFT 4
666 #define CG_SPLL_SPREAD_SPECTRUM_2 0x794
667 #define CLK_V(x) ((x) << 0)
668 #define CLK_V_MASK (0x3ffffff << 0)
669 #define CLK_V_SHIFT 0
671 #define SMC_SCRATCH0 0x81c
673 #define CG_SPLL_FUNC_CNTL_4 0x850
675 #define MPLL_SS1 0x85c
676 #define CLKV(x) ((x) << 0)
677 #define CLKV_MASK (0x3ffffff << 0)
678 #define MPLL_SS2 0x860
679 #define CLKS(x) ((x) << 0)
680 #define CLKS_MASK (0xfff << 0)
682 #define CG_CAC_CTRL 0x88c
683 #define TID_CNT(x) ((x) << 0)
684 #define TID_CNT_MASK (0x3fff << 0)
685 #define TID_UNIT(x) ((x) << 14)
686 #define TID_UNIT_MASK (0xf << 14)
688 #define CG_IND_ADDR 0x8f8
689 #define CG_IND_DATA 0x8fc
690 /* CGIND regs */
691 #define CG_CGTT_LOCAL_0 0x00
692 #define CG_CGTT_LOCAL_1 0x01
694 #define MC_CG_CONFIG 0x25bc
695 #define MCDW_WR_ENABLE (1 << 0)
696 #define MCDX_WR_ENABLE (1 << 1)
697 #define MCDY_WR_ENABLE (1 << 2)
698 #define MCDZ_WR_ENABLE (1 << 3)
699 #define MC_RD_ENABLE(x) ((x) << 4)
700 #define MC_RD_ENABLE_MASK (3 << 4)
701 #define INDEX(x) ((x) << 6)
702 #define INDEX_MASK (0xfff << 6)
703 #define INDEX_SHIFT 6
705 #define MC_ARB_CAC_CNTL 0x2750
706 #define ENABLE (1 << 0)
707 #define READ_WEIGHT(x) ((x) << 1)
708 #define READ_WEIGHT_MASK (0x3f << 1)
709 #define READ_WEIGHT_SHIFT 1
710 #define WRITE_WEIGHT(x) ((x) << 7)
711 #define WRITE_WEIGHT_MASK (0x3f << 7)
712 #define WRITE_WEIGHT_SHIFT 7
713 #define ALLOW_OVERFLOW (1 << 13)
715 #define MC_ARB_DRAM_TIMING 0x2774
716 #define MC_ARB_DRAM_TIMING2 0x2778
718 #define MC_ARB_RFSH_RATE 0x27b0
719 #define POWERMODE0(x) ((x) << 0)
720 #define POWERMODE0_MASK (0xff << 0)
721 #define POWERMODE0_SHIFT 0
722 #define POWERMODE1(x) ((x) << 8)
723 #define POWERMODE1_MASK (0xff << 8)
724 #define POWERMODE1_SHIFT 8
725 #define POWERMODE2(x) ((x) << 16)
726 #define POWERMODE2_MASK (0xff << 16)
727 #define POWERMODE2_SHIFT 16
728 #define POWERMODE3(x) ((x) << 24)
729 #define POWERMODE3_MASK (0xff << 24)
730 #define POWERMODE3_SHIFT 24
732 #define MC_ARB_CG 0x27e8
733 #define CG_ARB_REQ(x) ((x) << 0)
734 #define CG_ARB_REQ_MASK (0xff << 0)
735 #define CG_ARB_REQ_SHIFT 0
736 #define CG_ARB_RESP(x) ((x) << 8)
737 #define CG_ARB_RESP_MASK (0xff << 8)
738 #define CG_ARB_RESP_SHIFT 8
739 #define ARB_CG_REQ(x) ((x) << 16)
740 #define ARB_CG_REQ_MASK (0xff << 16)
741 #define ARB_CG_REQ_SHIFT 16
742 #define ARB_CG_RESP(x) ((x) << 24)
743 #define ARB_CG_RESP_MASK (0xff << 24)
744 #define ARB_CG_RESP_SHIFT 24
746 #define MC_ARB_DRAM_TIMING_1 0x27f0
747 #define MC_ARB_DRAM_TIMING_2 0x27f4
748 #define MC_ARB_DRAM_TIMING_3 0x27f8
749 #define MC_ARB_DRAM_TIMING2_1 0x27fc
750 #define MC_ARB_DRAM_TIMING2_2 0x2800
751 #define MC_ARB_DRAM_TIMING2_3 0x2804
752 #define MC_ARB_BURST_TIME 0x2808
753 #define STATE0(x) ((x) << 0)
754 #define STATE0_MASK (0x1f << 0)
755 #define STATE0_SHIFT 0
756 #define STATE1(x) ((x) << 5)
757 #define STATE1_MASK (0x1f << 5)
758 #define STATE1_SHIFT 5
759 #define STATE2(x) ((x) << 10)
760 #define STATE2_MASK (0x1f << 10)
761 #define STATE2_SHIFT 10
762 #define STATE3(x) ((x) << 15)
763 #define STATE3_MASK (0x1f << 15)
764 #define STATE3_SHIFT 15
766 #define MC_CG_DATAPORT 0x2884
768 #define MC_SEQ_RAS_TIMING 0x28a0
769 #define MC_SEQ_CAS_TIMING 0x28a4
770 #define MC_SEQ_MISC_TIMING 0x28a8
771 #define MC_SEQ_MISC_TIMING2 0x28ac
772 #define MC_SEQ_PMG_TIMING 0x28b0
773 #define MC_SEQ_RD_CTL_D0 0x28b4
774 #define MC_SEQ_RD_CTL_D1 0x28b8
775 #define MC_SEQ_WR_CTL_D0 0x28bc
776 #define MC_SEQ_WR_CTL_D1 0x28c0
778 #define MC_SEQ_MISC0 0x2a00
779 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
780 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
781 #define MC_SEQ_MISC0_GDDR5_VALUE 5
782 #define MC_SEQ_MISC1 0x2a04
783 #define MC_SEQ_RESERVE_M 0x2a08
784 #define MC_PMG_CMD_EMRS 0x2a0c
786 #define MC_SEQ_MISC3 0x2a2c
788 #define MC_SEQ_MISC5 0x2a54
789 #define MC_SEQ_MISC6 0x2a58
791 #define MC_SEQ_MISC7 0x2a64
793 #define MC_SEQ_RAS_TIMING_LP 0x2a6c
794 #define MC_SEQ_CAS_TIMING_LP 0x2a70
795 #define MC_SEQ_MISC_TIMING_LP 0x2a74
796 #define MC_SEQ_MISC_TIMING2_LP 0x2a78
797 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
798 #define MC_SEQ_WR_CTL_D1_LP 0x2a80
799 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
800 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
802 #define MC_PMG_CMD_MRS 0x2aac
804 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
805 #define MC_SEQ_RD_CTL_D1_LP 0x2b20
807 #define MC_PMG_CMD_MRS1 0x2b44
808 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
809 #define MC_SEQ_PMG_TIMING_LP 0x2b4c
811 #define MC_PMG_CMD_MRS2 0x2b5c
812 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
814 #define LB_SYNC_RESET_SEL 0x6b28
815 #define LB_SYNC_RESET_SEL_MASK (3 << 0)
816 #define LB_SYNC_RESET_SEL_SHIFT 0
818 #define DC_STUTTER_CNTL 0x6b30
819 #define DC_STUTTER_ENABLE_A (1 << 0)
820 #define DC_STUTTER_ENABLE_B (1 << 1)
822 #define SQ_CAC_THRESHOLD 0x8e4c
823 #define VSP(x) ((x) << 0)
824 #define VSP_MASK (0xff << 0)
825 #define VSP_SHIFT 0
826 #define VSP0(x) ((x) << 8)
827 #define VSP0_MASK (0xff << 8)
828 #define VSP0_SHIFT 8
829 #define GPR(x) ((x) << 16)
830 #define GPR_MASK (0xff << 16)
831 #define GPR_SHIFT 16
833 #define SQ_POWER_THROTTLE 0x8e58
834 #define MIN_POWER(x) ((x) << 0)
835 #define MIN_POWER_MASK (0x3fff << 0)
836 #define MIN_POWER_SHIFT 0
837 #define MAX_POWER(x) ((x) << 16)
838 #define MAX_POWER_MASK (0x3fff << 16)
839 #define MAX_POWER_SHIFT 0
840 #define SQ_POWER_THROTTLE2 0x8e5c
841 #define MAX_POWER_DELTA(x) ((x) << 0)
842 #define MAX_POWER_DELTA_MASK (0x3fff << 0)
843 #define MAX_POWER_DELTA_SHIFT 0
844 #define STI_SIZE(x) ((x) << 16)
845 #define STI_SIZE_MASK (0x3ff << 16)
846 #define STI_SIZE_SHIFT 16
847 #define LTI_RATIO(x) ((x) << 27)
848 #define LTI_RATIO_MASK (0xf << 27)
849 #define LTI_RATIO_SHIFT 27
851 /* CG indirect registers */
852 #define CG_CAC_REGION_1_WEIGHT_0 0x83
853 #define WEIGHT_TCP_SIG0(x) ((x) << 0)
854 #define WEIGHT_TCP_SIG0_MASK (0x3f << 0)
855 #define WEIGHT_TCP_SIG0_SHIFT 0
856 #define WEIGHT_TCP_SIG1(x) ((x) << 6)
857 #define WEIGHT_TCP_SIG1_MASK (0x3f << 6)
858 #define WEIGHT_TCP_SIG1_SHIFT 6
859 #define WEIGHT_TA_SIG(x) ((x) << 12)
860 #define WEIGHT_TA_SIG_MASK (0x3f << 12)
861 #define WEIGHT_TA_SIG_SHIFT 12
862 #define CG_CAC_REGION_1_WEIGHT_1 0x84
863 #define WEIGHT_TCC_EN0(x) ((x) << 0)
864 #define WEIGHT_TCC_EN0_MASK (0x3f << 0)
865 #define WEIGHT_TCC_EN0_SHIFT 0
866 #define WEIGHT_TCC_EN1(x) ((x) << 6)
867 #define WEIGHT_TCC_EN1_MASK (0x3f << 6)
868 #define WEIGHT_TCC_EN1_SHIFT 6
869 #define WEIGHT_TCC_EN2(x) ((x) << 12)
870 #define WEIGHT_TCC_EN2_MASK (0x3f << 12)
871 #define WEIGHT_TCC_EN2_SHIFT 12
872 #define WEIGHT_TCC_EN3(x) ((x) << 18)
873 #define WEIGHT_TCC_EN3_MASK (0x3f << 18)
874 #define WEIGHT_TCC_EN3_SHIFT 18
875 #define CG_CAC_REGION_2_WEIGHT_0 0x85
876 #define WEIGHT_CB_EN0(x) ((x) << 0)
877 #define WEIGHT_CB_EN0_MASK (0x3f << 0)
878 #define WEIGHT_CB_EN0_SHIFT 0
879 #define WEIGHT_CB_EN1(x) ((x) << 6)
880 #define WEIGHT_CB_EN1_MASK (0x3f << 6)
881 #define WEIGHT_CB_EN1_SHIFT 6
882 #define WEIGHT_CB_EN2(x) ((x) << 12)
883 #define WEIGHT_CB_EN2_MASK (0x3f << 12)
884 #define WEIGHT_CB_EN2_SHIFT 12
885 #define WEIGHT_CB_EN3(x) ((x) << 18)
886 #define WEIGHT_CB_EN3_MASK (0x3f << 18)
887 #define WEIGHT_CB_EN3_SHIFT 18
888 #define CG_CAC_REGION_2_WEIGHT_1 0x86
889 #define WEIGHT_DB_SIG0(x) ((x) << 0)
890 #define WEIGHT_DB_SIG0_MASK (0x3f << 0)
891 #define WEIGHT_DB_SIG0_SHIFT 0
892 #define WEIGHT_DB_SIG1(x) ((x) << 6)
893 #define WEIGHT_DB_SIG1_MASK (0x3f << 6)
894 #define WEIGHT_DB_SIG1_SHIFT 6
895 #define WEIGHT_DB_SIG2(x) ((x) << 12)
896 #define WEIGHT_DB_SIG2_MASK (0x3f << 12)
897 #define WEIGHT_DB_SIG2_SHIFT 12
898 #define WEIGHT_DB_SIG3(x) ((x) << 18)
899 #define WEIGHT_DB_SIG3_MASK (0x3f << 18)
900 #define WEIGHT_DB_SIG3_SHIFT 18
901 #define CG_CAC_REGION_2_WEIGHT_2 0x87
902 #define WEIGHT_SXM_SIG0(x) ((x) << 0)
903 #define WEIGHT_SXM_SIG0_MASK (0x3f << 0)
904 #define WEIGHT_SXM_SIG0_SHIFT 0
905 #define WEIGHT_SXM_SIG1(x) ((x) << 6)
906 #define WEIGHT_SXM_SIG1_MASK (0x3f << 6)
907 #define WEIGHT_SXM_SIG1_SHIFT 6
908 #define WEIGHT_SXM_SIG2(x) ((x) << 12)
909 #define WEIGHT_SXM_SIG2_MASK (0x3f << 12)
910 #define WEIGHT_SXM_SIG2_SHIFT 12
911 #define WEIGHT_SXS_SIG0(x) ((x) << 18)
912 #define WEIGHT_SXS_SIG0_MASK (0x3f << 18)
913 #define WEIGHT_SXS_SIG0_SHIFT 18
914 #define WEIGHT_SXS_SIG1(x) ((x) << 24)
915 #define WEIGHT_SXS_SIG1_MASK (0x3f << 24)
916 #define WEIGHT_SXS_SIG1_SHIFT 24
917 #define CG_CAC_REGION_3_WEIGHT_0 0x88
918 #define WEIGHT_XBR_0(x) ((x) << 0)
919 #define WEIGHT_XBR_0_MASK (0x3f << 0)
920 #define WEIGHT_XBR_0_SHIFT 0
921 #define WEIGHT_XBR_1(x) ((x) << 6)
922 #define WEIGHT_XBR_1_MASK (0x3f << 6)
923 #define WEIGHT_XBR_1_SHIFT 6
924 #define WEIGHT_XBR_2(x) ((x) << 12)
925 #define WEIGHT_XBR_2_MASK (0x3f << 12)
926 #define WEIGHT_XBR_2_SHIFT 12
927 #define WEIGHT_SPI_SIG0(x) ((x) << 18)
928 #define WEIGHT_SPI_SIG0_MASK (0x3f << 18)
929 #define WEIGHT_SPI_SIG0_SHIFT 18
930 #define CG_CAC_REGION_3_WEIGHT_1 0x89
931 #define WEIGHT_SPI_SIG1(x) ((x) << 0)
932 #define WEIGHT_SPI_SIG1_MASK (0x3f << 0)
933 #define WEIGHT_SPI_SIG1_SHIFT 0
934 #define WEIGHT_SPI_SIG2(x) ((x) << 6)
935 #define WEIGHT_SPI_SIG2_MASK (0x3f << 6)
936 #define WEIGHT_SPI_SIG2_SHIFT 6
937 #define WEIGHT_SPI_SIG3(x) ((x) << 12)
938 #define WEIGHT_SPI_SIG3_MASK (0x3f << 12)
939 #define WEIGHT_SPI_SIG3_SHIFT 12
940 #define WEIGHT_SPI_SIG4(x) ((x) << 18)
941 #define WEIGHT_SPI_SIG4_MASK (0x3f << 18)
942 #define WEIGHT_SPI_SIG4_SHIFT 18
943 #define WEIGHT_SPI_SIG5(x) ((x) << 24)
944 #define WEIGHT_SPI_SIG5_MASK (0x3f << 24)
945 #define WEIGHT_SPI_SIG5_SHIFT 24
946 #define CG_CAC_REGION_4_WEIGHT_0 0x8a
947 #define WEIGHT_LDS_SIG0(x) ((x) << 0)
948 #define WEIGHT_LDS_SIG0_MASK (0x3f << 0)
949 #define WEIGHT_LDS_SIG0_SHIFT 0
950 #define WEIGHT_LDS_SIG1(x) ((x) << 6)
951 #define WEIGHT_LDS_SIG1_MASK (0x3f << 6)
952 #define WEIGHT_LDS_SIG1_SHIFT 6
953 #define WEIGHT_SC(x) ((x) << 24)
954 #define WEIGHT_SC_MASK (0x3f << 24)
955 #define WEIGHT_SC_SHIFT 24
956 #define CG_CAC_REGION_4_WEIGHT_1 0x8b
957 #define WEIGHT_BIF(x) ((x) << 0)
958 #define WEIGHT_BIF_MASK (0x3f << 0)
959 #define WEIGHT_BIF_SHIFT 0
960 #define WEIGHT_CP(x) ((x) << 6)
961 #define WEIGHT_CP_MASK (0x3f << 6)
962 #define WEIGHT_CP_SHIFT 6
963 #define WEIGHT_PA_SIG0(x) ((x) << 12)
964 #define WEIGHT_PA_SIG0_MASK (0x3f << 12)
965 #define WEIGHT_PA_SIG0_SHIFT 12
966 #define WEIGHT_PA_SIG1(x) ((x) << 18)
967 #define WEIGHT_PA_SIG1_MASK (0x3f << 18)
968 #define WEIGHT_PA_SIG1_SHIFT 18
969 #define WEIGHT_VGT_SIG0(x) ((x) << 24)
970 #define WEIGHT_VGT_SIG0_MASK (0x3f << 24)
971 #define WEIGHT_VGT_SIG0_SHIFT 24
972 #define CG_CAC_REGION_4_WEIGHT_2 0x8c
973 #define WEIGHT_VGT_SIG1(x) ((x) << 0)
974 #define WEIGHT_VGT_SIG1_MASK (0x3f << 0)
975 #define WEIGHT_VGT_SIG1_SHIFT 0
976 #define WEIGHT_VGT_SIG2(x) ((x) << 6)
977 #define WEIGHT_VGT_SIG2_MASK (0x3f << 6)
978 #define WEIGHT_VGT_SIG2_SHIFT 6
979 #define WEIGHT_DC_SIG0(x) ((x) << 12)
980 #define WEIGHT_DC_SIG0_MASK (0x3f << 12)
981 #define WEIGHT_DC_SIG0_SHIFT 12
982 #define WEIGHT_DC_SIG1(x) ((x) << 18)
983 #define WEIGHT_DC_SIG1_MASK (0x3f << 18)
984 #define WEIGHT_DC_SIG1_SHIFT 18
985 #define WEIGHT_DC_SIG2(x) ((x) << 24)
986 #define WEIGHT_DC_SIG2_MASK (0x3f << 24)
987 #define WEIGHT_DC_SIG2_SHIFT 24
988 #define CG_CAC_REGION_4_WEIGHT_3 0x8d
989 #define WEIGHT_DC_SIG3(x) ((x) << 0)
990 #define WEIGHT_DC_SIG3_MASK (0x3f << 0)
991 #define WEIGHT_DC_SIG3_SHIFT 0
992 #define WEIGHT_UVD_SIG0(x) ((x) << 6)
993 #define WEIGHT_UVD_SIG0_MASK (0x3f << 6)
994 #define WEIGHT_UVD_SIG0_SHIFT 6
995 #define WEIGHT_UVD_SIG1(x) ((x) << 12)
996 #define WEIGHT_UVD_SIG1_MASK (0x3f << 12)
997 #define WEIGHT_UVD_SIG1_SHIFT 12
998 #define WEIGHT_SPARE0(x) ((x) << 18)
999 #define WEIGHT_SPARE0_MASK (0x3f << 18)
1000 #define WEIGHT_SPARE0_SHIFT 18
1001 #define WEIGHT_SPARE1(x) ((x) << 24)
1002 #define WEIGHT_SPARE1_MASK (0x3f << 24)
1003 #define WEIGHT_SPARE1_SHIFT 24
1004 #define CG_CAC_REGION_5_WEIGHT_0 0x8e
1005 #define WEIGHT_SQ_VSP(x) ((x) << 0)
1006 #define WEIGHT_SQ_VSP_MASK (0x3fff << 0)
1007 #define WEIGHT_SQ_VSP_SHIFT 0
1008 #define WEIGHT_SQ_VSP0(x) ((x) << 14)
1009 #define WEIGHT_SQ_VSP0_MASK (0x3fff << 14)
1010 #define WEIGHT_SQ_VSP0_SHIFT 14
1011 #define CG_CAC_REGION_4_OVERRIDE_4 0xab
1012 #define OVR_MODE_SPARE_0(x) ((x) << 16)
1013 #define OVR_MODE_SPARE_0_MASK (0x1 << 16)
1014 #define OVR_MODE_SPARE_0_SHIFT 16
1015 #define OVR_VAL_SPARE_0(x) ((x) << 17)
1016 #define OVR_VAL_SPARE_0_MASK (0x1 << 17)
1017 #define OVR_VAL_SPARE_0_SHIFT 17
1018 #define OVR_MODE_SPARE_1(x) ((x) << 18)
1019 #define OVR_MODE_SPARE_1_MASK (0x3f << 18)
1020 #define OVR_MODE_SPARE_1_SHIFT 18
1021 #define OVR_VAL_SPARE_1(x) ((x) << 19)
1022 #define OVR_VAL_SPARE_1_MASK (0x3f << 19)
1023 #define OVR_VAL_SPARE_1_SHIFT 19
1024 #define CG_CAC_REGION_5_WEIGHT_1 0xb7
1025 #define WEIGHT_SQ_GPR(x) ((x) << 0)
1026 #define WEIGHT_SQ_GPR_MASK (0x3fff << 0)
1027 #define WEIGHT_SQ_GPR_SHIFT 0
1028 #define WEIGHT_SQ_LDS(x) ((x) << 14)
1029 #define WEIGHT_SQ_LDS_MASK (0x3fff << 14)
1030 #define WEIGHT_SQ_LDS_SHIFT 14
1032 /* PCIE link stuff */
1035 # define LC_LINK_WIDTH_SHIFT 0
1036 # define LC_LINK_WIDTH_MASK 0x7
1037 # define LC_LINK_WIDTH_X0 0
1038 # define LC_LINK_WIDTH_X1 1
1039 # define LC_LINK_WIDTH_X2 2
1040 # define LC_LINK_WIDTH_X4 3
1041 # define LC_LINK_WIDTH_X8 4
1042 # define LC_LINK_WIDTH_X16 6
1043 # define LC_LINK_WIDTH_RD_SHIFT 4
1044 # define LC_LINK_WIDTH_RD_MASK 0x70
1045 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1046 # define LC_RECONFIG_NOW (1 << 8)
1047 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
1048 # define LC_RENEGOTIATE_EN (1 << 10)
1049 # define LC_SHORT_RECONFIG_EN (1 << 11)
1050 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
1051 # define LC_UPCONFIGURE_DIS (1 << 13)
1053 # define LC_GEN2_EN_STRAP (1 << 0)
1054 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
1055 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
1056 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
1057 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
1058 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
1059 # define LC_CURRENT_DATA_RATE (1 << 11)
1060 # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
1061 # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
1062 # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
1063 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
1064 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
1065 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
1066 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
1067 #define MM_CFGREGS_CNTL 0x544c
1068 # define MM_WR_TO_CFG_EN (1 << 3)
1070 # define TARGET_LINK_SPEED_MASK (0xf << 0)
1071 # define SELECTABLE_DEEMPHASIS (1 << 6)
1073 /*
1074 * UVD
1075 */
1076 #define UVD_SEMA_ADDR_LOW 0xEF00
1077 #define UVD_SEMA_ADDR_HIGH 0xEF04
1078 #define UVD_SEMA_CMD 0xEF08
1079 #define UVD_UDEC_ADDR_CONFIG 0xEF4C
1080 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
1081 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
1082 #define UVD_RBC_RB_RPTR 0xF690
1083 #define UVD_RBC_RB_WPTR 0xF694
1085 /*
1086 * PM4
1087 */
1088 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1089 (((reg) >> 2) & 0xFFFF) | \
1090 ((n) & 0x3FFF) << 16)
1091 #define CP_PACKET2 0x80000000
1092 #define PACKET2_PAD_SHIFT 0
1093 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1095 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1097 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1098 (((op) & 0xFF) << 8) | \
1099 ((n) & 0x3FFF) << 16)
1101 /* Packet 3 types */
1102 #define PACKET3_NOP 0x10
1103 #define PACKET3_SET_BASE 0x11
1104 #define PACKET3_CLEAR_STATE 0x12
1105 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1106 #define PACKET3_DEALLOC_STATE 0x14
1107 #define PACKET3_DISPATCH_DIRECT 0x15
1108 #define PACKET3_DISPATCH_INDIRECT 0x16
1109 #define PACKET3_INDIRECT_BUFFER_END 0x17
1110 #define PACKET3_MODE_CONTROL 0x18
1111 #define PACKET3_SET_PREDICATION 0x20
1112 #define PACKET3_REG_RMW 0x21
1113 #define PACKET3_COND_EXEC 0x22
1114 #define PACKET3_PRED_EXEC 0x23
1115 #define PACKET3_DRAW_INDIRECT 0x24
1116 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1117 #define PACKET3_INDEX_BASE 0x26
1118 #define PACKET3_DRAW_INDEX_2 0x27
1119 #define PACKET3_CONTEXT_CONTROL 0x28
1120 #define PACKET3_DRAW_INDEX_OFFSET 0x29
1121 #define PACKET3_INDEX_TYPE 0x2A
1122 #define PACKET3_DRAW_INDEX 0x2B
1123 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1124 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1125 #define PACKET3_NUM_INSTANCES 0x2F
1126 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1127 #define PACKET3_INDIRECT_BUFFER 0x32
1128 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1129 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1130 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1131 #define PACKET3_WRITE_DATA 0x37
1132 #define PACKET3_MEM_SEMAPHORE 0x39
1133 #define PACKET3_MPEG_INDEX 0x3A
1134 #define PACKET3_WAIT_REG_MEM 0x3C
1135 #define PACKET3_MEM_WRITE 0x3D
1136 #define PACKET3_PFP_SYNC_ME 0x42
1137 #define PACKET3_SURFACE_SYNC 0x43
1138 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1139 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1140 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1141 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1142 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1143 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1144 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1145 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1146 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1147 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
1148 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
1149 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
1150 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
1151 # define PACKET3_FULL_CACHE_ENA (1 << 20)
1152 # define PACKET3_TC_ACTION_ENA (1 << 23)
1153 # define PACKET3_CB_ACTION_ENA (1 << 25)
1154 # define PACKET3_DB_ACTION_ENA (1 << 26)
1155 # define PACKET3_SH_ACTION_ENA (1 << 27)
1156 # define PACKET3_SX_ACTION_ENA (1 << 28)
1157 # define PACKET3_ENGINE_ME (1 << 31)
1158 #define PACKET3_ME_INITIALIZE 0x44
1159 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1160 #define PACKET3_COND_WRITE 0x45
1161 #define PACKET3_EVENT_WRITE 0x46
1162 #define EVENT_TYPE(x) ((x) << 0)
1163 #define EVENT_INDEX(x) ((x) << 8)
1164 /* 0 - any non-TS event
1165 * 1 - ZPASS_DONE
1166 * 2 - SAMPLE_PIPELINESTAT
1167 * 3 - SAMPLE_STREAMOUTSTAT*
1168 * 4 - *S_PARTIAL_FLUSH
1169 * 5 - TS events
1170 */
1171 #define PACKET3_EVENT_WRITE_EOP 0x47
1172 #define DATA_SEL(x) ((x) << 29)
1173 /* 0 - discard
1174 * 1 - send low 32bit data
1175 * 2 - send 64bit data
1176 * 3 - send 64bit counter value
1177 */
1178 #define INT_SEL(x) ((x) << 24)
1179 /* 0 - none
1180 * 1 - interrupt only (DATA_SEL = 0)
1181 * 2 - interrupt when data write is confirmed
1182 */
1183 #define PACKET3_EVENT_WRITE_EOS 0x48
1184 #define PACKET3_PREAMBLE_CNTL 0x4A
1185 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1186 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1187 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
1188 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
1189 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E
1190 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F
1191 #define PACKET3_ONE_REG_WRITE 0x57
1192 #define PACKET3_SET_CONFIG_REG 0x68
1193 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1194 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
1195 #define PACKET3_SET_CONTEXT_REG 0x69
1196 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1197 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1198 #define PACKET3_SET_ALU_CONST 0x6A
1199 /* alu const buffers only; no reg file */
1200 #define PACKET3_SET_BOOL_CONST 0x6B
1201 #define PACKET3_SET_BOOL_CONST_START 0x0003a500
1202 #define PACKET3_SET_BOOL_CONST_END 0x0003a518
1203 #define PACKET3_SET_LOOP_CONST 0x6C
1204 #define PACKET3_SET_LOOP_CONST_START 0x0003a200
1205 #define PACKET3_SET_LOOP_CONST_END 0x0003a500
1206 #define PACKET3_SET_RESOURCE 0x6D
1207 #define PACKET3_SET_RESOURCE_START 0x00030000
1208 #define PACKET3_SET_RESOURCE_END 0x00038000
1209 #define PACKET3_SET_SAMPLER 0x6E
1210 #define PACKET3_SET_SAMPLER_START 0x0003c000
1211 #define PACKET3_SET_SAMPLER_END 0x0003c600
1212 #define PACKET3_SET_CTL_CONST 0x6F
1213 #define PACKET3_SET_CTL_CONST_START 0x0003cff0
1214 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c
1215 #define PACKET3_SET_RESOURCE_OFFSET 0x70
1216 #define PACKET3_SET_ALU_CONST_VS 0x71
1217 #define PACKET3_SET_ALU_CONST_DI 0x72
1218 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1219 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
1220 #define PACKET3_SET_APPEND_CNT 0x75
1221 #define PACKET3_ME_WRITE 0x7A
1223 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1227 #define DMA_RB_CNTL 0xd000
1228 # define DMA_RB_ENABLE (1 << 0)
1231 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1234 #define DMA_RB_BASE 0xd004
1235 #define DMA_RB_RPTR 0xd008
1236 #define DMA_RB_WPTR 0xd00c
1238 #define DMA_RB_RPTR_ADDR_HI 0xd01c
1239 #define DMA_RB_RPTR_ADDR_LO 0xd020
1241 #define DMA_IB_CNTL 0xd024
1242 # define DMA_IB_ENABLE (1 << 0)
1243 # define DMA_IB_SWAP_ENABLE (1 << 4)
1244 # define CMD_VMID_FORCE (1 << 31)
1245 #define DMA_IB_RPTR 0xd028
1246 #define DMA_CNTL 0xd02c
1247 # define TRAP_ENABLE (1 << 0)
1248 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1249 # define SEM_WAIT_INT_ENABLE (1 << 2)
1250 # define DATA_SWAP_ENABLE (1 << 3)
1251 # define FENCE_SWAP_ENABLE (1 << 4)
1252 # define CTXEMPTY_INT_ENABLE (1 << 28)
1253 #define DMA_STATUS_REG 0xd034
1254 # define DMA_IDLE (1 << 0)
1255 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044
1256 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048
1257 #define DMA_TILING_CONFIG 0xd0b8
1258 #define DMA_MODE 0xd0bc
1260 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
1261 (((t) & 0x1) << 23) | \
1262 (((s) & 0x1) << 22) | \
1263 (((n) & 0xFFFFF) << 0))
1265 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1266 (((vmid) & 0xF) << 20) | \
1267 (((n) & 0xFFFFF) << 0))
1269 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
1270 (1 << 26) | \
1271 (1 << 21) | \
1272 (((n) & 0xFFFFF) << 0))
1274 /* async DMA Packet types */
1275 #define DMA_PACKET_WRITE 0x2
1276 #define DMA_PACKET_COPY 0x3
1277 #define DMA_PACKET_INDIRECT_BUFFER 0x4
1278 #define DMA_PACKET_SEMAPHORE 0x5
1279 #define DMA_PACKET_FENCE 0x6
1280 #define DMA_PACKET_TRAP 0x7
1281 #define DMA_PACKET_SRBM_WRITE 0x9
1282 #define DMA_PACKET_CONSTANT_FILL 0xd
1283 #define DMA_PACKET_NOP 0xf
1285 #endif