2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
26 #include <linux/hdmi.h>
27 #include <linux/gcd.h>
29 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
38 enum r600_hdmi_color_format
{
45 * IEC60958 status bits
47 enum r600_hdmi_iec_status_bits
{
48 AUDIO_STATUS_DIG_ENABLE
= 0x01,
49 AUDIO_STATUS_V
= 0x02,
50 AUDIO_STATUS_VCFG
= 0x04,
51 AUDIO_STATUS_EMPHASIS
= 0x08,
52 AUDIO_STATUS_COPYRIGHT
= 0x10,
53 AUDIO_STATUS_NONAUDIO
= 0x20,
54 AUDIO_STATUS_PROFESSIONAL
= 0x40,
55 AUDIO_STATUS_LEVEL
= 0x80
58 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr
[] = {
59 /* 32kHz 44.1kHz 48kHz */
60 /* Clock N CTS N CTS N CTS */
61 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
62 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
63 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
64 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
65 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
66 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
67 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
68 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
69 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
70 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
75 * calculate CTS and N values if they are not found in the table
77 static void r600_hdmi_calc_cts(uint32_t clock
, int *CTS
, int *N
, int freq
)
80 unsigned long div
, mul
;
82 /* Safe, but overly large values */
86 /* Smallest valid fraction */
93 * The optimal N is 128*freq/1000. Calculate the closest larger
94 * value that doesn't truncate any bits.
96 mul
= ((128*freq
/1000) + (n
-1))/n
;
101 /* Check that we are in spec (not always possible) */
102 if (n
< (128*freq
/1500))
103 printk(KERN_WARNING
"Calculated ACR N value is too small. You may experience audio problems.\n");
104 if (n
> (128*freq
/300))
105 printk(KERN_WARNING
"Calculated ACR N value is too large. You may experience audio problems.\n");
110 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
114 struct radeon_hdmi_acr
r600_hdmi_acr(uint32_t clock
)
116 struct radeon_hdmi_acr res
;
119 /* Precalculated values for common clocks */
120 for (i
= 0; i
< ARRAY_SIZE(r600_hdmi_predefined_acr
); i
++) {
121 if (r600_hdmi_predefined_acr
[i
].clock
== clock
)
122 return r600_hdmi_predefined_acr
[i
];
125 /* And odd clocks get manually calculated */
126 r600_hdmi_calc_cts(clock
, &res
.cts_32khz
, &res
.n_32khz
, 32000);
127 r600_hdmi_calc_cts(clock
, &res
.cts_44_1khz
, &res
.n_44_1khz
, 44100);
128 r600_hdmi_calc_cts(clock
, &res
.cts_48khz
, &res
.n_48khz
, 48000);
134 * update the N and CTS parameters for a given pixel clock rate
136 static void r600_hdmi_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
138 struct drm_device
*dev
= encoder
->dev
;
139 struct radeon_device
*rdev
= dev
->dev_private
;
140 struct radeon_hdmi_acr acr
= r600_hdmi_acr(clock
);
141 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
142 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
143 uint32_t offset
= dig
->afmt
->offset
;
145 WREG32(HDMI0_ACR_32_0
+ offset
, HDMI0_ACR_CTS_32(acr
.cts_32khz
));
146 WREG32(HDMI0_ACR_32_1
+ offset
, acr
.n_32khz
);
148 WREG32(HDMI0_ACR_44_0
+ offset
, HDMI0_ACR_CTS_44(acr
.cts_44_1khz
));
149 WREG32(HDMI0_ACR_44_1
+ offset
, acr
.n_44_1khz
);
151 WREG32(HDMI0_ACR_48_0
+ offset
, HDMI0_ACR_CTS_48(acr
.cts_48khz
));
152 WREG32(HDMI0_ACR_48_1
+ offset
, acr
.n_48khz
);
156 * build a HDMI Video Info Frame
158 static void r600_hdmi_update_avi_infoframe(struct drm_encoder
*encoder
,
159 void *buffer
, size_t size
)
161 struct drm_device
*dev
= encoder
->dev
;
162 struct radeon_device
*rdev
= dev
->dev_private
;
163 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
164 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
165 uint32_t offset
= dig
->afmt
->offset
;
166 uint8_t *frame
= buffer
+ 3;
167 uint8_t *header
= buffer
;
169 WREG32(HDMI0_AVI_INFO0
+ offset
,
170 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
171 WREG32(HDMI0_AVI_INFO1
+ offset
,
172 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
173 WREG32(HDMI0_AVI_INFO2
+ offset
,
174 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
175 WREG32(HDMI0_AVI_INFO3
+ offset
,
176 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
180 * build a Audio Info Frame
182 static void r600_hdmi_update_audio_infoframe(struct drm_encoder
*encoder
,
183 const void *buffer
, size_t size
)
185 struct drm_device
*dev
= encoder
->dev
;
186 struct radeon_device
*rdev
= dev
->dev_private
;
187 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
188 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
189 uint32_t offset
= dig
->afmt
->offset
;
190 const u8
*frame
= buffer
+ 3;
192 WREG32(HDMI0_AUDIO_INFO0
+ offset
,
193 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
194 WREG32(HDMI0_AUDIO_INFO1
+ offset
,
195 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x8] << 24));
199 * test if audio buffer is filled enough to start playing
201 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder
*encoder
)
203 struct drm_device
*dev
= encoder
->dev
;
204 struct radeon_device
*rdev
= dev
->dev_private
;
205 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
206 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
207 uint32_t offset
= dig
->afmt
->offset
;
209 return (RREG32(HDMI0_STATUS
+ offset
) & 0x10) != 0;
213 * have buffer status changed since last call?
215 int r600_hdmi_buffer_status_changed(struct drm_encoder
*encoder
)
217 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
218 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
221 if (!dig
->afmt
|| !dig
->afmt
->enabled
)
224 status
= r600_hdmi_is_audio_buffer_filled(encoder
);
225 result
= dig
->afmt
->last_buffer_filled_status
!= status
;
226 dig
->afmt
->last_buffer_filled_status
= status
;
232 * write the audio workaround status to the hardware
234 static void r600_hdmi_audio_workaround(struct drm_encoder
*encoder
)
236 struct drm_device
*dev
= encoder
->dev
;
237 struct radeon_device
*rdev
= dev
->dev_private
;
238 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
239 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
240 uint32_t offset
= dig
->afmt
->offset
;
241 bool hdmi_audio_workaround
= false; /* FIXME */
244 if (!hdmi_audio_workaround
||
245 r600_hdmi_is_audio_buffer_filled(encoder
))
246 value
= 0; /* disable workaround */
248 value
= HDMI0_AUDIO_TEST_EN
; /* enable workaround */
249 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL
+ offset
,
250 value
, ~HDMI0_AUDIO_TEST_EN
);
253 static void r600_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
255 struct drm_device
*dev
= encoder
->dev
;
256 struct radeon_device
*rdev
= dev
->dev_private
;
257 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
258 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
259 u32 base_rate
= 24000;
260 u32 max_ratio
= clock
/ base_rate
;
262 u32 dto_modulo
= clock
;
266 if (!dig
|| !dig
->afmt
)
269 if (max_ratio
>= 8) {
270 dto_phase
= 192 * 1000;
272 } else if (max_ratio
>= 4) {
273 dto_phase
= 96 * 1000;
275 } else if (max_ratio
>= 2) {
276 dto_phase
= 48 * 1000;
279 dto_phase
= 24 * 1000;
283 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
284 * doesn't matter which one you use. Just use the first one.
286 /* XXX two dtos; generally use dto0 for hdmi */
287 /* Express [24MHz / target pixel clock] as an exact rational
288 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
289 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
291 if (ASIC_IS_DCE32(rdev
)) {
292 if (dig
->dig_encoder
== 0) {
293 dto_cntl
= RREG32(DCCG_AUDIO_DTO0_CNTL
) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK
;
294 dto_cntl
|= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio
);
295 WREG32(DCCG_AUDIO_DTO0_CNTL
, dto_cntl
);
296 WREG32(DCCG_AUDIO_DTO0_PHASE
, dto_phase
);
297 WREG32(DCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
298 WREG32(DCCG_AUDIO_DTO_SELECT
, 0); /* select DTO0 */
300 dto_cntl
= RREG32(DCCG_AUDIO_DTO1_CNTL
) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK
;
301 dto_cntl
|= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio
);
302 WREG32(DCCG_AUDIO_DTO1_CNTL
, dto_cntl
);
303 WREG32(DCCG_AUDIO_DTO1_PHASE
, dto_phase
);
304 WREG32(DCCG_AUDIO_DTO1_MODULE
, dto_modulo
);
305 WREG32(DCCG_AUDIO_DTO_SELECT
, 1); /* select DTO1 */
308 /* according to the reg specs, this should DCE3.2 only, but in
309 * practice it seems to cover DCE2.0/3.0/3.1 as well.
311 if (dig
->dig_encoder
== 0) {
312 WREG32(DCCG_AUDIO_DTO0_PHASE
, base_rate
* 100);
313 WREG32(DCCG_AUDIO_DTO0_MODULE
, clock
* 100);
314 WREG32(DCCG_AUDIO_DTO_SELECT
, 0); /* select DTO0 */
316 WREG32(DCCG_AUDIO_DTO1_PHASE
, base_rate
* 100);
317 WREG32(DCCG_AUDIO_DTO1_MODULE
, clock
* 100);
318 WREG32(DCCG_AUDIO_DTO_SELECT
, 1); /* select DTO1 */
323 static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder
*encoder
)
325 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
326 struct drm_connector
*connector
;
327 struct radeon_connector
*radeon_connector
= NULL
;
332 /* XXX: setting this register causes hangs on some asics */
335 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
336 if (connector
->encoder
== encoder
) {
337 radeon_connector
= to_radeon_connector(connector
);
342 if (!radeon_connector
) {
343 DRM_ERROR("Couldn't find encoder's connector\n");
347 sad_count
= drm_edid_to_speaker_allocation(radeon_connector
->edid
, &sadb
);
349 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
353 /* program the speaker allocation */
354 tmp
= RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER
);
355 tmp
&= ~(DP_CONNECTION
| SPEAKER_ALLOCATION_MASK
);
357 tmp
|= HDMI_CONNECTION
;
359 tmp
|= SPEAKER_ALLOCATION(sadb
[0]);
361 tmp
|= SPEAKER_ALLOCATION(5); /* stereo */
362 WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER
, tmp
);
367 static void dce3_2_afmt_write_sad_regs(struct drm_encoder
*encoder
)
369 struct radeon_device
*rdev
= encoder
->dev
->dev_private
;
370 struct drm_connector
*connector
;
371 struct radeon_connector
*radeon_connector
= NULL
;
372 struct cea_sad
*sads
;
375 static const u16 eld_reg_to_type
[][2] = {
376 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
377 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
378 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
379 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
380 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
381 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
382 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
383 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
384 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
385 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
386 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
387 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
390 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
391 if (connector
->encoder
== encoder
) {
392 radeon_connector
= to_radeon_connector(connector
);
397 if (!radeon_connector
) {
398 DRM_ERROR("Couldn't find encoder's connector\n");
402 sad_count
= drm_edid_to_sad(radeon_connector
->edid
, &sads
);
404 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
409 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
412 int max_channels
= -1;
415 for (j
= 0; j
< sad_count
; j
++) {
416 struct cea_sad
*sad
= &sads
[j
];
418 if (sad
->format
== eld_reg_to_type
[i
][1]) {
419 if (sad
->channels
> max_channels
) {
420 value
= MAX_CHANNELS(sad
->channels
) |
421 DESCRIPTOR_BYTE_2(sad
->byte2
) |
422 SUPPORTED_FREQUENCIES(sad
->freq
);
423 max_channels
= sad
->channels
;
426 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
427 stereo_freqs
|= sad
->freq
;
433 value
|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs
);
435 WREG32(eld_reg_to_type
[i
][0], value
);
442 * update the info frames with the data from the current display mode
444 void r600_hdmi_setmode(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
)
446 struct drm_device
*dev
= encoder
->dev
;
447 struct radeon_device
*rdev
= dev
->dev_private
;
448 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
449 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
450 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
451 struct hdmi_avi_infoframe frame
;
455 if (!dig
|| !dig
->afmt
)
458 /* Silent, r600_hdmi_enable will raise WARN for us */
459 if (!dig
->afmt
->enabled
)
461 offset
= dig
->afmt
->offset
;
463 r600_audio_set_dto(encoder
, mode
->clock
);
465 WREG32(HDMI0_VBI_PACKET_CONTROL
+ offset
,
466 HDMI0_NULL_SEND
); /* send null packets when required */
468 WREG32(HDMI0_AUDIO_CRC_CONTROL
+ offset
, 0x1000);
470 if (ASIC_IS_DCE32(rdev
)) {
471 WREG32(HDMI0_AUDIO_PACKET_CONTROL
+ offset
,
472 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
473 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
474 WREG32(AFMT_AUDIO_PACKET_CONTROL
+ offset
,
475 AFMT_AUDIO_SAMPLE_SEND
| /* send audio packets */
476 AFMT_60958_CS_UPDATE
); /* allow 60958 channel status fields to be updated */
478 WREG32(HDMI0_AUDIO_PACKET_CONTROL
+ offset
,
479 HDMI0_AUDIO_SAMPLE_SEND
| /* send audio packets */
480 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
481 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
482 HDMI0_60958_CS_UPDATE
); /* allow 60958 channel status fields to be updated */
485 if (ASIC_IS_DCE32(rdev
)) {
486 dce3_2_afmt_write_speaker_allocation(encoder
);
487 dce3_2_afmt_write_sad_regs(encoder
);
490 WREG32(HDMI0_ACR_PACKET_CONTROL
+ offset
,
491 HDMI0_ACR_SOURCE
| /* select SW CTS value - XXX verify that hw CTS works on all families */
492 HDMI0_ACR_AUTO_SEND
); /* allow hw to sent ACR packets when required */
494 WREG32(HDMI0_VBI_PACKET_CONTROL
+ offset
,
495 HDMI0_NULL_SEND
| /* send null packets when required */
496 HDMI0_GC_SEND
| /* send general control packets */
497 HDMI0_GC_CONT
); /* send general control packets every frame */
499 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
500 WREG32(HDMI0_INFOFRAME_CONTROL0
+ offset
,
501 HDMI0_AVI_INFO_SEND
| /* enable AVI info frames */
502 HDMI0_AVI_INFO_CONT
| /* send AVI info frames every frame/field */
503 HDMI0_AUDIO_INFO_SEND
| /* enable audio info frames (frames won't be set until audio is enabled) */
504 HDMI0_AUDIO_INFO_CONT
); /* send audio info frames every frame/field */
506 WREG32(HDMI0_INFOFRAME_CONTROL1
+ offset
,
507 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
508 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
510 WREG32(HDMI0_GC
+ offset
, 0); /* unset HDMI0_GC_AVMUTE */
512 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
);
514 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
518 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
520 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
524 r600_hdmi_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
525 r600_hdmi_update_ACR(encoder
, mode
->clock
);
527 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
528 WREG32(HDMI0_RAMP_CONTROL0
+ offset
, 0x00FFFFFF);
529 WREG32(HDMI0_RAMP_CONTROL1
+ offset
, 0x007FFFFF);
530 WREG32(HDMI0_RAMP_CONTROL2
+ offset
, 0x00000001);
531 WREG32(HDMI0_RAMP_CONTROL3
+ offset
, 0x00000001);
533 r600_hdmi_audio_workaround(encoder
);
537 * update settings with current parameters from audio engine
539 void r600_hdmi_update_audio_settings(struct drm_encoder
*encoder
)
541 struct drm_device
*dev
= encoder
->dev
;
542 struct radeon_device
*rdev
= dev
->dev_private
;
543 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
544 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
545 struct r600_audio_pin audio
= r600_audio_status(rdev
);
546 uint8_t buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AUDIO_INFOFRAME_SIZE
];
547 struct hdmi_audio_infoframe frame
;
552 if (!dig
->afmt
|| !dig
->afmt
->enabled
)
554 offset
= dig
->afmt
->offset
;
556 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
557 r600_hdmi_is_audio_buffer_filled(encoder
) ? "playing" : "stopped",
558 audio
.channels
, audio
.rate
, audio
.bits_per_sample
);
559 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
560 (int)audio
.status_bits
, (int)audio
.category_code
);
563 if (audio
.status_bits
& AUDIO_STATUS_PROFESSIONAL
)
565 if (audio
.status_bits
& AUDIO_STATUS_NONAUDIO
)
567 if (audio
.status_bits
& AUDIO_STATUS_COPYRIGHT
)
569 if (audio
.status_bits
& AUDIO_STATUS_EMPHASIS
)
572 iec
|= HDMI0_60958_CS_CATEGORY_CODE(audio
.category_code
);
574 switch (audio
.rate
) {
576 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
579 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
582 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
585 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
588 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
591 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
594 iec
|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
598 WREG32(HDMI0_60958_0
+ offset
, iec
);
601 switch (audio
.bits_per_sample
) {
603 iec
|= HDMI0_60958_CS_WORD_LENGTH(0x2);
606 iec
|= HDMI0_60958_CS_WORD_LENGTH(0x3);
609 iec
|= HDMI0_60958_CS_WORD_LENGTH(0xb);
612 if (audio
.status_bits
& AUDIO_STATUS_V
)
614 WREG32_P(HDMI0_60958_1
+ offset
, iec
, ~0x5000f);
616 err
= hdmi_audio_infoframe_init(&frame
);
618 DRM_ERROR("failed to setup audio infoframe\n");
622 frame
.channels
= audio
.channels
;
624 err
= hdmi_audio_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
626 DRM_ERROR("failed to pack audio infoframe\n");
630 r600_hdmi_update_audio_infoframe(encoder
, buffer
, sizeof(buffer
));
631 r600_hdmi_audio_workaround(encoder
);
635 * enable the HDMI engine
637 void r600_hdmi_enable(struct drm_encoder
*encoder
, bool enable
)
639 struct drm_device
*dev
= encoder
->dev
;
640 struct radeon_device
*rdev
= dev
->dev_private
;
641 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
642 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
643 u32 hdmi
= HDMI0_ERROR_ACK
;
645 if (!dig
|| !dig
->afmt
)
648 /* Silent, r600_hdmi_enable will raise WARN for us */
649 if (enable
&& dig
->afmt
->enabled
)
651 if (!enable
&& !dig
->afmt
->enabled
)
655 dig
->afmt
->pin
= r600_audio_get_pin(rdev
);
657 dig
->afmt
->pin
= NULL
;
659 /* Older chipsets require setting HDMI and routing manually */
660 if (!ASIC_IS_DCE3(rdev
)) {
662 hdmi
|= HDMI0_ENABLE
;
663 switch (radeon_encoder
->encoder_id
) {
664 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
666 WREG32_OR(AVIVO_TMDSA_CNTL
, AVIVO_TMDSA_CNTL_HDMI_EN
);
667 hdmi
|= HDMI0_STREAM(HDMI0_STREAM_TMDSA
);
669 WREG32_AND(AVIVO_TMDSA_CNTL
, ~AVIVO_TMDSA_CNTL_HDMI_EN
);
672 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
674 WREG32_OR(AVIVO_LVTMA_CNTL
, AVIVO_LVTMA_CNTL_HDMI_EN
);
675 hdmi
|= HDMI0_STREAM(HDMI0_STREAM_LVTMA
);
677 WREG32_AND(AVIVO_LVTMA_CNTL
, ~AVIVO_LVTMA_CNTL_HDMI_EN
);
680 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
682 WREG32_OR(DDIA_CNTL
, DDIA_HDMI_EN
);
683 hdmi
|= HDMI0_STREAM(HDMI0_STREAM_DDIA
);
685 WREG32_AND(DDIA_CNTL
, ~DDIA_HDMI_EN
);
688 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
690 hdmi
|= HDMI0_STREAM(HDMI0_STREAM_DVOA
);
693 dev_err(rdev
->dev
, "Invalid encoder for HDMI: 0x%X\n",
694 radeon_encoder
->encoder_id
);
697 WREG32(HDMI0_CONTROL
+ dig
->afmt
->offset
, hdmi
);
700 if (rdev
->irq
.installed
) {
701 /* if irq is available use it */
702 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
704 radeon_irq_kms_enable_afmt(rdev
, dig
->afmt
->id
);
706 radeon_irq_kms_disable_afmt(rdev
, dig
->afmt
->id
);
709 dig
->afmt
->enabled
= enable
;
711 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
712 enable
? "En" : "Dis", dig
->afmt
->offset
, radeon_encoder
->encoder_id
);