?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_display.c
blobd680608f6f5bc9a80e879b4f24769f8a9ffb1e8c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_edid.h>
36
37 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
38 {
39 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40 struct drm_device *dev = crtc->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 int i;
43
44 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
45 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
46
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
50
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
54
55 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
56 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
57 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
58
59 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
60 for (i = 0; i < 256; i++) {
61 WREG32(AVIVO_DC_LUT_30_COLOR,
62 (radeon_crtc->lut_r[i] << 20) |
63 (radeon_crtc->lut_g[i] << 10) |
64 (radeon_crtc->lut_b[i] << 0));
65 }
66
67 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
68 }
69
70 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
71 {
72 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
73 struct drm_device *dev = crtc->dev;
74 struct radeon_device *rdev = dev->dev_private;
75 int i;
76
77 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
78 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
79
80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
83
84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
87
88 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
89 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
90
91 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
92 for (i = 0; i < 256; i++) {
93 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
94 (radeon_crtc->lut_r[i] << 20) |
95 (radeon_crtc->lut_g[i] << 10) |
96 (radeon_crtc->lut_b[i] << 0));
97 }
98 }
99
100 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
101 {
102 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
103 struct drm_device *dev = crtc->dev;
104 struct radeon_device *rdev = dev->dev_private;
105 int i;
106
107 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
108
109 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
110 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
111 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
112 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
113 NI_GRPH_PRESCALE_BYPASS);
114 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
115 NI_OVL_PRESCALE_BYPASS);
116 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
117 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
118 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
119
120 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
121
122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
125
126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
129
130 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
131 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
132
133 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
134 for (i = 0; i < 256; i++) {
135 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
136 (radeon_crtc->lut_r[i] << 20) |
137 (radeon_crtc->lut_g[i] << 10) |
138 (radeon_crtc->lut_b[i] << 0));
139 }
140
141 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
142 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
143 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
146 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
147 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
148 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
149 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
150 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
151 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
152 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
153 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
154 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
155 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
156 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
157 if (ASIC_IS_DCE8(rdev)) {
158 /* XXX this only needs to be programmed once per crtc at startup,
159 * not sure where the best place for it is
160 */
161 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
162 CIK_CURSOR_ALPHA_BLND_ENA);
163 }
164 }
165
166 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
167 {
168 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
169 struct drm_device *dev = crtc->dev;
170 struct radeon_device *rdev = dev->dev_private;
171 int i;
172 uint32_t dac2_cntl;
173
174 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
175 if (radeon_crtc->crtc_id == 0)
176 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
177 else
178 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
179 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
180
181 WREG8(RADEON_PALETTE_INDEX, 0);
182 for (i = 0; i < 256; i++) {
183 WREG32(RADEON_PALETTE_30_DATA,
184 (radeon_crtc->lut_r[i] << 20) |
185 (radeon_crtc->lut_g[i] << 10) |
186 (radeon_crtc->lut_b[i] << 0));
187 }
188 }
189
190 void radeon_crtc_load_lut(struct drm_crtc *crtc)
191 {
192 struct drm_device *dev = crtc->dev;
193 struct radeon_device *rdev = dev->dev_private;
194
195 if (!crtc->enabled)
196 return;
197
198 if (ASIC_IS_DCE5(rdev))
199 dce5_crtc_load_lut(crtc);
200 else if (ASIC_IS_DCE4(rdev))
201 dce4_crtc_load_lut(crtc);
202 else if (ASIC_IS_AVIVO(rdev))
203 avivo_crtc_load_lut(crtc);
204 else
205 legacy_crtc_load_lut(crtc);
206 }
207
208 /** Sets the color ramps on behalf of fbcon */
209 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
210 u16 blue, int regno)
211 {
212 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
213
214 radeon_crtc->lut_r[regno] = red >> 6;
215 radeon_crtc->lut_g[regno] = green >> 6;
216 radeon_crtc->lut_b[regno] = blue >> 6;
217 }
218
219 /** Gets the color ramps on behalf of fbcon */
220 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
221 u16 *blue, int regno)
222 {
223 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
224
225 *red = radeon_crtc->lut_r[regno] << 6;
226 *green = radeon_crtc->lut_g[regno] << 6;
227 *blue = radeon_crtc->lut_b[regno] << 6;
228 }
229
230 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
231 u16 *blue, uint32_t start, uint32_t size)
232 {
233 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
234 int end = (start + size > 256) ? 256 : start + size, i;
235
236 /* userspace palettes are always correct as is */
237 for (i = start; i < end; i++) {
238 radeon_crtc->lut_r[i] = red[i] >> 6;
239 radeon_crtc->lut_g[i] = green[i] >> 6;
240 radeon_crtc->lut_b[i] = blue[i] >> 6;
241 }
242 radeon_crtc_load_lut(crtc);
243 }
244
245 static void radeon_crtc_destroy(struct drm_crtc *crtc)
246 {
247 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
248
249 drm_crtc_cleanup(crtc);
250 kfree(radeon_crtc);
251 }
252
253 /*
254 * Handle unpin events outside the interrupt handler proper.
255 */
256 static void radeon_unpin_work_func(struct work_struct *__work)
257 {
258 struct radeon_unpin_work *work =
259 container_of(__work, struct radeon_unpin_work, work);
260 int r;
261
262 /* unpin of the old buffer */
263 r = radeon_bo_reserve(work->old_rbo, false);
264 if (likely(r == 0)) {
265 r = radeon_bo_unpin(work->old_rbo);
266 if (unlikely(r != 0)) {
267 DRM_ERROR("failed to unpin buffer after flip\n");
268 }
269 radeon_bo_unreserve(work->old_rbo);
270 } else
271 DRM_ERROR("failed to reserve buffer after flip\n");
272
273 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
274 kfree(work);
275 }
276
277 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
278 {
279 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
280 struct radeon_unpin_work *work;
281 unsigned long flags;
282 u32 update_pending;
283 int vpos, hpos;
284
285 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
286 work = radeon_crtc->unpin_work;
287 if (work == NULL ||
288 (work->fence && !radeon_fence_signaled(work->fence))) {
289 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
290 return;
291 }
292 /* New pageflip, or just completion of a previous one? */
293 if (!radeon_crtc->deferred_flip_completion) {
294 /* do the flip (mmio) */
295 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
296 } else {
297 /* This is just a completion of a flip queued in crtc
298 * at last invocation. Make sure we go directly to
299 * completion routine.
300 */
301 update_pending = 0;
302 radeon_crtc->deferred_flip_completion = 0;
303 }
304
305 /* Has the pageflip already completed in crtc, or is it certain
306 * to complete in this vblank?
307 */
308 if (update_pending &&
309 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
310 &vpos, &hpos, NULL, NULL)) &&
311 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
312 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
313 /* crtc didn't flip in this target vblank interval,
314 * but flip is pending in crtc. Based on the current
315 * scanout position we know that the current frame is
316 * (nearly) complete and the flip will (likely)
317 * complete before the start of the next frame.
318 */
319 update_pending = 0;
320 }
321 if (update_pending) {
322 /* crtc didn't flip in this target vblank interval,
323 * but flip is pending in crtc. It will complete it
324 * in next vblank interval, so complete the flip at
325 * next vblank irq.
326 */
327 radeon_crtc->deferred_flip_completion = 1;
328 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
329 return;
330 }
331
332 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
333 radeon_crtc->unpin_work = NULL;
334
335 /* wakeup userspace */
336 if (work->event)
337 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
338
339 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
340
341 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
342 radeon_fence_unref(&work->fence);
343 radeon_post_page_flip(work->rdev, work->crtc_id);
344 schedule_work(&work->work);
345 }
346
347 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
348 struct drm_framebuffer *fb,
349 struct drm_pending_vblank_event *event,
350 uint32_t page_flip_flags)
351 {
352 struct drm_device *dev = crtc->dev;
353 struct radeon_device *rdev = dev->dev_private;
354 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
355 struct radeon_framebuffer *old_radeon_fb;
356 struct radeon_framebuffer *new_radeon_fb;
357 struct drm_gem_object *obj;
358 struct radeon_bo *rbo;
359 struct radeon_unpin_work *work;
360 unsigned long flags;
361 u32 tiling_flags, pitch_pixels;
362 u64 base;
363 int r;
364
365 work = kzalloc(sizeof *work, GFP_KERNEL);
366 if (work == NULL)
367 return -ENOMEM;
368
369 work->event = event;
370 work->rdev = rdev;
371 work->crtc_id = radeon_crtc->crtc_id;
372 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
373 new_radeon_fb = to_radeon_framebuffer(fb);
374 /* schedule unpin of the old buffer */
375 obj = old_radeon_fb->obj;
376 /* take a reference to the old object */
377 drm_gem_object_reference(obj);
378 rbo = gem_to_radeon_bo(obj);
379 work->old_rbo = rbo;
380 obj = new_radeon_fb->obj;
381 rbo = gem_to_radeon_bo(obj);
382
383 spin_lock(&rbo->tbo.bdev->fence_lock);
384 if (rbo->tbo.sync_obj)
385 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
386 spin_unlock(&rbo->tbo.bdev->fence_lock);
387
388 INIT_WORK(&work->work, radeon_unpin_work_func);
389
390 /* We borrow the event spin lock for protecting unpin_work */
391 spin_lock_irqsave(&dev->event_lock, flags);
392 if (radeon_crtc->unpin_work) {
393 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
394 r = -EBUSY;
395 goto unlock_free;
396 }
397 radeon_crtc->unpin_work = work;
398 radeon_crtc->deferred_flip_completion = 0;
399 spin_unlock_irqrestore(&dev->event_lock, flags);
400
401 /* pin the new buffer */
402 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
403 work->old_rbo, rbo);
404
405 r = radeon_bo_reserve(rbo, false);
406 if (unlikely(r != 0)) {
407 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
408 goto pflip_cleanup;
409 }
410 /* Only 27 bit offset for legacy CRTC */
411 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
412 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
413 if (unlikely(r != 0)) {
414 radeon_bo_unreserve(rbo);
415 r = -EINVAL;
416 DRM_ERROR("failed to pin new rbo buffer before flip\n");
417 goto pflip_cleanup;
418 }
419 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
420 radeon_bo_unreserve(rbo);
421
422 if (!ASIC_IS_AVIVO(rdev)) {
423 /* crtc offset is from display base addr not FB location */
424 base -= radeon_crtc->legacy_display_base_addr;
425 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
426
427 if (tiling_flags & RADEON_TILING_MACRO) {
428 if (ASIC_IS_R300(rdev)) {
429 base &= ~0x7ff;
430 } else {
431 int byteshift = fb->bits_per_pixel >> 4;
432 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
433 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
434 }
435 } else {
436 int offset = crtc->y * pitch_pixels + crtc->x;
437 switch (fb->bits_per_pixel) {
438 case 8:
439 default:
440 offset *= 1;
441 break;
442 case 15:
443 case 16:
444 offset *= 2;
445 break;
446 case 24:
447 offset *= 3;
448 break;
449 case 32:
450 offset *= 4;
451 break;
452 }
453 base += offset;
454 }
455 base &= ~7;
456 }
457
458 spin_lock_irqsave(&dev->event_lock, flags);
459 work->new_crtc_base = base;
460 spin_unlock_irqrestore(&dev->event_lock, flags);
461
462 /* update crtc fb */
463 crtc->fb = fb;
464
465 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
466 if (r) {
467 DRM_ERROR("failed to get vblank before flip\n");
468 goto pflip_cleanup1;
469 }
470
471 /* set the proper interrupt */
472 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
473
474 return 0;
475
476 pflip_cleanup1:
477 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
478 DRM_ERROR("failed to reserve new rbo in error path\n");
479 goto pflip_cleanup;
480 }
481 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
482 DRM_ERROR("failed to unpin new rbo in error path\n");
483 }
484 radeon_bo_unreserve(rbo);
485
486 pflip_cleanup:
487 spin_lock_irqsave(&dev->event_lock, flags);
488 radeon_crtc->unpin_work = NULL;
489 unlock_free:
490 spin_unlock_irqrestore(&dev->event_lock, flags);
491 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
492 radeon_fence_unref(&work->fence);
493 kfree(work);
494
495 return r;
496 }
497
498 static int
499 radeon_crtc_set_config(struct drm_mode_set *set)
500 {
501 struct drm_device *dev;
502 struct radeon_device *rdev;
503 struct drm_crtc *crtc;
504 bool active = false;
505 int ret;
506
507 if (!set || !set->crtc)
508 return -EINVAL;
509
510 dev = set->crtc->dev;
511
512 ret = pm_runtime_get_sync(dev->dev);
513 if (ret < 0)
514 return ret;
515
516 ret = drm_crtc_helper_set_config(set);
517
518 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
519 if (crtc->enabled)
520 active = true;
521
522 pm_runtime_mark_last_busy(dev->dev);
523
524 rdev = dev->dev_private;
525 /* if we have active crtcs and we don't have a power ref,
526 take the current one */
527 if (active && !rdev->have_disp_power_ref) {
528 rdev->have_disp_power_ref = true;
529 return ret;
530 }
531 /* if we have no active crtcs, then drop the power ref
532 we got before */
533 if (!active && rdev->have_disp_power_ref) {
534 pm_runtime_put_autosuspend(dev->dev);
535 rdev->have_disp_power_ref = false;
536 }
537
538 /* drop the power reference we got coming in here */
539 pm_runtime_put_autosuspend(dev->dev);
540 return ret;
541 }
542 static const struct drm_crtc_funcs radeon_crtc_funcs = {
543 .cursor_set = radeon_crtc_cursor_set,
544 .cursor_move = radeon_crtc_cursor_move,
545 .gamma_set = radeon_crtc_gamma_set,
546 .set_config = radeon_crtc_set_config,
547 .destroy = radeon_crtc_destroy,
548 .page_flip = radeon_crtc_page_flip,
549 };
550
551 static void radeon_crtc_init(struct drm_device *dev, int index)
552 {
553 struct radeon_device *rdev = dev->dev_private;
554 struct radeon_crtc *radeon_crtc;
555 int i;
556
557 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
558 if (radeon_crtc == NULL)
559 return;
560
561 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
562
563 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
564 radeon_crtc->crtc_id = index;
565 rdev->mode_info.crtcs[index] = radeon_crtc;
566
567 if (rdev->family >= CHIP_BONAIRE) {
568 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
569 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
570 } else {
571 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
572 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
573 }
574
575 #if 0
576 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
577 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
578 radeon_crtc->mode_set.num_connectors = 0;
579 #endif
580
581 for (i = 0; i < 256; i++) {
582 radeon_crtc->lut_r[i] = i << 2;
583 radeon_crtc->lut_g[i] = i << 2;
584 radeon_crtc->lut_b[i] = i << 2;
585 }
586
587 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
588 radeon_atombios_init_crtc(dev, radeon_crtc);
589 else
590 radeon_legacy_init_crtc(dev, radeon_crtc);
591 }
592
593 static const char *encoder_names[38] = {
594 "NONE",
595 "INTERNAL_LVDS",
596 "INTERNAL_TMDS1",
597 "INTERNAL_TMDS2",
598 "INTERNAL_DAC1",
599 "INTERNAL_DAC2",
600 "INTERNAL_SDVOA",
601 "INTERNAL_SDVOB",
602 "SI170B",
603 "CH7303",
604 "CH7301",
605 "INTERNAL_DVO1",
606 "EXTERNAL_SDVOA",
607 "EXTERNAL_SDVOB",
608 "TITFP513",
609 "INTERNAL_LVTM1",
610 "VT1623",
611 "HDMI_SI1930",
612 "HDMI_INTERNAL",
613 "INTERNAL_KLDSCP_TMDS1",
614 "INTERNAL_KLDSCP_DVO1",
615 "INTERNAL_KLDSCP_DAC1",
616 "INTERNAL_KLDSCP_DAC2",
617 "SI178",
618 "MVPU_FPGA",
619 "INTERNAL_DDI",
620 "VT1625",
621 "HDMI_SI1932",
622 "DP_AN9801",
623 "DP_DP501",
624 "INTERNAL_UNIPHY",
625 "INTERNAL_KLDSCP_LVTMA",
626 "INTERNAL_UNIPHY1",
627 "INTERNAL_UNIPHY2",
628 "NUTMEG",
629 "TRAVIS",
630 "INTERNAL_VCE",
631 "INTERNAL_UNIPHY3",
632 };
633
634 static const char *hpd_names[6] = {
635 "HPD1",
636 "HPD2",
637 "HPD3",
638 "HPD4",
639 "HPD5",
640 "HPD6",
641 };
642
643 static void radeon_print_display_setup(struct drm_device *dev)
644 {
645 struct drm_connector *connector;
646 struct radeon_connector *radeon_connector;
647 struct drm_encoder *encoder;
648 struct radeon_encoder *radeon_encoder;
649 uint32_t devices;
650 int i = 0;
651
652 DRM_INFO("Radeon Display Connectors\n");
653 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
654 radeon_connector = to_radeon_connector(connector);
655 DRM_INFO("Connector %d:\n", i);
656 DRM_INFO(" %s\n", drm_get_connector_name(connector));
657 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
658 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
659 if (radeon_connector->ddc_bus) {
660 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
661 radeon_connector->ddc_bus->rec.mask_clk_reg,
662 radeon_connector->ddc_bus->rec.mask_data_reg,
663 radeon_connector->ddc_bus->rec.a_clk_reg,
664 radeon_connector->ddc_bus->rec.a_data_reg,
665 radeon_connector->ddc_bus->rec.en_clk_reg,
666 radeon_connector->ddc_bus->rec.en_data_reg,
667 radeon_connector->ddc_bus->rec.y_clk_reg,
668 radeon_connector->ddc_bus->rec.y_data_reg);
669 if (radeon_connector->router.ddc_valid)
670 DRM_INFO(" DDC Router 0x%x/0x%x\n",
671 radeon_connector->router.ddc_mux_control_pin,
672 radeon_connector->router.ddc_mux_state);
673 if (radeon_connector->router.cd_valid)
674 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
675 radeon_connector->router.cd_mux_control_pin,
676 radeon_connector->router.cd_mux_state);
677 } else {
678 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
679 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
680 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
681 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
682 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
683 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
684 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
685 }
686 DRM_INFO(" Encoders:\n");
687 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
688 radeon_encoder = to_radeon_encoder(encoder);
689 devices = radeon_encoder->devices & radeon_connector->devices;
690 if (devices) {
691 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
692 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
693 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
694 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
695 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
696 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
697 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
698 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
699 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
700 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
701 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
702 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
703 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
704 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
705 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
706 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
707 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
708 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
709 if (devices & ATOM_DEVICE_TV1_SUPPORT)
710 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
711 if (devices & ATOM_DEVICE_CV_SUPPORT)
712 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
713 }
714 }
715 i++;
716 }
717 }
718
719 static bool radeon_setup_enc_conn(struct drm_device *dev)
720 {
721 struct radeon_device *rdev = dev->dev_private;
722 bool ret = false;
723
724 if (rdev->bios) {
725 if (rdev->is_atom_bios) {
726 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
727 if (ret == false)
728 ret = radeon_get_atom_connector_info_from_object_table(dev);
729 } else {
730 ret = radeon_get_legacy_connector_info_from_bios(dev);
731 if (ret == false)
732 ret = radeon_get_legacy_connector_info_from_table(dev);
733 }
734 } else {
735 if (!ASIC_IS_AVIVO(rdev))
736 ret = radeon_get_legacy_connector_info_from_table(dev);
737 }
738 if (ret) {
739 radeon_setup_encoder_clones(dev);
740 radeon_print_display_setup(dev);
741 }
742
743 return ret;
744 }
745
746 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
747 {
748 struct drm_device *dev = radeon_connector->base.dev;
749 struct radeon_device *rdev = dev->dev_private;
750 int ret = 0;
751
752 /* on hw with routers, select right port */
753 if (radeon_connector->router.ddc_valid)
754 radeon_router_select_ddc_port(radeon_connector);
755
756 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
757 ENCODER_OBJECT_ID_NONE) {
758 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
759
760 if (dig->dp_i2c_bus)
761 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
762 &dig->dp_i2c_bus->adapter);
763 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
764 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
765 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
766
767 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
768 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
769 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
770 &dig->dp_i2c_bus->adapter);
771 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
772 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
773 &radeon_connector->ddc_bus->adapter);
774 } else {
775 if (radeon_connector->ddc_bus && !radeon_connector->edid)
776 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
777 &radeon_connector->ddc_bus->adapter);
778 }
779
780 if (!radeon_connector->edid) {
781 if (rdev->is_atom_bios) {
782 /* some laptops provide a hardcoded edid in rom for LCDs */
783 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
784 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
785 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
786 } else
787 /* some servers provide a hardcoded edid in rom for KVMs */
788 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
789 }
790 if (radeon_connector->edid) {
791 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
792 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
793 return ret;
794 }
795 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
796 return 0;
797 }
798
799 /* avivo */
800 static void avivo_get_fb_div(struct radeon_pll *pll,
801 u32 target_clock,
802 u32 post_div,
803 u32 ref_div,
804 u32 *fb_div,
805 u32 *frac_fb_div)
806 {
807 u32 tmp = post_div * ref_div;
808
809 tmp *= target_clock;
810 *fb_div = tmp / pll->reference_freq;
811 *frac_fb_div = tmp % pll->reference_freq;
812
813 if (*fb_div > pll->max_feedback_div)
814 *fb_div = pll->max_feedback_div;
815 else if (*fb_div < pll->min_feedback_div)
816 *fb_div = pll->min_feedback_div;
817 }
818
819 static u32 avivo_get_post_div(struct radeon_pll *pll,
820 u32 target_clock)
821 {
822 u32 vco, post_div, tmp;
823
824 if (pll->flags & RADEON_PLL_USE_POST_DIV)
825 return pll->post_div;
826
827 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
828 if (pll->flags & RADEON_PLL_IS_LCD)
829 vco = pll->lcd_pll_out_min;
830 else
831 vco = pll->pll_out_min;
832 } else {
833 if (pll->flags & RADEON_PLL_IS_LCD)
834 vco = pll->lcd_pll_out_max;
835 else
836 vco = pll->pll_out_max;
837 }
838
839 post_div = vco / target_clock;
840 tmp = vco % target_clock;
841
842 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
843 if (tmp)
844 post_div++;
845 } else {
846 if (!tmp)
847 post_div--;
848 }
849
850 if (post_div > pll->max_post_div)
851 post_div = pll->max_post_div;
852 else if (post_div < pll->min_post_div)
853 post_div = pll->min_post_div;
854
855 return post_div;
856 }
857
858 #define MAX_TOLERANCE 10
859
860 void radeon_compute_pll_avivo(struct radeon_pll *pll,
861 u32 freq,
862 u32 *dot_clock_p,
863 u32 *fb_div_p,
864 u32 *frac_fb_div_p,
865 u32 *ref_div_p,
866 u32 *post_div_p)
867 {
868 u32 target_clock = freq / 10;
869 u32 post_div = avivo_get_post_div(pll, target_clock);
870 u32 ref_div = pll->min_ref_div;
871 u32 fb_div = 0, frac_fb_div = 0, tmp;
872
873 if (pll->flags & RADEON_PLL_USE_REF_DIV)
874 ref_div = pll->reference_div;
875
876 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
877 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
878 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
879 if (frac_fb_div >= 5) {
880 frac_fb_div -= 5;
881 frac_fb_div = frac_fb_div / 10;
882 frac_fb_div++;
883 }
884 if (frac_fb_div >= 10) {
885 fb_div++;
886 frac_fb_div = 0;
887 }
888 } else {
889 while (ref_div <= pll->max_ref_div) {
890 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
891 &fb_div, &frac_fb_div);
892 if (frac_fb_div >= (pll->reference_freq / 2))
893 fb_div++;
894 frac_fb_div = 0;
895 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
896 tmp = (tmp * 10000) / target_clock;
897
898 if (tmp > (10000 + MAX_TOLERANCE))
899 ref_div++;
900 else if (tmp >= (10000 - MAX_TOLERANCE))
901 break;
902 else
903 ref_div++;
904 }
905 }
906
907 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
908 (ref_div * post_div * 10);
909 *fb_div_p = fb_div;
910 *frac_fb_div_p = frac_fb_div;
911 *ref_div_p = ref_div;
912 *post_div_p = post_div;
913 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
914 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
915 }
916
917 /* pre-avivo */
918 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
919 {
920 uint64_t mod;
921
922 n += d / 2;
923
924 mod = do_div(n, d);
925 return n;
926 }
927
928 void radeon_compute_pll_legacy(struct radeon_pll *pll,
929 uint64_t freq,
930 uint32_t *dot_clock_p,
931 uint32_t *fb_div_p,
932 uint32_t *frac_fb_div_p,
933 uint32_t *ref_div_p,
934 uint32_t *post_div_p)
935 {
936 uint32_t min_ref_div = pll->min_ref_div;
937 uint32_t max_ref_div = pll->max_ref_div;
938 uint32_t min_post_div = pll->min_post_div;
939 uint32_t max_post_div = pll->max_post_div;
940 uint32_t min_fractional_feed_div = 0;
941 uint32_t max_fractional_feed_div = 0;
942 uint32_t best_vco = pll->best_vco;
943 uint32_t best_post_div = 1;
944 uint32_t best_ref_div = 1;
945 uint32_t best_feedback_div = 1;
946 uint32_t best_frac_feedback_div = 0;
947 uint32_t best_freq = -1;
948 uint32_t best_error = 0xffffffff;
949 uint32_t best_vco_diff = 1;
950 uint32_t post_div;
951 u32 pll_out_min, pll_out_max;
952
953 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
954 freq = freq * 1000;
955
956 if (pll->flags & RADEON_PLL_IS_LCD) {
957 pll_out_min = pll->lcd_pll_out_min;
958 pll_out_max = pll->lcd_pll_out_max;
959 } else {
960 pll_out_min = pll->pll_out_min;
961 pll_out_max = pll->pll_out_max;
962 }
963
964 if (pll_out_min > 64800)
965 pll_out_min = 64800;
966
967 if (pll->flags & RADEON_PLL_USE_REF_DIV)
968 min_ref_div = max_ref_div = pll->reference_div;
969 else {
970 while (min_ref_div < max_ref_div-1) {
971 uint32_t mid = (min_ref_div + max_ref_div) / 2;
972 uint32_t pll_in = pll->reference_freq / mid;
973 if (pll_in < pll->pll_in_min)
974 max_ref_div = mid;
975 else if (pll_in > pll->pll_in_max)
976 min_ref_div = mid;
977 else
978 break;
979 }
980 }
981
982 if (pll->flags & RADEON_PLL_USE_POST_DIV)
983 min_post_div = max_post_div = pll->post_div;
984
985 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
986 min_fractional_feed_div = pll->min_frac_feedback_div;
987 max_fractional_feed_div = pll->max_frac_feedback_div;
988 }
989
990 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
991 uint32_t ref_div;
992
993 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
994 continue;
995
996 /* legacy radeons only have a few post_divs */
997 if (pll->flags & RADEON_PLL_LEGACY) {
998 if ((post_div == 5) ||
999 (post_div == 7) ||
1000 (post_div == 9) ||
1001 (post_div == 10) ||
1002 (post_div == 11) ||
1003 (post_div == 13) ||
1004 (post_div == 14) ||
1005 (post_div == 15))
1006 continue;
1007 }
1008
1009 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1010 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1011 uint32_t pll_in = pll->reference_freq / ref_div;
1012 uint32_t min_feed_div = pll->min_feedback_div;
1013 uint32_t max_feed_div = pll->max_feedback_div + 1;
1014
1015 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1016 continue;
1017
1018 while (min_feed_div < max_feed_div) {
1019 uint32_t vco;
1020 uint32_t min_frac_feed_div = min_fractional_feed_div;
1021 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1022 uint32_t frac_feedback_div;
1023 uint64_t tmp;
1024
1025 feedback_div = (min_feed_div + max_feed_div) / 2;
1026
1027 tmp = (uint64_t)pll->reference_freq * feedback_div;
1028 vco = radeon_div(tmp, ref_div);
1029
1030 if (vco < pll_out_min) {
1031 min_feed_div = feedback_div + 1;
1032 continue;
1033 } else if (vco > pll_out_max) {
1034 max_feed_div = feedback_div;
1035 continue;
1036 }
1037
1038 while (min_frac_feed_div < max_frac_feed_div) {
1039 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1040 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1041 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1042 current_freq = radeon_div(tmp, ref_div * post_div);
1043
1044 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1045 if (freq < current_freq)
1046 error = 0xffffffff;
1047 else
1048 error = freq - current_freq;
1049 } else
1050 error = abs(current_freq - freq);
1051 vco_diff = abs(vco - best_vco);
1052
1053 if ((best_vco == 0 && error < best_error) ||
1054 (best_vco != 0 &&
1055 ((best_error > 100 && error < best_error - 100) ||
1056 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1057 best_post_div = post_div;
1058 best_ref_div = ref_div;
1059 best_feedback_div = feedback_div;
1060 best_frac_feedback_div = frac_feedback_div;
1061 best_freq = current_freq;
1062 best_error = error;
1063 best_vco_diff = vco_diff;
1064 } else if (current_freq == freq) {
1065 if (best_freq == -1) {
1066 best_post_div = post_div;
1067 best_ref_div = ref_div;
1068 best_feedback_div = feedback_div;
1069 best_frac_feedback_div = frac_feedback_div;
1070 best_freq = current_freq;
1071 best_error = error;
1072 best_vco_diff = vco_diff;
1073 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1074 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1075 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1076 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1077 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1078 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1079 best_post_div = post_div;
1080 best_ref_div = ref_div;
1081 best_feedback_div = feedback_div;
1082 best_frac_feedback_div = frac_feedback_div;
1083 best_freq = current_freq;
1084 best_error = error;
1085 best_vco_diff = vco_diff;
1086 }
1087 }
1088 if (current_freq < freq)
1089 min_frac_feed_div = frac_feedback_div + 1;
1090 else
1091 max_frac_feed_div = frac_feedback_div;
1092 }
1093 if (current_freq < freq)
1094 min_feed_div = feedback_div + 1;
1095 else
1096 max_feed_div = feedback_div;
1097 }
1098 }
1099 }
1100
1101 *dot_clock_p = best_freq / 10000;
1102 *fb_div_p = best_feedback_div;
1103 *frac_fb_div_p = best_frac_feedback_div;
1104 *ref_div_p = best_ref_div;
1105 *post_div_p = best_post_div;
1106 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1107 (long long)freq,
1108 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1109 best_ref_div, best_post_div);
1110
1111 }
1112
1113 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1114 {
1115 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1116
1117 if (radeon_fb->obj) {
1118 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1119 }
1120 drm_framebuffer_cleanup(fb);
1121 kfree(radeon_fb);
1122 }
1123
1124 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1125 struct drm_file *file_priv,
1126 unsigned int *handle)
1127 {
1128 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1129
1130 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1131 }
1132
1133 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1134 .destroy = radeon_user_framebuffer_destroy,
1135 .create_handle = radeon_user_framebuffer_create_handle,
1136 };
1137
1138 int
1139 radeon_framebuffer_init(struct drm_device *dev,
1140 struct radeon_framebuffer *rfb,
1141 struct drm_mode_fb_cmd2 *mode_cmd,
1142 struct drm_gem_object *obj)
1143 {
1144 int ret;
1145 rfb->obj = obj;
1146 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1147 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1148 if (ret) {
1149 rfb->obj = NULL;
1150 return ret;
1151 }
1152 return 0;
1153 }
1154
1155 static struct drm_framebuffer *
1156 radeon_user_framebuffer_create(struct drm_device *dev,
1157 struct drm_file *file_priv,
1158 struct drm_mode_fb_cmd2 *mode_cmd)
1159 {
1160 struct drm_gem_object *obj;
1161 struct radeon_framebuffer *radeon_fb;
1162 int ret;
1163
1164 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1165 if (obj == NULL) {
1166 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1167 "can't create framebuffer\n", mode_cmd->handles[0]);
1168 return ERR_PTR(-ENOENT);
1169 }
1170
1171 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1172 if (radeon_fb == NULL) {
1173 drm_gem_object_unreference_unlocked(obj);
1174 return ERR_PTR(-ENOMEM);
1175 }
1176
1177 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1178 if (ret) {
1179 kfree(radeon_fb);
1180 drm_gem_object_unreference_unlocked(obj);
1181 return ERR_PTR(ret);
1182 }
1183
1184 return &radeon_fb->base;
1185 }
1186
1187 static void radeon_output_poll_changed(struct drm_device *dev)
1188 {
1189 struct radeon_device *rdev = dev->dev_private;
1190 radeon_fb_output_poll_changed(rdev);
1191 }
1192
1193 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1194 .fb_create = radeon_user_framebuffer_create,
1195 .output_poll_changed = radeon_output_poll_changed
1196 };
1197
1198 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1199 { { 0, "driver" },
1200 { 1, "bios" },
1201 };
1202
1203 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1204 { { TV_STD_NTSC, "ntsc" },
1205 { TV_STD_PAL, "pal" },
1206 { TV_STD_PAL_M, "pal-m" },
1207 { TV_STD_PAL_60, "pal-60" },
1208 { TV_STD_NTSC_J, "ntsc-j" },
1209 { TV_STD_SCART_PAL, "scart-pal" },
1210 { TV_STD_PAL_CN, "pal-cn" },
1211 { TV_STD_SECAM, "secam" },
1212 };
1213
1214 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1215 { { UNDERSCAN_OFF, "off" },
1216 { UNDERSCAN_ON, "on" },
1217 { UNDERSCAN_AUTO, "auto" },
1218 };
1219
1220 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1221 { { RADEON_AUDIO_DISABLE, "off" },
1222 { RADEON_AUDIO_ENABLE, "on" },
1223 { RADEON_AUDIO_AUTO, "auto" },
1224 };
1225
1226 /* XXX support different dither options? spatial, temporal, both, etc. */
1227 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1228 { { RADEON_FMT_DITHER_DISABLE, "off" },
1229 { RADEON_FMT_DITHER_ENABLE, "on" },
1230 };
1231
1232 static int radeon_modeset_create_props(struct radeon_device *rdev)
1233 {
1234 int sz;
1235
1236 if (rdev->is_atom_bios) {
1237 rdev->mode_info.coherent_mode_property =
1238 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1239 if (!rdev->mode_info.coherent_mode_property)
1240 return -ENOMEM;
1241 }
1242
1243 if (!ASIC_IS_AVIVO(rdev)) {
1244 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1245 rdev->mode_info.tmds_pll_property =
1246 drm_property_create_enum(rdev->ddev, 0,
1247 "tmds_pll",
1248 radeon_tmds_pll_enum_list, sz);
1249 }
1250
1251 rdev->mode_info.load_detect_property =
1252 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1253 if (!rdev->mode_info.load_detect_property)
1254 return -ENOMEM;
1255
1256 drm_mode_create_scaling_mode_property(rdev->ddev);
1257
1258 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1259 rdev->mode_info.tv_std_property =
1260 drm_property_create_enum(rdev->ddev, 0,
1261 "tv standard",
1262 radeon_tv_std_enum_list, sz);
1263
1264 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1265 rdev->mode_info.underscan_property =
1266 drm_property_create_enum(rdev->ddev, 0,
1267 "underscan",
1268 radeon_underscan_enum_list, sz);
1269
1270 rdev->mode_info.underscan_hborder_property =
1271 drm_property_create_range(rdev->ddev, 0,
1272 "underscan hborder", 0, 128);
1273 if (!rdev->mode_info.underscan_hborder_property)
1274 return -ENOMEM;
1275
1276 rdev->mode_info.underscan_vborder_property =
1277 drm_property_create_range(rdev->ddev, 0,
1278 "underscan vborder", 0, 128);
1279 if (!rdev->mode_info.underscan_vborder_property)
1280 return -ENOMEM;
1281
1282 sz = ARRAY_SIZE(radeon_audio_enum_list);
1283 rdev->mode_info.audio_property =
1284 drm_property_create_enum(rdev->ddev, 0,
1285 "audio",
1286 radeon_audio_enum_list, sz);
1287
1288 sz = ARRAY_SIZE(radeon_dither_enum_list);
1289 rdev->mode_info.dither_property =
1290 drm_property_create_enum(rdev->ddev, 0,
1291 "dither",
1292 radeon_dither_enum_list, sz);
1293
1294 return 0;
1295 }
1296
1297 void radeon_update_display_priority(struct radeon_device *rdev)
1298 {
1299 /* adjustment options for the display watermarks */
1300 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1301 /* set display priority to high for r3xx, rv515 chips
1302 * this avoids flickering due to underflow to the
1303 * display controllers during heavy acceleration.
1304 * Don't force high on rs4xx igp chips as it seems to
1305 * affect the sound card. See kernel bug 15982.
1306 */
1307 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1308 !(rdev->flags & RADEON_IS_IGP))
1309 rdev->disp_priority = 2;
1310 else
1311 rdev->disp_priority = 0;
1312 } else
1313 rdev->disp_priority = radeon_disp_priority;
1314
1315 }
1316
1317 /*
1318 * Allocate hdmi structs and determine register offsets
1319 */
1320 static void radeon_afmt_init(struct radeon_device *rdev)
1321 {
1322 int i;
1323
1324 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1325 rdev->mode_info.afmt[i] = NULL;
1326
1327 if (ASIC_IS_NODCE(rdev)) {
1328 /* nothing to do */
1329 } else if (ASIC_IS_DCE4(rdev)) {
1330 static uint32_t eg_offsets[] = {
1331 EVERGREEN_CRTC0_REGISTER_OFFSET,
1332 EVERGREEN_CRTC1_REGISTER_OFFSET,
1333 EVERGREEN_CRTC2_REGISTER_OFFSET,
1334 EVERGREEN_CRTC3_REGISTER_OFFSET,
1335 EVERGREEN_CRTC4_REGISTER_OFFSET,
1336 EVERGREEN_CRTC5_REGISTER_OFFSET,
1337 0x13830 - 0x7030,
1338 };
1339 int num_afmt;
1340
1341 /* DCE8 has 7 audio blocks tied to DIG encoders */
1342 /* DCE6 has 6 audio blocks tied to DIG encoders */
1343 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1344 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1345 if (ASIC_IS_DCE8(rdev))
1346 num_afmt = 7;
1347 else if (ASIC_IS_DCE6(rdev))
1348 num_afmt = 6;
1349 else if (ASIC_IS_DCE5(rdev))
1350 num_afmt = 6;
1351 else if (ASIC_IS_DCE41(rdev))
1352 num_afmt = 2;
1353 else /* DCE4 */
1354 num_afmt = 6;
1355
1356 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1357 for (i = 0; i < num_afmt; i++) {
1358 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1359 if (rdev->mode_info.afmt[i]) {
1360 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1361 rdev->mode_info.afmt[i]->id = i;
1362 }
1363 }
1364 } else if (ASIC_IS_DCE3(rdev)) {
1365 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1366 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1367 if (rdev->mode_info.afmt[0]) {
1368 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1369 rdev->mode_info.afmt[0]->id = 0;
1370 }
1371 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1372 if (rdev->mode_info.afmt[1]) {
1373 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1374 rdev->mode_info.afmt[1]->id = 1;
1375 }
1376 } else if (ASIC_IS_DCE2(rdev)) {
1377 /* DCE2 has at least 1 routable audio block */
1378 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1379 if (rdev->mode_info.afmt[0]) {
1380 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1381 rdev->mode_info.afmt[0]->id = 0;
1382 }
1383 /* r6xx has 2 routable audio blocks */
1384 if (rdev->family >= CHIP_R600) {
1385 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1386 if (rdev->mode_info.afmt[1]) {
1387 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1388 rdev->mode_info.afmt[1]->id = 1;
1389 }
1390 }
1391 }
1392 }
1393
1394 static void radeon_afmt_fini(struct radeon_device *rdev)
1395 {
1396 int i;
1397
1398 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1399 kfree(rdev->mode_info.afmt[i]);
1400 rdev->mode_info.afmt[i] = NULL;
1401 }
1402 }
1403
1404 int radeon_modeset_init(struct radeon_device *rdev)
1405 {
1406 int i;
1407 int ret;
1408
1409 drm_mode_config_init(rdev->ddev);
1410 rdev->mode_info.mode_config_initialized = true;
1411
1412 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1413
1414 if (ASIC_IS_DCE5(rdev)) {
1415 rdev->ddev->mode_config.max_width = 16384;
1416 rdev->ddev->mode_config.max_height = 16384;
1417 } else if (ASIC_IS_AVIVO(rdev)) {
1418 rdev->ddev->mode_config.max_width = 8192;
1419 rdev->ddev->mode_config.max_height = 8192;
1420 } else {
1421 rdev->ddev->mode_config.max_width = 4096;
1422 rdev->ddev->mode_config.max_height = 4096;
1423 }
1424
1425 rdev->ddev->mode_config.preferred_depth = 24;
1426 rdev->ddev->mode_config.prefer_shadow = 1;
1427
1428 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1429
1430 ret = radeon_modeset_create_props(rdev);
1431 if (ret) {
1432 return ret;
1433 }
1434
1435 /* init i2c buses */
1436 radeon_i2c_init(rdev);
1437
1438 /* check combios for a valid hardcoded EDID - Sun servers */
1439 if (!rdev->is_atom_bios) {
1440 /* check for hardcoded EDID in BIOS */
1441 radeon_combios_check_hardcoded_edid(rdev);
1442 }
1443
1444 /* allocate crtcs */
1445 for (i = 0; i < rdev->num_crtc; i++) {
1446 radeon_crtc_init(rdev->ddev, i);
1447 }
1448
1449 /* okay we should have all the bios connectors */
1450 ret = radeon_setup_enc_conn(rdev->ddev);
1451 if (!ret) {
1452 return ret;
1453 }
1454
1455 /* init dig PHYs, disp eng pll */
1456 if (rdev->is_atom_bios) {
1457 radeon_atom_encoder_init(rdev);
1458 radeon_atom_disp_eng_pll_init(rdev);
1459 }
1460
1461 /* initialize hpd */
1462 radeon_hpd_init(rdev);
1463
1464 /* setup afmt */
1465 radeon_afmt_init(rdev);
1466
1467 radeon_fbdev_init(rdev);
1468 drm_kms_helper_poll_init(rdev->ddev);
1469
1470 if (rdev->pm.dpm_enabled) {
1471 /* do dpm late init */
1472 ret = radeon_pm_late_init(rdev);
1473 if (ret) {
1474 rdev->pm.dpm_enabled = false;
1475 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1476 }
1477 /* set the dpm state for PX since there won't be
1478 * a modeset to call this.
1479 */
1480 radeon_pm_compute_clocks(rdev);
1481 }
1482
1483 return 0;
1484 }
1485
1486 void radeon_modeset_fini(struct radeon_device *rdev)
1487 {
1488 radeon_fbdev_fini(rdev);
1489 kfree(rdev->mode_info.bios_hardcoded_edid);
1490
1491 if (rdev->mode_info.mode_config_initialized) {
1492 radeon_afmt_fini(rdev);
1493 drm_kms_helper_poll_fini(rdev->ddev);
1494 radeon_hpd_fini(rdev);
1495 drm_mode_config_cleanup(rdev->ddev);
1496 rdev->mode_info.mode_config_initialized = false;
1497 }
1498 /* free i2c buses */
1499 radeon_i2c_fini(rdev);
1500 }
1501
1502 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1503 {
1504 /* try and guess if this is a tv or a monitor */
1505 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1506 (mode->vdisplay == 576) || /* 576p */
1507 (mode->vdisplay == 720) || /* 720p */
1508 (mode->vdisplay == 1080)) /* 1080p */
1509 return true;
1510 else
1511 return false;
1512 }
1513
1514 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1515 const struct drm_display_mode *mode,
1516 struct drm_display_mode *adjusted_mode)
1517 {
1518 struct drm_device *dev = crtc->dev;
1519 struct radeon_device *rdev = dev->dev_private;
1520 struct drm_encoder *encoder;
1521 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1522 struct radeon_encoder *radeon_encoder;
1523 struct drm_connector *connector;
1524 struct radeon_connector *radeon_connector;
1525 bool first = true;
1526 u32 src_v = 1, dst_v = 1;
1527 u32 src_h = 1, dst_h = 1;
1528
1529 radeon_crtc->h_border = 0;
1530 radeon_crtc->v_border = 0;
1531
1532 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1533 if (encoder->crtc != crtc)
1534 continue;
1535 radeon_encoder = to_radeon_encoder(encoder);
1536 connector = radeon_get_connector_for_encoder(encoder);
1537 radeon_connector = to_radeon_connector(connector);
1538
1539 if (first) {
1540 /* set scaling */
1541 if (radeon_encoder->rmx_type == RMX_OFF)
1542 radeon_crtc->rmx_type = RMX_OFF;
1543 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1544 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1545 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1546 else
1547 radeon_crtc->rmx_type = RMX_OFF;
1548 /* copy native mode */
1549 memcpy(&radeon_crtc->native_mode,
1550 &radeon_encoder->native_mode,
1551 sizeof(struct drm_display_mode));
1552 src_v = crtc->mode.vdisplay;
1553 dst_v = radeon_crtc->native_mode.vdisplay;
1554 src_h = crtc->mode.hdisplay;
1555 dst_h = radeon_crtc->native_mode.hdisplay;
1556
1557 /* fix up for overscan on hdmi */
1558 if (ASIC_IS_AVIVO(rdev) &&
1559 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1560 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1561 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1562 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1563 is_hdtv_mode(mode)))) {
1564 if (radeon_encoder->underscan_hborder != 0)
1565 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1566 else
1567 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1568 if (radeon_encoder->underscan_vborder != 0)
1569 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1570 else
1571 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1572 radeon_crtc->rmx_type = RMX_FULL;
1573 src_v = crtc->mode.vdisplay;
1574 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1575 src_h = crtc->mode.hdisplay;
1576 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1577 }
1578 first = false;
1579 } else {
1580 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1581 /* WARNING: Right now this can't happen but
1582 * in the future we need to check that scaling
1583 * are consistent across different encoder
1584 * (ie all encoder can work with the same
1585 * scaling).
1586 */
1587 DRM_ERROR("Scaling not consistent across encoder.\n");
1588 return false;
1589 }
1590 }
1591 }
1592 if (radeon_crtc->rmx_type != RMX_OFF) {
1593 fixed20_12 a, b;
1594 a.full = dfixed_const(src_v);
1595 b.full = dfixed_const(dst_v);
1596 radeon_crtc->vsc.full = dfixed_div(a, b);
1597 a.full = dfixed_const(src_h);
1598 b.full = dfixed_const(dst_h);
1599 radeon_crtc->hsc.full = dfixed_div(a, b);
1600 } else {
1601 radeon_crtc->vsc.full = dfixed_const(1);
1602 radeon_crtc->hsc.full = dfixed_const(1);
1603 }
1604 return true;
1605 }
1606
1607 /*
1608 * Retrieve current video scanout position of crtc on a given gpu, and
1609 * an optional accurate timestamp of when query happened.
1610 *
1611 * \param dev Device to query.
1612 * \param crtc Crtc to query.
1613 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1614 * \param *vpos Location where vertical scanout position should be stored.
1615 * \param *hpos Location where horizontal scanout position should go.
1616 * \param *stime Target location for timestamp taken immediately before
1617 * scanout position query. Can be NULL to skip timestamp.
1618 * \param *etime Target location for timestamp taken immediately after
1619 * scanout position query. Can be NULL to skip timestamp.
1620 *
1621 * Returns vpos as a positive number while in active scanout area.
1622 * Returns vpos as a negative number inside vblank, counting the number
1623 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1624 * until start of active scanout / end of vblank."
1625 *
1626 * \return Flags, or'ed together as follows:
1627 *
1628 * DRM_SCANOUTPOS_VALID = Query successful.
1629 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1630 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1631 * this flag means that returned position may be offset by a constant but
1632 * unknown small number of scanlines wrt. real scanout position.
1633 *
1634 */
1635 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1636 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1637 {
1638 u32 stat_crtc = 0, vbl = 0, position = 0;
1639 int vbl_start, vbl_end, vtotal, ret = 0;
1640 bool in_vbl = true;
1641
1642 struct radeon_device *rdev = dev->dev_private;
1643
1644 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1645
1646 /* Get optional system timestamp before query. */
1647 if (stime)
1648 *stime = ktime_get();
1649
1650 if (ASIC_IS_DCE4(rdev)) {
1651 if (crtc == 0) {
1652 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1653 EVERGREEN_CRTC0_REGISTER_OFFSET);
1654 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1655 EVERGREEN_CRTC0_REGISTER_OFFSET);
1656 ret |= DRM_SCANOUTPOS_VALID;
1657 }
1658 if (crtc == 1) {
1659 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1660 EVERGREEN_CRTC1_REGISTER_OFFSET);
1661 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1662 EVERGREEN_CRTC1_REGISTER_OFFSET);
1663 ret |= DRM_SCANOUTPOS_VALID;
1664 }
1665 if (crtc == 2) {
1666 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1667 EVERGREEN_CRTC2_REGISTER_OFFSET);
1668 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1669 EVERGREEN_CRTC2_REGISTER_OFFSET);
1670 ret |= DRM_SCANOUTPOS_VALID;
1671 }
1672 if (crtc == 3) {
1673 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1674 EVERGREEN_CRTC3_REGISTER_OFFSET);
1675 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1676 EVERGREEN_CRTC3_REGISTER_OFFSET);
1677 ret |= DRM_SCANOUTPOS_VALID;
1678 }
1679 if (crtc == 4) {
1680 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1681 EVERGREEN_CRTC4_REGISTER_OFFSET);
1682 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1683 EVERGREEN_CRTC4_REGISTER_OFFSET);
1684 ret |= DRM_SCANOUTPOS_VALID;
1685 }
1686 if (crtc == 5) {
1687 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1688 EVERGREEN_CRTC5_REGISTER_OFFSET);
1689 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1690 EVERGREEN_CRTC5_REGISTER_OFFSET);
1691 ret |= DRM_SCANOUTPOS_VALID;
1692 }
1693 } else if (ASIC_IS_AVIVO(rdev)) {
1694 if (crtc == 0) {
1695 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1696 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1697 ret |= DRM_SCANOUTPOS_VALID;
1698 }
1699 if (crtc == 1) {
1700 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1701 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1702 ret |= DRM_SCANOUTPOS_VALID;
1703 }
1704 } else {
1705 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1706 if (crtc == 0) {
1707 /* Assume vbl_end == 0, get vbl_start from
1708 * upper 16 bits.
1709 */
1710 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1711 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1712 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1713 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1714 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1715 if (!(stat_crtc & 1))
1716 in_vbl = false;
1717
1718 ret |= DRM_SCANOUTPOS_VALID;
1719 }
1720 if (crtc == 1) {
1721 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1722 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1723 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1724 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1725 if (!(stat_crtc & 1))
1726 in_vbl = false;
1727
1728 ret |= DRM_SCANOUTPOS_VALID;
1729 }
1730 }
1731
1732 /* Get optional system timestamp after query. */
1733 if (etime)
1734 *etime = ktime_get();
1735
1736 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1737
1738 /* Decode into vertical and horizontal scanout position. */
1739 *vpos = position & 0x1fff;
1740 *hpos = (position >> 16) & 0x1fff;
1741
1742 /* Valid vblank area boundaries from gpu retrieved? */
1743 if (vbl > 0) {
1744 /* Yes: Decode. */
1745 ret |= DRM_SCANOUTPOS_ACCURATE;
1746 vbl_start = vbl & 0x1fff;
1747 vbl_end = (vbl >> 16) & 0x1fff;
1748 }
1749 else {
1750 /* No: Fake something reasonable which gives at least ok results. */
1751 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1752 vbl_end = 0;
1753 }
1754
1755 /* Test scanout position against vblank region. */
1756 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1757 in_vbl = false;
1758
1759 /* Check if inside vblank area and apply corrective offsets:
1760 * vpos will then be >=0 in video scanout area, but negative
1761 * within vblank area, counting down the number of lines until
1762 * start of scanout.
1763 */
1764
1765 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1766 if (in_vbl && (*vpos >= vbl_start)) {
1767 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1768 *vpos = *vpos - vtotal;
1769 }
1770
1771 /* Correct for shifted end of vbl at vbl_end. */
1772 *vpos = *vpos - vbl_end;
1773
1774 /* In vblank? */
1775 if (in_vbl)
1776 ret |= DRM_SCANOUTPOS_INVBL;
1777
1778 /* Is vpos outside nominal vblank area, but less than
1779 * 1/100 of a frame height away from start of vblank?
1780 * If so, assume this isn't a massively delayed vblank
1781 * interrupt, but a vblank interrupt that fired a few
1782 * microseconds before true start of vblank. Compensate
1783 * by adding a full frame duration to the final timestamp.
1784 * Happens, e.g., on ATI R500, R600.
1785 *
1786 * We only do this if DRM_CALLED_FROM_VBLIRQ.
1787 */
1788 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1789 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1790 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1791
1792 if (vbl_start - *vpos < vtotal / 100) {
1793 *vpos -= vtotal;
1794
1795 /* Signal this correction as "applied". */
1796 ret |= 0x8;
1797 }
1798 }
1799
1800 return ret;
1801 }
Linux with added FPC-III support