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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / radeon_pm.c
blob8e8153e471c20a6b0dba28b38ce36bcd78f41a7b
1 /*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23 #include <drm/drmP.h>
24 #include "radeon.h"
25 #include "avivod.h"
26 #include "atom.h"
27 #include <linux/power_supply.h>
28 #include <linux/hwmon.h>
29 #include <linux/hwmon-sysfs.h>
30
31 #define RADEON_IDLE_LOOP_MS 100
32 #define RADEON_RECLOCK_DELAY_MS 200
33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
34
35 static const char *radeon_pm_state_type_name[5] = {
36 "",
37 "Powersave",
38 "Battery",
39 "Balanced",
40 "Performance",
41 };
42
43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
47 static void radeon_pm_update_profile(struct radeon_device *rdev);
48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
49
50 int radeon_pm_get_type_index(struct radeon_device *rdev,
51 enum radeon_pm_state_type ps_type,
52 int instance)
53 {
54 int i;
55 int found_instance = -1;
56
57 for (i = 0; i < rdev->pm.num_power_states; i++) {
58 if (rdev->pm.power_state[i].type == ps_type) {
59 found_instance++;
60 if (found_instance == instance)
61 return i;
62 }
63 }
64 /* return default if no match */
65 return rdev->pm.default_power_state_index;
66 }
67
68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
69 {
70 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
71 mutex_lock(&rdev->pm.mutex);
72 if (power_supply_is_system_supplied() > 0)
73 rdev->pm.dpm.ac_power = true;
74 else
75 rdev->pm.dpm.ac_power = false;
76 if (rdev->asic->dpm.enable_bapm)
77 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
78 mutex_unlock(&rdev->pm.mutex);
79 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
80 if (rdev->pm.profile == PM_PROFILE_AUTO) {
81 mutex_lock(&rdev->pm.mutex);
82 radeon_pm_update_profile(rdev);
83 radeon_pm_set_clocks(rdev);
84 mutex_unlock(&rdev->pm.mutex);
85 }
86 }
87 }
88
89 static void radeon_pm_update_profile(struct radeon_device *rdev)
90 {
91 switch (rdev->pm.profile) {
92 case PM_PROFILE_DEFAULT:
93 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
94 break;
95 case PM_PROFILE_AUTO:
96 if (power_supply_is_system_supplied() > 0) {
97 if (rdev->pm.active_crtc_count > 1)
98 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
99 else
100 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
101 } else {
102 if (rdev->pm.active_crtc_count > 1)
103 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
104 else
105 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
106 }
107 break;
108 case PM_PROFILE_LOW:
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
111 else
112 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
113 break;
114 case PM_PROFILE_MID:
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
117 else
118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
119 break;
120 case PM_PROFILE_HIGH:
121 if (rdev->pm.active_crtc_count > 1)
122 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
123 else
124 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
125 break;
126 }
127
128 if (rdev->pm.active_crtc_count == 0) {
129 rdev->pm.requested_power_state_index =
130 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
131 rdev->pm.requested_clock_mode_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
133 } else {
134 rdev->pm.requested_power_state_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
136 rdev->pm.requested_clock_mode_index =
137 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
138 }
139 }
140
141 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
142 {
143 struct radeon_bo *bo, *n;
144
145 if (list_empty(&rdev->gem.objects))
146 return;
147
148 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
149 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
150 ttm_bo_unmap_virtual(&bo->tbo);
151 }
152 }
153
154 static void radeon_sync_with_vblank(struct radeon_device *rdev)
155 {
156 if (rdev->pm.active_crtcs) {
157 rdev->pm.vblank_sync = false;
158 wait_event_timeout(
159 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
160 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
161 }
162 }
163
164 static void radeon_set_power_state(struct radeon_device *rdev)
165 {
166 u32 sclk, mclk;
167 bool misc_after = false;
168
169 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
170 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
171 return;
172
173 if (radeon_gui_idle(rdev)) {
174 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
175 clock_info[rdev->pm.requested_clock_mode_index].sclk;
176 if (sclk > rdev->pm.default_sclk)
177 sclk = rdev->pm.default_sclk;
178
179 /* starting with BTC, there is one state that is used for both
180 * MH and SH. Difference is that we always use the high clock index for
181 * mclk and vddci.
182 */
183 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
184 (rdev->family >= CHIP_BARTS) &&
185 rdev->pm.active_crtc_count &&
186 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
187 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
188 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
189 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
190 else
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.requested_clock_mode_index].mclk;
193
194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
196
197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
199 misc_after = true;
200
201 radeon_sync_with_vblank(rdev);
202
203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
204 if (!radeon_pm_in_vbl(rdev))
205 return;
206 }
207
208 radeon_pm_prepare(rdev);
209
210 if (!misc_after)
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
213
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
221 }
222
223 /* set memory clock */
224 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
230 }
231
232 if (misc_after)
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
235
236 radeon_pm_finish(rdev);
237
238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
240 } else
241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
242 }
243
244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
245 {
246 int i, r;
247
248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
251 return;
252
253 mutex_lock(&rdev->ddev->struct_mutex);
254 down_write(&rdev->pm.mclk_lock);
255 mutex_lock(&rdev->ring_lock);
256
257 /* wait for the rings to drain */
258 for (i = 0; i < RADEON_NUM_RINGS; i++) {
259 struct radeon_ring *ring = &rdev->ring[i];
260 if (!ring->ready) {
261 continue;
262 }
263 r = radeon_fence_wait_empty_locked(rdev, i);
264 if (r) {
265 /* needs a GPU reset dont reset here */
266 mutex_unlock(&rdev->ring_lock);
267 up_write(&rdev->pm.mclk_lock);
268 mutex_unlock(&rdev->ddev->struct_mutex);
269 return;
270 }
271 }
272
273 radeon_unmap_vram_bos(rdev);
274
275 if (rdev->irq.installed) {
276 for (i = 0; i < rdev->num_crtc; i++) {
277 if (rdev->pm.active_crtcs & (1 << i)) {
278 rdev->pm.req_vblank |= (1 << i);
279 drm_vblank_get(rdev->ddev, i);
280 }
281 }
282 }
283
284 radeon_set_power_state(rdev);
285
286 if (rdev->irq.installed) {
287 for (i = 0; i < rdev->num_crtc; i++) {
288 if (rdev->pm.req_vblank & (1 << i)) {
289 rdev->pm.req_vblank &= ~(1 << i);
290 drm_vblank_put(rdev->ddev, i);
291 }
292 }
293 }
294
295 /* update display watermarks based on new power state */
296 radeon_update_bandwidth_info(rdev);
297 if (rdev->pm.active_crtc_count)
298 radeon_bandwidth_update(rdev);
299
300 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
301
302 mutex_unlock(&rdev->ring_lock);
303 up_write(&rdev->pm.mclk_lock);
304 mutex_unlock(&rdev->ddev->struct_mutex);
305 }
306
307 static void radeon_pm_print_states(struct radeon_device *rdev)
308 {
309 int i, j;
310 struct radeon_power_state *power_state;
311 struct radeon_pm_clock_info *clock_info;
312
313 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
314 for (i = 0; i < rdev->pm.num_power_states; i++) {
315 power_state = &rdev->pm.power_state[i];
316 DRM_DEBUG_DRIVER("State %d: %s\n", i,
317 radeon_pm_state_type_name[power_state->type]);
318 if (i == rdev->pm.default_power_state_index)
319 DRM_DEBUG_DRIVER("\tDefault");
320 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
321 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
322 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
323 DRM_DEBUG_DRIVER("\tSingle display only\n");
324 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
325 for (j = 0; j < power_state->num_clock_modes; j++) {
326 clock_info = &(power_state->clock_info[j]);
327 if (rdev->flags & RADEON_IS_IGP)
328 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
329 j,
330 clock_info->sclk * 10);
331 else
332 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
333 j,
334 clock_info->sclk * 10,
335 clock_info->mclk * 10,
336 clock_info->voltage.voltage);
337 }
338 }
339 }
340
341 static ssize_t radeon_get_pm_profile(struct device *dev,
342 struct device_attribute *attr,
343 char *buf)
344 {
345 struct drm_device *ddev = dev_get_drvdata(dev);
346 struct radeon_device *rdev = ddev->dev_private;
347 int cp = rdev->pm.profile;
348
349 return snprintf(buf, PAGE_SIZE, "%s\n",
350 (cp == PM_PROFILE_AUTO) ? "auto" :
351 (cp == PM_PROFILE_LOW) ? "low" :
352 (cp == PM_PROFILE_MID) ? "mid" :
353 (cp == PM_PROFILE_HIGH) ? "high" : "default");
354 }
355
356 static ssize_t radeon_set_pm_profile(struct device *dev,
357 struct device_attribute *attr,
358 const char *buf,
359 size_t count)
360 {
361 struct drm_device *ddev = dev_get_drvdata(dev);
362 struct radeon_device *rdev = ddev->dev_private;
363
364 mutex_lock(&rdev->pm.mutex);
365 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
366 if (strncmp("default", buf, strlen("default")) == 0)
367 rdev->pm.profile = PM_PROFILE_DEFAULT;
368 else if (strncmp("auto", buf, strlen("auto")) == 0)
369 rdev->pm.profile = PM_PROFILE_AUTO;
370 else if (strncmp("low", buf, strlen("low")) == 0)
371 rdev->pm.profile = PM_PROFILE_LOW;
372 else if (strncmp("mid", buf, strlen("mid")) == 0)
373 rdev->pm.profile = PM_PROFILE_MID;
374 else if (strncmp("high", buf, strlen("high")) == 0)
375 rdev->pm.profile = PM_PROFILE_HIGH;
376 else {
377 count = -EINVAL;
378 goto fail;
379 }
380 radeon_pm_update_profile(rdev);
381 radeon_pm_set_clocks(rdev);
382 } else
383 count = -EINVAL;
384
385 fail:
386 mutex_unlock(&rdev->pm.mutex);
387
388 return count;
389 }
390
391 static ssize_t radeon_get_pm_method(struct device *dev,
392 struct device_attribute *attr,
393 char *buf)
394 {
395 struct drm_device *ddev = dev_get_drvdata(dev);
396 struct radeon_device *rdev = ddev->dev_private;
397 int pm = rdev->pm.pm_method;
398
399 return snprintf(buf, PAGE_SIZE, "%s\n",
400 (pm == PM_METHOD_DYNPM) ? "dynpm" :
401 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
402 }
403
404 static ssize_t radeon_set_pm_method(struct device *dev,
405 struct device_attribute *attr,
406 const char *buf,
407 size_t count)
408 {
409 struct drm_device *ddev = dev_get_drvdata(dev);
410 struct radeon_device *rdev = ddev->dev_private;
411
412 /* we don't support the legacy modes with dpm */
413 if (rdev->pm.pm_method == PM_METHOD_DPM) {
414 count = -EINVAL;
415 goto fail;
416 }
417
418 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
419 mutex_lock(&rdev->pm.mutex);
420 rdev->pm.pm_method = PM_METHOD_DYNPM;
421 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
422 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
423 mutex_unlock(&rdev->pm.mutex);
424 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
425 mutex_lock(&rdev->pm.mutex);
426 /* disable dynpm */
427 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
428 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
429 rdev->pm.pm_method = PM_METHOD_PROFILE;
430 mutex_unlock(&rdev->pm.mutex);
431 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
432 } else {
433 count = -EINVAL;
434 goto fail;
435 }
436 radeon_pm_compute_clocks(rdev);
437 fail:
438 return count;
439 }
440
441 static ssize_t radeon_get_dpm_state(struct device *dev,
442 struct device_attribute *attr,
443 char *buf)
444 {
445 struct drm_device *ddev = dev_get_drvdata(dev);
446 struct radeon_device *rdev = ddev->dev_private;
447 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
448
449 return snprintf(buf, PAGE_SIZE, "%s\n",
450 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
451 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
452 }
453
454 static ssize_t radeon_set_dpm_state(struct device *dev,
455 struct device_attribute *attr,
456 const char *buf,
457 size_t count)
458 {
459 struct drm_device *ddev = dev_get_drvdata(dev);
460 struct radeon_device *rdev = ddev->dev_private;
461
462 mutex_lock(&rdev->pm.mutex);
463 if (strncmp("battery", buf, strlen("battery")) == 0)
464 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
465 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
466 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
467 else if (strncmp("performance", buf, strlen("performance")) == 0)
468 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
469 else {
470 mutex_unlock(&rdev->pm.mutex);
471 count = -EINVAL;
472 goto fail;
473 }
474 mutex_unlock(&rdev->pm.mutex);
475 radeon_pm_compute_clocks(rdev);
476 fail:
477 return count;
478 }
479
480 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
481 struct device_attribute *attr,
482 char *buf)
483 {
484 struct drm_device *ddev = dev_get_drvdata(dev);
485 struct radeon_device *rdev = ddev->dev_private;
486 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
487
488 return snprintf(buf, PAGE_SIZE, "%s\n",
489 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
490 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
491 }
492
493 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
494 struct device_attribute *attr,
495 const char *buf,
496 size_t count)
497 {
498 struct drm_device *ddev = dev_get_drvdata(dev);
499 struct radeon_device *rdev = ddev->dev_private;
500 enum radeon_dpm_forced_level level;
501 int ret = 0;
502
503 mutex_lock(&rdev->pm.mutex);
504 if (strncmp("low", buf, strlen("low")) == 0) {
505 level = RADEON_DPM_FORCED_LEVEL_LOW;
506 } else if (strncmp("high", buf, strlen("high")) == 0) {
507 level = RADEON_DPM_FORCED_LEVEL_HIGH;
508 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
509 level = RADEON_DPM_FORCED_LEVEL_AUTO;
510 } else {
511 count = -EINVAL;
512 goto fail;
513 }
514 if (rdev->asic->dpm.force_performance_level) {
515 if (rdev->pm.dpm.thermal_active) {
516 count = -EINVAL;
517 goto fail;
518 }
519 ret = radeon_dpm_force_performance_level(rdev, level);
520 if (ret)
521 count = -EINVAL;
522 }
523 fail:
524 mutex_unlock(&rdev->pm.mutex);
525
526 return count;
527 }
528
529 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
530 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
531 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
532 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
533 radeon_get_dpm_forced_performance_level,
534 radeon_set_dpm_forced_performance_level);
535
536 static ssize_t radeon_hwmon_show_temp(struct device *dev,
537 struct device_attribute *attr,
538 char *buf)
539 {
540 struct radeon_device *rdev = dev_get_drvdata(dev);
541 int temp;
542
543 if (rdev->asic->pm.get_temperature)
544 temp = radeon_get_temperature(rdev);
545 else
546 temp = 0;
547
548 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
549 }
550
551 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
552 struct device_attribute *attr,
553 char *buf)
554 {
555 struct radeon_device *rdev = dev_get_drvdata(dev);
556 int hyst = to_sensor_dev_attr(attr)->index;
557 int temp;
558
559 if (hyst)
560 temp = rdev->pm.dpm.thermal.min_temp;
561 else
562 temp = rdev->pm.dpm.thermal.max_temp;
563
564 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
565 }
566
567 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
568 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
569 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
570
571 static struct attribute *hwmon_attributes[] = {
572 &sensor_dev_attr_temp1_input.dev_attr.attr,
573 &sensor_dev_attr_temp1_crit.dev_attr.attr,
574 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
575 NULL
576 };
577
578 static umode_t hwmon_attributes_visible(struct kobject *kobj,
579 struct attribute *attr, int index)
580 {
581 struct device *dev = container_of(kobj, struct device, kobj);
582 struct radeon_device *rdev = dev_get_drvdata(dev);
583
584 /* Skip limit attributes if DPM is not enabled */
585 if (rdev->pm.pm_method != PM_METHOD_DPM &&
586 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
587 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
588 return 0;
589
590 return attr->mode;
591 }
592
593 static const struct attribute_group hwmon_attrgroup = {
594 .attrs = hwmon_attributes,
595 .is_visible = hwmon_attributes_visible,
596 };
597
598 static const struct attribute_group *hwmon_groups[] = {
599 &hwmon_attrgroup,
600 NULL
601 };
602
603 static int radeon_hwmon_init(struct radeon_device *rdev)
604 {
605 int err = 0;
606 struct device *hwmon_dev;
607
608 switch (rdev->pm.int_thermal_type) {
609 case THERMAL_TYPE_RV6XX:
610 case THERMAL_TYPE_RV770:
611 case THERMAL_TYPE_EVERGREEN:
612 case THERMAL_TYPE_NI:
613 case THERMAL_TYPE_SUMO:
614 case THERMAL_TYPE_SI:
615 case THERMAL_TYPE_CI:
616 case THERMAL_TYPE_KV:
617 if (rdev->asic->pm.get_temperature == NULL)
618 return err;
619 hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
620 "radeon", rdev,
621 hwmon_groups);
622 if (IS_ERR(hwmon_dev)) {
623 err = PTR_ERR(hwmon_dev);
624 dev_err(rdev->dev,
625 "Unable to register hwmon device: %d\n", err);
626 }
627 break;
628 default:
629 break;
630 }
631
632 return err;
633 }
634
635 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
636 {
637 struct radeon_device *rdev =
638 container_of(work, struct radeon_device,
639 pm.dpm.thermal.work);
640 /* switch to the thermal state */
641 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
642
643 if (!rdev->pm.dpm_enabled)
644 return;
645
646 if (rdev->asic->pm.get_temperature) {
647 int temp = radeon_get_temperature(rdev);
648
649 if (temp < rdev->pm.dpm.thermal.min_temp)
650 /* switch back the user state */
651 dpm_state = rdev->pm.dpm.user_state;
652 } else {
653 if (rdev->pm.dpm.thermal.high_to_low)
654 /* switch back the user state */
655 dpm_state = rdev->pm.dpm.user_state;
656 }
657 mutex_lock(&rdev->pm.mutex);
658 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
659 rdev->pm.dpm.thermal_active = true;
660 else
661 rdev->pm.dpm.thermal_active = false;
662 rdev->pm.dpm.state = dpm_state;
663 mutex_unlock(&rdev->pm.mutex);
664
665 radeon_pm_compute_clocks(rdev);
666 }
667
668 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
669 enum radeon_pm_state_type dpm_state)
670 {
671 int i;
672 struct radeon_ps *ps;
673 u32 ui_class;
674 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
675 true : false;
676
677 /* check if the vblank period is too short to adjust the mclk */
678 if (single_display && rdev->asic->dpm.vblank_too_short) {
679 if (radeon_dpm_vblank_too_short(rdev))
680 single_display = false;
681 }
682
683 /* certain older asics have a separare 3D performance state,
684 * so try that first if the user selected performance
685 */
686 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
687 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
688 /* balanced states don't exist at the moment */
689 if (dpm_state == POWER_STATE_TYPE_BALANCED)
690 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
691
692 restart_search:
693 /* Pick the best power state based on current conditions */
694 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
695 ps = &rdev->pm.dpm.ps[i];
696 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
697 switch (dpm_state) {
698 /* user states */
699 case POWER_STATE_TYPE_BATTERY:
700 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
701 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
702 if (single_display)
703 return ps;
704 } else
705 return ps;
706 }
707 break;
708 case POWER_STATE_TYPE_BALANCED:
709 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
710 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
711 if (single_display)
712 return ps;
713 } else
714 return ps;
715 }
716 break;
717 case POWER_STATE_TYPE_PERFORMANCE:
718 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
719 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
720 if (single_display)
721 return ps;
722 } else
723 return ps;
724 }
725 break;
726 /* internal states */
727 case POWER_STATE_TYPE_INTERNAL_UVD:
728 if (rdev->pm.dpm.uvd_ps)
729 return rdev->pm.dpm.uvd_ps;
730 else
731 break;
732 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
733 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
734 return ps;
735 break;
736 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
737 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
738 return ps;
739 break;
740 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
741 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
742 return ps;
743 break;
744 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
745 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
746 return ps;
747 break;
748 case POWER_STATE_TYPE_INTERNAL_BOOT:
749 return rdev->pm.dpm.boot_ps;
750 case POWER_STATE_TYPE_INTERNAL_THERMAL:
751 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
752 return ps;
753 break;
754 case POWER_STATE_TYPE_INTERNAL_ACPI:
755 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
756 return ps;
757 break;
758 case POWER_STATE_TYPE_INTERNAL_ULV:
759 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
760 return ps;
761 break;
762 case POWER_STATE_TYPE_INTERNAL_3DPERF:
763 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
764 return ps;
765 break;
766 default:
767 break;
768 }
769 }
770 /* use a fallback state if we didn't match */
771 switch (dpm_state) {
772 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
773 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
774 goto restart_search;
775 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
776 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
777 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
778 if (rdev->pm.dpm.uvd_ps) {
779 return rdev->pm.dpm.uvd_ps;
780 } else {
781 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
782 goto restart_search;
783 }
784 case POWER_STATE_TYPE_INTERNAL_THERMAL:
785 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
786 goto restart_search;
787 case POWER_STATE_TYPE_INTERNAL_ACPI:
788 dpm_state = POWER_STATE_TYPE_BATTERY;
789 goto restart_search;
790 case POWER_STATE_TYPE_BATTERY:
791 case POWER_STATE_TYPE_BALANCED:
792 case POWER_STATE_TYPE_INTERNAL_3DPERF:
793 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
794 goto restart_search;
795 default:
796 break;
797 }
798
799 return NULL;
800 }
801
802 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
803 {
804 int i;
805 struct radeon_ps *ps;
806 enum radeon_pm_state_type dpm_state;
807 int ret;
808
809 /* if dpm init failed */
810 if (!rdev->pm.dpm_enabled)
811 return;
812
813 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
814 /* add other state override checks here */
815 if ((!rdev->pm.dpm.thermal_active) &&
816 (!rdev->pm.dpm.uvd_active))
817 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
818 }
819 dpm_state = rdev->pm.dpm.state;
820
821 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
822 if (ps)
823 rdev->pm.dpm.requested_ps = ps;
824 else
825 return;
826
827 /* no need to reprogram if nothing changed unless we are on BTC+ */
828 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
829 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
830 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
831 * all we need to do is update the display configuration.
832 */
833 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
834 /* update display watermarks based on new power state */
835 radeon_bandwidth_update(rdev);
836 /* update displays */
837 radeon_dpm_display_configuration_changed(rdev);
838 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
839 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
840 }
841 return;
842 } else {
843 /* for BTC+ if the num crtcs hasn't changed and state is the same,
844 * nothing to do, if the num crtcs is > 1 and state is the same,
845 * update display configuration.
846 */
847 if (rdev->pm.dpm.new_active_crtcs ==
848 rdev->pm.dpm.current_active_crtcs) {
849 return;
850 } else {
851 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
852 (rdev->pm.dpm.new_active_crtc_count > 1)) {
853 /* update display watermarks based on new power state */
854 radeon_bandwidth_update(rdev);
855 /* update displays */
856 radeon_dpm_display_configuration_changed(rdev);
857 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
858 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
859 return;
860 }
861 }
862 }
863 }
864
865 if (radeon_dpm == 1) {
866 printk("switching from power state:\n");
867 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
868 printk("switching to power state:\n");
869 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
870 }
871 mutex_lock(&rdev->ddev->struct_mutex);
872 down_write(&rdev->pm.mclk_lock);
873 mutex_lock(&rdev->ring_lock);
874
875 ret = radeon_dpm_pre_set_power_state(rdev);
876 if (ret)
877 goto done;
878
879 /* update display watermarks based on new power state */
880 radeon_bandwidth_update(rdev);
881 /* update displays */
882 radeon_dpm_display_configuration_changed(rdev);
883
884 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
885 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
886
887 /* wait for the rings to drain */
888 for (i = 0; i < RADEON_NUM_RINGS; i++) {
889 struct radeon_ring *ring = &rdev->ring[i];
890 if (ring->ready)
891 radeon_fence_wait_empty_locked(rdev, i);
892 }
893
894 /* program the new power state */
895 radeon_dpm_set_power_state(rdev);
896
897 /* update current power state */
898 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
899
900 radeon_dpm_post_set_power_state(rdev);
901
902 if (rdev->asic->dpm.force_performance_level) {
903 if (rdev->pm.dpm.thermal_active) {
904 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
905 /* force low perf level for thermal */
906 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
907 /* save the user's level */
908 rdev->pm.dpm.forced_level = level;
909 } else {
910 /* otherwise, user selected level */
911 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
912 }
913 }
914
915 done:
916 mutex_unlock(&rdev->ring_lock);
917 up_write(&rdev->pm.mclk_lock);
918 mutex_unlock(&rdev->ddev->struct_mutex);
919 }
920
921 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
922 {
923 enum radeon_pm_state_type dpm_state;
924
925 if (rdev->asic->dpm.powergate_uvd) {
926 mutex_lock(&rdev->pm.mutex);
927 /* don't powergate anything if we
928 have active but pause streams */
929 enable |= rdev->pm.dpm.sd > 0;
930 enable |= rdev->pm.dpm.hd > 0;
931 /* enable/disable UVD */
932 radeon_dpm_powergate_uvd(rdev, !enable);
933 mutex_unlock(&rdev->pm.mutex);
934 } else {
935 if (enable) {
936 mutex_lock(&rdev->pm.mutex);
937 rdev->pm.dpm.uvd_active = true;
938 /* disable this for now */
939 #if 0
940 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
941 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
942 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
943 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
944 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
945 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
946 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
947 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
948 else
949 #endif
950 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
951 rdev->pm.dpm.state = dpm_state;
952 mutex_unlock(&rdev->pm.mutex);
953 } else {
954 mutex_lock(&rdev->pm.mutex);
955 rdev->pm.dpm.uvd_active = false;
956 mutex_unlock(&rdev->pm.mutex);
957 }
958
959 radeon_pm_compute_clocks(rdev);
960 }
961 }
962
963 static void radeon_pm_suspend_old(struct radeon_device *rdev)
964 {
965 mutex_lock(&rdev->pm.mutex);
966 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
967 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
968 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
969 }
970 mutex_unlock(&rdev->pm.mutex);
971
972 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
973 }
974
975 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
976 {
977 mutex_lock(&rdev->pm.mutex);
978 /* disable dpm */
979 radeon_dpm_disable(rdev);
980 /* reset the power state */
981 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
982 rdev->pm.dpm_enabled = false;
983 mutex_unlock(&rdev->pm.mutex);
984 }
985
986 void radeon_pm_suspend(struct radeon_device *rdev)
987 {
988 if (rdev->pm.pm_method == PM_METHOD_DPM)
989 radeon_pm_suspend_dpm(rdev);
990 else
991 radeon_pm_suspend_old(rdev);
992 }
993
994 static void radeon_pm_resume_old(struct radeon_device *rdev)
995 {
996 /* set up the default clocks if the MC ucode is loaded */
997 if ((rdev->family >= CHIP_BARTS) &&
998 (rdev->family <= CHIP_CAYMAN) &&
999 rdev->mc_fw) {
1000 if (rdev->pm.default_vddc)
1001 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1002 SET_VOLTAGE_TYPE_ASIC_VDDC);
1003 if (rdev->pm.default_vddci)
1004 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1005 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1006 if (rdev->pm.default_sclk)
1007 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1008 if (rdev->pm.default_mclk)
1009 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1010 }
1011 /* asic init will reset the default power state */
1012 mutex_lock(&rdev->pm.mutex);
1013 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1014 rdev->pm.current_clock_mode_index = 0;
1015 rdev->pm.current_sclk = rdev->pm.default_sclk;
1016 rdev->pm.current_mclk = rdev->pm.default_mclk;
1017 if (rdev->pm.power_state) {
1018 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1019 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1020 }
1021 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1022 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1023 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1024 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1025 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1026 }
1027 mutex_unlock(&rdev->pm.mutex);
1028 radeon_pm_compute_clocks(rdev);
1029 }
1030
1031 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1032 {
1033 int ret;
1034
1035 /* asic init will reset to the boot state */
1036 mutex_lock(&rdev->pm.mutex);
1037 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1038 radeon_dpm_setup_asic(rdev);
1039 ret = radeon_dpm_enable(rdev);
1040 mutex_unlock(&rdev->pm.mutex);
1041 if (ret)
1042 goto dpm_resume_fail;
1043 rdev->pm.dpm_enabled = true;
1044 radeon_pm_compute_clocks(rdev);
1045 return;
1046
1047 dpm_resume_fail:
1048 DRM_ERROR("radeon: dpm resume failed\n");
1049 if ((rdev->family >= CHIP_BARTS) &&
1050 (rdev->family <= CHIP_CAYMAN) &&
1051 rdev->mc_fw) {
1052 if (rdev->pm.default_vddc)
1053 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1054 SET_VOLTAGE_TYPE_ASIC_VDDC);
1055 if (rdev->pm.default_vddci)
1056 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1057 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1058 if (rdev->pm.default_sclk)
1059 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1060 if (rdev->pm.default_mclk)
1061 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1062 }
1063 }
1064
1065 void radeon_pm_resume(struct radeon_device *rdev)
1066 {
1067 if (rdev->pm.pm_method == PM_METHOD_DPM)
1068 radeon_pm_resume_dpm(rdev);
1069 else
1070 radeon_pm_resume_old(rdev);
1071 }
1072
1073 static int radeon_pm_init_old(struct radeon_device *rdev)
1074 {
1075 int ret;
1076
1077 rdev->pm.profile = PM_PROFILE_DEFAULT;
1078 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1079 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1080 rdev->pm.dynpm_can_upclock = true;
1081 rdev->pm.dynpm_can_downclock = true;
1082 rdev->pm.default_sclk = rdev->clock.default_sclk;
1083 rdev->pm.default_mclk = rdev->clock.default_mclk;
1084 rdev->pm.current_sclk = rdev->clock.default_sclk;
1085 rdev->pm.current_mclk = rdev->clock.default_mclk;
1086 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1087
1088 if (rdev->bios) {
1089 if (rdev->is_atom_bios)
1090 radeon_atombios_get_power_modes(rdev);
1091 else
1092 radeon_combios_get_power_modes(rdev);
1093 radeon_pm_print_states(rdev);
1094 radeon_pm_init_profile(rdev);
1095 /* set up the default clocks if the MC ucode is loaded */
1096 if ((rdev->family >= CHIP_BARTS) &&
1097 (rdev->family <= CHIP_CAYMAN) &&
1098 rdev->mc_fw) {
1099 if (rdev->pm.default_vddc)
1100 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1101 SET_VOLTAGE_TYPE_ASIC_VDDC);
1102 if (rdev->pm.default_vddci)
1103 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1104 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1105 if (rdev->pm.default_sclk)
1106 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1107 if (rdev->pm.default_mclk)
1108 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1109 }
1110 }
1111
1112 /* set up the internal thermal sensor if applicable */
1113 ret = radeon_hwmon_init(rdev);
1114 if (ret)
1115 return ret;
1116
1117 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1118
1119 if (rdev->pm.num_power_states > 1) {
1120 /* where's the best place to put these? */
1121 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1122 if (ret)
1123 DRM_ERROR("failed to create device file for power profile\n");
1124 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1125 if (ret)
1126 DRM_ERROR("failed to create device file for power method\n");
1127
1128 if (radeon_debugfs_pm_init(rdev)) {
1129 DRM_ERROR("Failed to register debugfs file for PM!\n");
1130 }
1131
1132 DRM_INFO("radeon: power management initialized\n");
1133 }
1134
1135 return 0;
1136 }
1137
1138 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1139 {
1140 int i;
1141
1142 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1143 printk("== power state %d ==\n", i);
1144 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1145 }
1146 }
1147
1148 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1149 {
1150 int ret;
1151
1152 /* default to balanced state */
1153 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1154 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1155 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1156 rdev->pm.default_sclk = rdev->clock.default_sclk;
1157 rdev->pm.default_mclk = rdev->clock.default_mclk;
1158 rdev->pm.current_sclk = rdev->clock.default_sclk;
1159 rdev->pm.current_mclk = rdev->clock.default_mclk;
1160 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1161
1162 if (rdev->bios && rdev->is_atom_bios)
1163 radeon_atombios_get_power_modes(rdev);
1164 else
1165 return -EINVAL;
1166
1167 /* set up the internal thermal sensor if applicable */
1168 ret = radeon_hwmon_init(rdev);
1169 if (ret)
1170 return ret;
1171
1172 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1173 mutex_lock(&rdev->pm.mutex);
1174 radeon_dpm_init(rdev);
1175 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1176 if (radeon_dpm == 1)
1177 radeon_dpm_print_power_states(rdev);
1178 radeon_dpm_setup_asic(rdev);
1179 ret = radeon_dpm_enable(rdev);
1180 mutex_unlock(&rdev->pm.mutex);
1181 if (ret)
1182 goto dpm_failed;
1183 rdev->pm.dpm_enabled = true;
1184
1185 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1186 if (ret)
1187 DRM_ERROR("failed to create device file for dpm state\n");
1188 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1189 if (ret)
1190 DRM_ERROR("failed to create device file for dpm state\n");
1191 /* XXX: these are noops for dpm but are here for backwards compat */
1192 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1193 if (ret)
1194 DRM_ERROR("failed to create device file for power profile\n");
1195 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1196 if (ret)
1197 DRM_ERROR("failed to create device file for power method\n");
1198
1199 if (radeon_debugfs_pm_init(rdev)) {
1200 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1201 }
1202
1203 DRM_INFO("radeon: dpm initialized\n");
1204
1205 return 0;
1206
1207 dpm_failed:
1208 rdev->pm.dpm_enabled = false;
1209 if ((rdev->family >= CHIP_BARTS) &&
1210 (rdev->family <= CHIP_CAYMAN) &&
1211 rdev->mc_fw) {
1212 if (rdev->pm.default_vddc)
1213 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1214 SET_VOLTAGE_TYPE_ASIC_VDDC);
1215 if (rdev->pm.default_vddci)
1216 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1217 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1218 if (rdev->pm.default_sclk)
1219 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1220 if (rdev->pm.default_mclk)
1221 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1222 }
1223 DRM_ERROR("radeon: dpm initialization failed\n");
1224 return ret;
1225 }
1226
1227 int radeon_pm_init(struct radeon_device *rdev)
1228 {
1229 /* enable dpm on rv6xx+ */
1230 switch (rdev->family) {
1231 case CHIP_RV610:
1232 case CHIP_RV630:
1233 case CHIP_RV620:
1234 case CHIP_RV635:
1235 case CHIP_RV670:
1236 case CHIP_RS780:
1237 case CHIP_RS880:
1238 case CHIP_BARTS:
1239 case CHIP_TURKS:
1240 case CHIP_CAICOS:
1241 case CHIP_CAYMAN:
1242 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1243 if (!rdev->rlc_fw)
1244 rdev->pm.pm_method = PM_METHOD_PROFILE;
1245 else if ((rdev->family >= CHIP_RV770) &&
1246 (!(rdev->flags & RADEON_IS_IGP)) &&
1247 (!rdev->smc_fw))
1248 rdev->pm.pm_method = PM_METHOD_PROFILE;
1249 else if (radeon_dpm == 1)
1250 rdev->pm.pm_method = PM_METHOD_DPM;
1251 else
1252 rdev->pm.pm_method = PM_METHOD_PROFILE;
1253 break;
1254 case CHIP_RV770:
1255 case CHIP_RV730:
1256 case CHIP_RV710:
1257 case CHIP_RV740:
1258 case CHIP_CEDAR:
1259 case CHIP_REDWOOD:
1260 case CHIP_JUNIPER:
1261 case CHIP_CYPRESS:
1262 case CHIP_HEMLOCK:
1263 case CHIP_PALM:
1264 case CHIP_SUMO:
1265 case CHIP_SUMO2:
1266 case CHIP_ARUBA:
1267 case CHIP_TAHITI:
1268 case CHIP_PITCAIRN:
1269 case CHIP_VERDE:
1270 case CHIP_OLAND:
1271 case CHIP_HAINAN:
1272 case CHIP_BONAIRE:
1273 case CHIP_KABINI:
1274 case CHIP_KAVERI:
1275 case CHIP_HAWAII:
1276 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1277 if (!rdev->rlc_fw)
1278 rdev->pm.pm_method = PM_METHOD_PROFILE;
1279 else if ((rdev->family >= CHIP_RV770) &&
1280 (!(rdev->flags & RADEON_IS_IGP)) &&
1281 (!rdev->smc_fw))
1282 rdev->pm.pm_method = PM_METHOD_PROFILE;
1283 else if (radeon_dpm == 0)
1284 rdev->pm.pm_method = PM_METHOD_PROFILE;
1285 else
1286 rdev->pm.pm_method = PM_METHOD_DPM;
1287 break;
1288 default:
1289 /* default to profile method */
1290 rdev->pm.pm_method = PM_METHOD_PROFILE;
1291 break;
1292 }
1293
1294 if (rdev->pm.pm_method == PM_METHOD_DPM)
1295 return radeon_pm_init_dpm(rdev);
1296 else
1297 return radeon_pm_init_old(rdev);
1298 }
1299
1300 int radeon_pm_late_init(struct radeon_device *rdev)
1301 {
1302 int ret = 0;
1303
1304 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1305 mutex_lock(&rdev->pm.mutex);
1306 ret = radeon_dpm_late_enable(rdev);
1307 mutex_unlock(&rdev->pm.mutex);
1308 }
1309 return ret;
1310 }
1311
1312 static void radeon_pm_fini_old(struct radeon_device *rdev)
1313 {
1314 if (rdev->pm.num_power_states > 1) {
1315 mutex_lock(&rdev->pm.mutex);
1316 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1317 rdev->pm.profile = PM_PROFILE_DEFAULT;
1318 radeon_pm_update_profile(rdev);
1319 radeon_pm_set_clocks(rdev);
1320 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1321 /* reset default clocks */
1322 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1323 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1324 radeon_pm_set_clocks(rdev);
1325 }
1326 mutex_unlock(&rdev->pm.mutex);
1327
1328 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1329
1330 device_remove_file(rdev->dev, &dev_attr_power_profile);
1331 device_remove_file(rdev->dev, &dev_attr_power_method);
1332 }
1333
1334 if (rdev->pm.power_state)
1335 kfree(rdev->pm.power_state);
1336 }
1337
1338 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1339 {
1340 if (rdev->pm.num_power_states > 1) {
1341 mutex_lock(&rdev->pm.mutex);
1342 radeon_dpm_disable(rdev);
1343 mutex_unlock(&rdev->pm.mutex);
1344
1345 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1346 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1347 /* XXX backwards compat */
1348 device_remove_file(rdev->dev, &dev_attr_power_profile);
1349 device_remove_file(rdev->dev, &dev_attr_power_method);
1350 }
1351 radeon_dpm_fini(rdev);
1352
1353 if (rdev->pm.power_state)
1354 kfree(rdev->pm.power_state);
1355 }
1356
1357 void radeon_pm_fini(struct radeon_device *rdev)
1358 {
1359 if (rdev->pm.pm_method == PM_METHOD_DPM)
1360 radeon_pm_fini_dpm(rdev);
1361 else
1362 radeon_pm_fini_old(rdev);
1363 }
1364
1365 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1366 {
1367 struct drm_device *ddev = rdev->ddev;
1368 struct drm_crtc *crtc;
1369 struct radeon_crtc *radeon_crtc;
1370
1371 if (rdev->pm.num_power_states < 2)
1372 return;
1373
1374 mutex_lock(&rdev->pm.mutex);
1375
1376 rdev->pm.active_crtcs = 0;
1377 rdev->pm.active_crtc_count = 0;
1378 list_for_each_entry(crtc,
1379 &ddev->mode_config.crtc_list, head) {
1380 radeon_crtc = to_radeon_crtc(crtc);
1381 if (radeon_crtc->enabled) {
1382 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1383 rdev->pm.active_crtc_count++;
1384 }
1385 }
1386
1387 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1388 radeon_pm_update_profile(rdev);
1389 radeon_pm_set_clocks(rdev);
1390 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1391 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1392 if (rdev->pm.active_crtc_count > 1) {
1393 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1394 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1395
1396 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1397 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1398 radeon_pm_get_dynpm_state(rdev);
1399 radeon_pm_set_clocks(rdev);
1400
1401 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1402 }
1403 } else if (rdev->pm.active_crtc_count == 1) {
1404 /* TODO: Increase clocks if needed for current mode */
1405
1406 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1407 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1408 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1409 radeon_pm_get_dynpm_state(rdev);
1410 radeon_pm_set_clocks(rdev);
1411
1412 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1413 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1414 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1415 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1416 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1417 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1418 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1419 }
1420 } else { /* count == 0 */
1421 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1422 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1423
1424 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1425 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1426 radeon_pm_get_dynpm_state(rdev);
1427 radeon_pm_set_clocks(rdev);
1428 }
1429 }
1430 }
1431 }
1432
1433 mutex_unlock(&rdev->pm.mutex);
1434 }
1435
1436 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1437 {
1438 struct drm_device *ddev = rdev->ddev;
1439 struct drm_crtc *crtc;
1440 struct radeon_crtc *radeon_crtc;
1441
1442 if (!rdev->pm.dpm_enabled)
1443 return;
1444
1445 mutex_lock(&rdev->pm.mutex);
1446
1447 /* update active crtc counts */
1448 rdev->pm.dpm.new_active_crtcs = 0;
1449 rdev->pm.dpm.new_active_crtc_count = 0;
1450 list_for_each_entry(crtc,
1451 &ddev->mode_config.crtc_list, head) {
1452 radeon_crtc = to_radeon_crtc(crtc);
1453 if (crtc->enabled) {
1454 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1455 rdev->pm.dpm.new_active_crtc_count++;
1456 }
1457 }
1458
1459 /* update battery/ac status */
1460 if (power_supply_is_system_supplied() > 0)
1461 rdev->pm.dpm.ac_power = true;
1462 else
1463 rdev->pm.dpm.ac_power = false;
1464
1465 radeon_dpm_change_power_state_locked(rdev);
1466
1467 mutex_unlock(&rdev->pm.mutex);
1468
1469 }
1470
1471 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1472 {
1473 if (rdev->pm.pm_method == PM_METHOD_DPM)
1474 radeon_pm_compute_clocks_dpm(rdev);
1475 else
1476 radeon_pm_compute_clocks_old(rdev);
1477 }
1478
1479 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1480 {
1481 int crtc, vpos, hpos, vbl_status;
1482 bool in_vbl = true;
1483
1484 /* Iterate over all active crtc's. All crtc's must be in vblank,
1485 * otherwise return in_vbl == false.
1486 */
1487 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1488 if (rdev->pm.active_crtcs & (1 << crtc)) {
1489 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1490 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1491 !(vbl_status & DRM_SCANOUTPOS_INVBL))
1492 in_vbl = false;
1493 }
1494 }
1495
1496 return in_vbl;
1497 }
1498
1499 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1500 {
1501 u32 stat_crtc = 0;
1502 bool in_vbl = radeon_pm_in_vbl(rdev);
1503
1504 if (in_vbl == false)
1505 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1506 finish ? "exit" : "entry");
1507 return in_vbl;
1508 }
1509
1510 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1511 {
1512 struct radeon_device *rdev;
1513 int resched;
1514 rdev = container_of(work, struct radeon_device,
1515 pm.dynpm_idle_work.work);
1516
1517 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1518 mutex_lock(&rdev->pm.mutex);
1519 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1520 int not_processed = 0;
1521 int i;
1522
1523 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1524 struct radeon_ring *ring = &rdev->ring[i];
1525
1526 if (ring->ready) {
1527 not_processed += radeon_fence_count_emitted(rdev, i);
1528 if (not_processed >= 3)
1529 break;
1530 }
1531 }
1532
1533 if (not_processed >= 3) { /* should upclock */
1534 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1535 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1536 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1537 rdev->pm.dynpm_can_upclock) {
1538 rdev->pm.dynpm_planned_action =
1539 DYNPM_ACTION_UPCLOCK;
1540 rdev->pm.dynpm_action_timeout = jiffies +
1541 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1542 }
1543 } else if (not_processed == 0) { /* should downclock */
1544 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1545 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1546 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1547 rdev->pm.dynpm_can_downclock) {
1548 rdev->pm.dynpm_planned_action =
1549 DYNPM_ACTION_DOWNCLOCK;
1550 rdev->pm.dynpm_action_timeout = jiffies +
1551 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1552 }
1553 }
1554
1555 /* Note, radeon_pm_set_clocks is called with static_switch set
1556 * to false since we want to wait for vbl to avoid flicker.
1557 */
1558 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1559 jiffies > rdev->pm.dynpm_action_timeout) {
1560 radeon_pm_get_dynpm_state(rdev);
1561 radeon_pm_set_clocks(rdev);
1562 }
1563
1564 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1565 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1566 }
1567 mutex_unlock(&rdev->pm.mutex);
1568 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1569 }
1570
1571 /*
1572 * Debugfs info
1573 */
1574 #if defined(CONFIG_DEBUG_FS)
1575
1576 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1577 {
1578 struct drm_info_node *node = (struct drm_info_node *) m->private;
1579 struct drm_device *dev = node->minor->dev;
1580 struct radeon_device *rdev = dev->dev_private;
1581
1582 if (rdev->pm.dpm_enabled) {
1583 mutex_lock(&rdev->pm.mutex);
1584 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1585 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1586 else
1587 seq_printf(m, "Debugfs support not implemented for this asic\n");
1588 mutex_unlock(&rdev->pm.mutex);
1589 } else {
1590 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1591 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1592 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1593 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1594 else
1595 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1596 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1597 if (rdev->asic->pm.get_memory_clock)
1598 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1599 if (rdev->pm.current_vddc)
1600 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1601 if (rdev->asic->pm.get_pcie_lanes)
1602 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1603 }
1604
1605 return 0;
1606 }
1607
1608 static struct drm_info_list radeon_pm_info_list[] = {
1609 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1610 };
1611 #endif
1612
1613 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1614 {
1615 #if defined(CONFIG_DEBUG_FS)
1616 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1617 #else
1618 return 0;
1619 #endif
1620 }
Linux with added FPC-III support