drivers/gpu/drm/radeon/uvd_v4_2.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "radeon.h"
  28 #include "radeon_asic.h"
  29 #include "cikd.h"
  30
  31 /**
  32  * uvd_v4_2_resume - memory controller programming
  33  *
  34  * @rdev: radeon_device pointer
  35  *
  36  * Let the UVD memory controller know it's offsets
  37  */
  38 int uvd_v4_2_resume(struct radeon_device *rdev)
  39 {
  40         uint64_t addr;
  41         uint32_t size;
  42
  43         /* programm the VCPU memory controller bits 0-27 */
  44         addr = rdev->uvd.gpu_addr >> 3;
  45         size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
  46         WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
  47         WREG32(UVD_VCPU_CACHE_SIZE0, size);
  48
  49         addr += size;
  50         size = RADEON_UVD_STACK_SIZE >> 3;
  51         WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
  52         WREG32(UVD_VCPU_CACHE_SIZE1, size);
  53
  54         addr += size;
  55         size = RADEON_UVD_HEAP_SIZE >> 3;
  56         WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
  57         WREG32(UVD_VCPU_CACHE_SIZE2, size);
  58
  59         /* bits 28-31 */
  60         addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
  61         WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
  62
  63         /* bits 32-39 */
  64         addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
  65         WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
  66
  67         return 0;
  68 }