drivers/gpu/drm/rcar-du/rcar_du_group.c

   1 /*
   2  * rcar_du_group.c  --  R-Car Display Unit Channels Pair
   3  *
   4  * Copyright (C) 2013 Renesas Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 /*
  15  * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
  16  * unit, timings generator, ...) and device-global resources (start/stop
  17  * control, planes, ...) shared between the two CRTCs.
  18  *
  19  * The R8A7790 introduced a third CRTC with its own set of global resources.
  20  * This would be modeled as two separate DU device instances if it wasn't for
  21  * a handful or resources that are shared between the three CRTCs (mostly
  22  * related to input and output routing). For this reason the R8A7790 DU must be
  23  * modeled as a single device with three CRTCs, two sets of "semi-global"
  24  * resources, and a few device-global resources.
  25  *
  26  * The rcar_du_group object is a driver specific object, without any real
  27  * counterpart in the DU documentation, that models those semi-global resources.
  28  */
  29
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32
  33 #include "rcar_du_drv.h"
  34 #include "rcar_du_group.h"
  35 #include "rcar_du_regs.h"
  36
  37 u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
  38 {
  39         return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
  40 }
  41
  42 void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
  43 {
  44         rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
  45 }
  46
  47 static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
  48 {
  49         u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
  50
  51         if (!rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_DEFR8))
  52                 return;
  53
  54         /* The DEFR8 register for the first group also controls RGB output
  55          * routing to DPAD0
  56          */
  57         if (rgrp->index == 0)
  58                 defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
  59
  60         rcar_du_group_write(rgrp, DEFR8, defr8);
  61 }
  62
  63 static void rcar_du_group_setup(struct rcar_du_group *rgrp)
  64 {
  65         /* Enable extended features */
  66         rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
  67         rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
  68         rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
  69         rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
  70         rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
  71
  72         rcar_du_group_setup_defr8(rgrp);
  73
  74         /* Use DS1PR and DS2PR to configure planes priorities and connects the
  75          * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
  76          */
  77         rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
  78 }
  79
  80 /*
  81  * rcar_du_group_get - Acquire a reference to the DU channels group
  82  *
  83  * Acquiring the first reference setups core registers. A reference must be held
  84  * before accessing any hardware registers.
  85  *
  86  * This function must be called with the DRM mode_config lock held.
  87  *
  88  * Return 0 in case of success or a negative error code otherwise.
  89  */
  90 int rcar_du_group_get(struct rcar_du_group *rgrp)
  91 {
  92         if (rgrp->use_count)
  93                 goto done;
  94
  95         rcar_du_group_setup(rgrp);
  96
  97 done:
  98         rgrp->use_count++;
  99         return 0;
 100 }
 101
 102 /*
 103  * rcar_du_group_put - Release a reference to the DU
 104  *
 105  * This function must be called with the DRM mode_config lock held.
 106  */
 107 void rcar_du_group_put(struct rcar_du_group *rgrp)
 108 {
 109         --rgrp->use_count;
 110 }
 111
 112 static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
 113 {
 114         rcar_du_group_write(rgrp, DSYSR,
 115                 (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
 116                 (start ? DSYSR_DEN : DSYSR_DRES));
 117 }
 118
 119 void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
 120 {
 121         /* Many of the configuration bits are only updated when the display
 122          * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
 123          * of those bits could be pre-configured, but others (especially the
 124          * bits related to plane assignment to display timing controllers) need
 125          * to be modified at runtime.
 126          *
 127          * Restart the display controller if a start is requested. Sorry for the
 128          * flicker. It should be possible to move most of the "DRES-update" bits
 129          * setup to driver initialization time and minimize the number of cases
 130          * when the display controller will have to be restarted.
 131          */
 132         if (start) {
 133                 if (rgrp->used_crtcs++ != 0)
 134                         __rcar_du_group_start_stop(rgrp, false);
 135                 __rcar_du_group_start_stop(rgrp, true);
 136         } else {
 137                 if (--rgrp->used_crtcs == 0)
 138                         __rcar_du_group_start_stop(rgrp, false);
 139         }
 140 }
 141
 142 void rcar_du_group_restart(struct rcar_du_group *rgrp)
 143 {
 144         __rcar_du_group_start_stop(rgrp, false);
 145         __rcar_du_group_start_stop(rgrp, true);
 146 }
 147
 148 static int rcar_du_set_dpad0_routing(struct rcar_du_device *rcdu)
 149 {
 150         int ret;
 151
 152         /* RGB output routing to DPAD0 is configured in the DEFR8 register of
 153          * the first group. As this function can be called with the DU0 and DU1
 154          * CRTCs disabled, we need to enable the first group clock before
 155          * accessing the register.
 156          */
 157         ret = clk_prepare_enable(rcdu->crtcs[0].clock);
 158         if (ret < 0)
 159                 return ret;
 160
 161         rcar_du_group_setup_defr8(&rcdu->groups[0]);
 162
 163         clk_disable_unprepare(rcdu->crtcs[0].clock);
 164
 165         return 0;
 166 }
 167
 168 int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
 169 {
 170         struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
 171         u32 dorcr = rcar_du_group_read(rgrp, DORCR);
 172
 173         dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
 174
 175         /* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
 176          * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
 177          * by default.
 178          */
 179         if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
 180                 dorcr |= DORCR_PG2D_DS1;
 181         else
 182                 dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
 183
 184         rcar_du_group_write(rgrp, DORCR, dorcr);
 185
 186         return rcar_du_set_dpad0_routing(rgrp->dev);
 187 }