drivers/gpu/drm/tegra/dsi.h

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * Permission to use, copy, modify, distribute, and sell this software and its
   5  * documentation for any purpose is hereby granted without fee, provided that
   6  * the above copyright notice appear in all copies and that both that copyright
   7  * notice and this permission notice appear in supporting documentation, and
   8  * that the name of the copyright holders not be used in advertising or
   9  * publicity pertaining to distribution of the software without specific,
  10  * written prior permission.  The copyright holders make no representations
  11  * about the suitability of this software for any purpose.  It is provided "as
  12  * is" without express or implied warranty.
  13  *
  14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20  * OF THIS SOFTWARE.
  21  */
  22
  23 #ifndef DRM_TEGRA_DSI_H
  24 #define DRM_TEGRA_DSI_H
  25
  26 #define DSI_INCR_SYNCPT                 0x00
  27 #define DSI_INCR_SYNCPT_CONTROL         0x01
  28 #define DSI_INCR_SYNCPT_ERROR           0x02
  29 #define DSI_CTXSW                       0x08
  30 #define DSI_RD_DATA                     0x09
  31 #define DSI_WR_DATA                     0x0a
  32 #define DSI_POWER_CONTROL               0x0b
  33 #define DSI_POWER_CONTROL_ENABLE        (1 << 0)
  34 #define DSI_INT_ENABLE                  0x0c
  35 #define DSI_INT_STATUS                  0x0d
  36 #define DSI_INT_MASK                    0x0e
  37 #define DSI_HOST_CONTROL                0x0f
  38 #define DSI_HOST_CONTROL_RAW            (1 << 6)
  39 #define DSI_HOST_CONTROL_HS             (1 << 5)
  40 #define DSI_HOST_CONTROL_BTA            (1 << 2)
  41 #define DSI_HOST_CONTROL_CS             (1 << 1)
  42 #define DSI_HOST_CONTROL_ECC            (1 << 0)
  43 #define DSI_CONTROL                     0x10
  44 #define DSI_CONTROL_HS_CLK_CTRL         (1 << 20)
  45 #define DSI_CONTROL_CHANNEL(c)          (((c) & 0x3) << 16)
  46 #define DSI_CONTROL_FORMAT(f)           (((f) & 0x3) << 12)
  47 #define DSI_CONTROL_TX_TRIG(x)          (((x) & 0x3) <<  8)
  48 #define DSI_CONTROL_LANES(n)            (((n) & 0x3) <<  4)
  49 #define DSI_CONTROL_DCS_ENABLE          (1 << 3)
  50 #define DSI_CONTROL_SOURCE(s)           (((s) & 0x1) <<  2)
  51 #define DSI_CONTROL_VIDEO_ENABLE        (1 << 1)
  52 #define DSI_CONTROL_HOST_ENABLE         (1 << 0)
  53 #define DSI_SOL_DELAY                   0x11
  54 #define DSI_MAX_THRESHOLD               0x12
  55 #define DSI_TRIGGER                     0x13
  56 #define DSI_TX_CRC                      0x14
  57 #define DSI_STATUS                      0x15
  58 #define DSI_STATUS_IDLE                 (1 << 10)
  59 #define DSI_INIT_SEQ_CONTROL            0x1a
  60 #define DSI_INIT_SEQ_DATA_0             0x1b
  61 #define DSI_INIT_SEQ_DATA_1             0x1c
  62 #define DSI_INIT_SEQ_DATA_2             0x1d
  63 #define DSI_INIT_SEQ_DATA_3             0x1e
  64 #define DSI_INIT_SEQ_DATA_4             0x1f
  65 #define DSI_INIT_SEQ_DATA_5             0x20
  66 #define DSI_INIT_SEQ_DATA_6             0x21
  67 #define DSI_INIT_SEQ_DATA_7             0x22
  68 #define DSI_PKT_SEQ_0_LO                0x23
  69 #define DSI_PKT_SEQ_0_HI                0x24
  70 #define DSI_PKT_SEQ_1_LO                0x25
  71 #define DSI_PKT_SEQ_1_HI                0x26
  72 #define DSI_PKT_SEQ_2_LO                0x27
  73 #define DSI_PKT_SEQ_2_HI                0x28
  74 #define DSI_PKT_SEQ_3_LO                0x29
  75 #define DSI_PKT_SEQ_3_HI                0x2a
  76 #define DSI_PKT_SEQ_4_LO                0x2b
  77 #define DSI_PKT_SEQ_4_HI                0x2c
  78 #define DSI_PKT_SEQ_5_LO                0x2d
  79 #define DSI_PKT_SEQ_5_HI                0x2e
  80 #define DSI_DCS_CMDS                    0x33
  81 #define DSI_PKT_LEN_0_1                 0x34
  82 #define DSI_PKT_LEN_2_3                 0x35
  83 #define DSI_PKT_LEN_4_5                 0x36
  84 #define DSI_PKT_LEN_6_7                 0x37
  85 #define DSI_PHY_TIMING_0                0x3c
  86 #define DSI_PHY_TIMING_1                0x3d
  87 #define DSI_PHY_TIMING_2                0x3e
  88 #define DSI_BTA_TIMING                  0x3f
  89
  90 #define DSI_TIMING_FIELD(value, period, hwinc) \
  91         ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff)
  92
  93 #define DSI_TIMEOUT_0                   0x44
  94 #define DSI_TIMEOUT_LRX(x)              (((x) & 0xffff) << 16)
  95 #define DSI_TIMEOUT_HTX(x)              (((x) & 0xffff) <<  0)
  96 #define DSI_TIMEOUT_1                   0x45
  97 #define DSI_TIMEOUT_PR(x)               (((x) & 0xffff) << 16)
  98 #define DSI_TIMEOUT_TA(x)               (((x) & 0xffff) <<  0)
  99 #define DSI_TO_TALLY                    0x46
 100 #define DSI_TALLY_TA(x)                 (((x) & 0xff) << 16)
 101 #define DSI_TALLY_LRX(x)                (((x) & 0xff) <<  8)
 102 #define DSI_TALLY_HTX(x)                (((x) & 0xff) <<  0)
 103 #define DSI_PAD_CONTROL_0               0x4b
 104 #define DSI_PAD_CONTROL_VS1_PDIO(x)     (((x) & 0xf) <<  0)
 105 #define DSI_PAD_CONTROL_VS1_PDIO_CLK    (1 <<  8)
 106 #define DSI_PAD_CONTROL_VS1_PULLDN(x)   (((x) & 0xf) << 16)
 107 #define DSI_PAD_CONTROL_VS1_PULLDN_CLK  (1 << 24)
 108 #define DSI_PAD_CONTROL_CD              0x4c
 109 #define DSI_PAD_CD_STATUS               0x4d
 110 #define DSI_VIDEO_MODE_CONTROL          0x4e
 111 #define DSI_PAD_CONTROL_1               0x4f
 112 #define DSI_PAD_CONTROL_2               0x50
 113 #define DSI_PAD_OUT_CLK(x)              (((x) & 0x7) <<  0)
 114 #define DSI_PAD_LP_DN(x)                (((x) & 0x7) <<  4)
 115 #define DSI_PAD_LP_UP(x)                (((x) & 0x7) <<  8)
 116 #define DSI_PAD_SLEW_DN(x)              (((x) & 0x7) << 12)
 117 #define DSI_PAD_SLEW_UP(x)              (((x) & 0x7) << 16)
 118 #define DSI_PAD_CONTROL_3               0x51
 119 #define DSI_PAD_CONTROL_4               0x52
 120 #define DSI_GANGED_MODE_CONTROL         0x53
 121 #define DSI_GANGED_MODE_START           0x54
 122 #define DSI_GANGED_MODE_SIZE            0x55
 123 #define DSI_RAW_DATA_BYTE_COUNT         0x56
 124 #define DSI_ULTRA_LOW_POWER_CONTROL     0x57
 125 #define DSI_INIT_SEQ_DATA_8             0x58
 126 #define DSI_INIT_SEQ_DATA_9             0x59
 127 #define DSI_INIT_SEQ_DATA_10            0x5a
 128 #define DSI_INIT_SEQ_DATA_11            0x5b
 129 #define DSI_INIT_SEQ_DATA_12            0x5c
 130 #define DSI_INIT_SEQ_DATA_13            0x5d
 131 #define DSI_INIT_SEQ_DATA_14            0x5e
 132 #define DSI_INIT_SEQ_DATA_15            0x5f
 133
 134 #endif