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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-bfin-twi.c
blob3b9bd9a3f2b08a0a43683c87f1801d2f330185c3
1 /*
2 * Blackfin On-Chip Two Wire Interface Driver
3 *
4 * Copyright 2005-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/i2c.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/mm.h>
18 #include <linux/timer.h>
19 #include <linux/spinlock.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
24
25 #include <asm/blackfin.h>
26 #include <asm/portmux.h>
27 #include <asm/irq.h>
28 #include <asm/bfin_twi.h>
29
30 /* SMBus mode*/
31 #define TWI_I2C_MODE_STANDARD 1
32 #define TWI_I2C_MODE_STANDARDSUB 2
33 #define TWI_I2C_MODE_COMBINED 3
34 #define TWI_I2C_MODE_REPEAT 4
35
36 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
37 unsigned short twi_int_status)
38 {
39 unsigned short mast_stat = read_MASTER_STAT(iface);
40
41 if (twi_int_status & XMTSERV) {
42 if (iface->writeNum <= 0) {
43 /* start receive immediately after complete sending in
44 * combine mode.
45 */
46 if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
47 write_MASTER_CTL(iface,
48 read_MASTER_CTL(iface) | MDIR);
49 else if (iface->manual_stop)
50 write_MASTER_CTL(iface,
51 read_MASTER_CTL(iface) | STOP);
52 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
53 iface->cur_msg + 1 < iface->msg_num) {
54 if (iface->pmsg[iface->cur_msg + 1].flags &
55 I2C_M_RD)
56 write_MASTER_CTL(iface,
57 read_MASTER_CTL(iface) |
58 MDIR);
59 else
60 write_MASTER_CTL(iface,
61 read_MASTER_CTL(iface) &
62 ~MDIR);
63 }
64 }
65 /* Transmit next data */
66 while (iface->writeNum > 0 &&
67 (read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) {
68 SSYNC();
69 write_XMT_DATA8(iface, *(iface->transPtr++));
70 iface->writeNum--;
71 }
72 }
73 if (twi_int_status & RCVSERV) {
74 while (iface->readNum > 0 &&
75 (read_FIFO_STAT(iface) & RCVSTAT)) {
76 /* Receive next data */
77 *(iface->transPtr) = read_RCV_DATA8(iface);
78 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
79 /* Change combine mode into sub mode after
80 * read first data.
81 */
82 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
83 /* Get read number from first byte in block
84 * combine mode.
85 */
86 if (iface->readNum == 1 && iface->manual_stop)
87 iface->readNum = *iface->transPtr + 1;
88 }
89 iface->transPtr++;
90 iface->readNum--;
91 }
92
93 if (iface->readNum == 0) {
94 if (iface->manual_stop) {
95 /* Temporary workaround to avoid possible bus stall -
96 * Flush FIFO before issuing the STOP condition
97 */
98 read_RCV_DATA16(iface);
99 write_MASTER_CTL(iface,
100 read_MASTER_CTL(iface) | STOP);
101 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
102 iface->cur_msg + 1 < iface->msg_num) {
103 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
104 write_MASTER_CTL(iface,
105 read_MASTER_CTL(iface) | MDIR);
106 else
107 write_MASTER_CTL(iface,
108 read_MASTER_CTL(iface) & ~MDIR);
109 }
110 }
111 }
112 if (twi_int_status & MERR) {
113 write_INT_MASK(iface, 0);
114 write_MASTER_STAT(iface, 0x3e);
115 write_MASTER_CTL(iface, 0);
116 iface->result = -EIO;
117
118 if (mast_stat & LOSTARB)
119 dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
120 if (mast_stat & ANAK)
121 dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
122 if (mast_stat & DNAK)
123 dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
124 if (mast_stat & BUFRDERR)
125 dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
126 if (mast_stat & BUFWRERR)
127 dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
128
129 /* Faulty slave devices, may drive SDA low after a transfer
130 * finishes. To release the bus this code generates up to 9
131 * extra clocks until SDA is released.
132 */
133
134 if (read_MASTER_STAT(iface) & SDASEN) {
135 int cnt = 9;
136 do {
137 write_MASTER_CTL(iface, SCLOVR);
138 udelay(6);
139 write_MASTER_CTL(iface, 0);
140 udelay(6);
141 } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
142
143 write_MASTER_CTL(iface, SDAOVR | SCLOVR);
144 udelay(6);
145 write_MASTER_CTL(iface, SDAOVR);
146 udelay(6);
147 write_MASTER_CTL(iface, 0);
148 }
149
150 /* If it is a quick transfer, only address without data,
151 * not an err, return 1.
152 */
153 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
154 iface->transPtr == NULL &&
155 (twi_int_status & MCOMP) && (mast_stat & DNAK))
156 iface->result = 1;
157
158 complete(&iface->complete);
159 return;
160 }
161 if (twi_int_status & MCOMP) {
162 if (twi_int_status & (XMTSERV | RCVSERV) &&
163 (read_MASTER_CTL(iface) & MEN) == 0 &&
164 (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
165 iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
166 iface->result = -1;
167 write_INT_MASK(iface, 0);
168 write_MASTER_CTL(iface, 0);
169 } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
170 if (iface->readNum == 0) {
171 /* set the read number to 1 and ask for manual
172 * stop in block combine mode
173 */
174 iface->readNum = 1;
175 iface->manual_stop = 1;
176 write_MASTER_CTL(iface,
177 read_MASTER_CTL(iface) | (0xff << 6));
178 } else {
179 /* set the readd number in other
180 * combine mode.
181 */
182 write_MASTER_CTL(iface,
183 (read_MASTER_CTL(iface) &
184 (~(0xff << 6))) |
185 (iface->readNum << 6));
186 }
187 /* remove restart bit and enable master receive */
188 write_MASTER_CTL(iface,
189 read_MASTER_CTL(iface) & ~RSTART);
190 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
191 iface->cur_msg + 1 < iface->msg_num) {
192 iface->cur_msg++;
193 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
194 iface->writeNum = iface->readNum =
195 iface->pmsg[iface->cur_msg].len;
196 /* Set Transmit device address */
197 write_MASTER_ADDR(iface,
198 iface->pmsg[iface->cur_msg].addr);
199 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
200 iface->read_write = I2C_SMBUS_READ;
201 else {
202 iface->read_write = I2C_SMBUS_WRITE;
203 /* Transmit first data */
204 if (iface->writeNum > 0) {
205 write_XMT_DATA8(iface,
206 *(iface->transPtr++));
207 iface->writeNum--;
208 }
209 }
210
211 if (iface->pmsg[iface->cur_msg].len <= 255) {
212 write_MASTER_CTL(iface,
213 (read_MASTER_CTL(iface) &
214 (~(0xff << 6))) |
215 (iface->pmsg[iface->cur_msg].len << 6));
216 iface->manual_stop = 0;
217 } else {
218 write_MASTER_CTL(iface,
219 (read_MASTER_CTL(iface) |
220 (0xff << 6)));
221 iface->manual_stop = 1;
222 }
223 /* remove restart bit before last message */
224 if (iface->cur_msg + 1 == iface->msg_num)
225 write_MASTER_CTL(iface,
226 read_MASTER_CTL(iface) & ~RSTART);
227 } else {
228 iface->result = 1;
229 write_INT_MASK(iface, 0);
230 write_MASTER_CTL(iface, 0);
231 }
232 complete(&iface->complete);
233 }
234 }
235
236 /* Interrupt handler */
237 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
238 {
239 struct bfin_twi_iface *iface = dev_id;
240 unsigned long flags;
241 unsigned short twi_int_status;
242
243 spin_lock_irqsave(&iface->lock, flags);
244 while (1) {
245 twi_int_status = read_INT_STAT(iface);
246 if (!twi_int_status)
247 break;
248 /* Clear interrupt status */
249 write_INT_STAT(iface, twi_int_status);
250 bfin_twi_handle_interrupt(iface, twi_int_status);
251 SSYNC();
252 }
253 spin_unlock_irqrestore(&iface->lock, flags);
254 return IRQ_HANDLED;
255 }
256
257 /*
258 * One i2c master transfer
259 */
260 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
261 struct i2c_msg *msgs, int num)
262 {
263 struct bfin_twi_iface *iface = adap->algo_data;
264 struct i2c_msg *pmsg;
265 int rc = 0;
266
267 if (!(read_CONTROL(iface) & TWI_ENA))
268 return -ENXIO;
269
270 if (read_MASTER_STAT(iface) & BUSBUSY)
271 return -EAGAIN;
272
273 iface->pmsg = msgs;
274 iface->msg_num = num;
275 iface->cur_msg = 0;
276
277 pmsg = &msgs[0];
278 if (pmsg->flags & I2C_M_TEN) {
279 dev_err(&adap->dev, "10 bits addr not supported!\n");
280 return -EINVAL;
281 }
282
283 if (iface->msg_num > 1)
284 iface->cur_mode = TWI_I2C_MODE_REPEAT;
285 iface->manual_stop = 0;
286 iface->transPtr = pmsg->buf;
287 iface->writeNum = iface->readNum = pmsg->len;
288 iface->result = 0;
289 init_completion(&(iface->complete));
290 /* Set Transmit device address */
291 write_MASTER_ADDR(iface, pmsg->addr);
292
293 /* FIFO Initiation. Data in FIFO should be
294 * discarded before start a new operation.
295 */
296 write_FIFO_CTL(iface, 0x3);
297 SSYNC();
298 write_FIFO_CTL(iface, 0);
299 SSYNC();
300
301 if (pmsg->flags & I2C_M_RD)
302 iface->read_write = I2C_SMBUS_READ;
303 else {
304 iface->read_write = I2C_SMBUS_WRITE;
305 /* Transmit first data */
306 if (iface->writeNum > 0) {
307 write_XMT_DATA8(iface, *(iface->transPtr++));
308 iface->writeNum--;
309 SSYNC();
310 }
311 }
312
313 /* clear int stat */
314 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
315
316 /* Interrupt mask . Enable XMT, RCV interrupt */
317 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
318 SSYNC();
319
320 if (pmsg->len <= 255)
321 write_MASTER_CTL(iface, pmsg->len << 6);
322 else {
323 write_MASTER_CTL(iface, 0xff << 6);
324 iface->manual_stop = 1;
325 }
326
327 /* Master enable */
328 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
329 (iface->msg_num > 1 ? RSTART : 0) |
330 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
331 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
332 SSYNC();
333
334 while (!iface->result) {
335 if (!wait_for_completion_timeout(&iface->complete,
336 adap->timeout)) {
337 iface->result = -1;
338 dev_err(&adap->dev, "master transfer timeout\n");
339 }
340 }
341
342 if (iface->result == 1)
343 rc = iface->cur_msg + 1;
344 else
345 rc = iface->result;
346
347 return rc;
348 }
349
350 /*
351 * Generic i2c master transfer entrypoint
352 */
353 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
354 struct i2c_msg *msgs, int num)
355 {
356 return bfin_twi_do_master_xfer(adap, msgs, num);
357 }
358
359 /*
360 * One I2C SMBus transfer
361 */
362 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
363 unsigned short flags, char read_write,
364 u8 command, int size, union i2c_smbus_data *data)
365 {
366 struct bfin_twi_iface *iface = adap->algo_data;
367 int rc = 0;
368
369 if (!(read_CONTROL(iface) & TWI_ENA))
370 return -ENXIO;
371
372 if (read_MASTER_STAT(iface) & BUSBUSY)
373 return -EAGAIN;
374
375 iface->writeNum = 0;
376 iface->readNum = 0;
377
378 /* Prepare datas & select mode */
379 switch (size) {
380 case I2C_SMBUS_QUICK:
381 iface->transPtr = NULL;
382 iface->cur_mode = TWI_I2C_MODE_STANDARD;
383 break;
384 case I2C_SMBUS_BYTE:
385 if (data == NULL)
386 iface->transPtr = NULL;
387 else {
388 if (read_write == I2C_SMBUS_READ)
389 iface->readNum = 1;
390 else
391 iface->writeNum = 1;
392 iface->transPtr = &data->byte;
393 }
394 iface->cur_mode = TWI_I2C_MODE_STANDARD;
395 break;
396 case I2C_SMBUS_BYTE_DATA:
397 if (read_write == I2C_SMBUS_READ) {
398 iface->readNum = 1;
399 iface->cur_mode = TWI_I2C_MODE_COMBINED;
400 } else {
401 iface->writeNum = 1;
402 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
403 }
404 iface->transPtr = &data->byte;
405 break;
406 case I2C_SMBUS_WORD_DATA:
407 if (read_write == I2C_SMBUS_READ) {
408 iface->readNum = 2;
409 iface->cur_mode = TWI_I2C_MODE_COMBINED;
410 } else {
411 iface->writeNum = 2;
412 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
413 }
414 iface->transPtr = (u8 *)&data->word;
415 break;
416 case I2C_SMBUS_PROC_CALL:
417 iface->writeNum = 2;
418 iface->readNum = 2;
419 iface->cur_mode = TWI_I2C_MODE_COMBINED;
420 iface->transPtr = (u8 *)&data->word;
421 break;
422 case I2C_SMBUS_BLOCK_DATA:
423 if (read_write == I2C_SMBUS_READ) {
424 iface->readNum = 0;
425 iface->cur_mode = TWI_I2C_MODE_COMBINED;
426 } else {
427 iface->writeNum = data->block[0] + 1;
428 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
429 }
430 iface->transPtr = data->block;
431 break;
432 case I2C_SMBUS_I2C_BLOCK_DATA:
433 if (read_write == I2C_SMBUS_READ) {
434 iface->readNum = data->block[0];
435 iface->cur_mode = TWI_I2C_MODE_COMBINED;
436 } else {
437 iface->writeNum = data->block[0];
438 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
439 }
440 iface->transPtr = (u8 *)&data->block[1];
441 break;
442 default:
443 return -1;
444 }
445
446 iface->result = 0;
447 iface->manual_stop = 0;
448 iface->read_write = read_write;
449 iface->command = command;
450 init_completion(&(iface->complete));
451
452 /* FIFO Initiation. Data in FIFO should be discarded before
453 * start a new operation.
454 */
455 write_FIFO_CTL(iface, 0x3);
456 SSYNC();
457 write_FIFO_CTL(iface, 0);
458
459 /* clear int stat */
460 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
461
462 /* Set Transmit device address */
463 write_MASTER_ADDR(iface, addr);
464 SSYNC();
465
466 switch (iface->cur_mode) {
467 case TWI_I2C_MODE_STANDARDSUB:
468 write_XMT_DATA8(iface, iface->command);
469 write_INT_MASK(iface, MCOMP | MERR |
470 ((iface->read_write == I2C_SMBUS_READ) ?
471 RCVSERV : XMTSERV));
472 SSYNC();
473
474 if (iface->writeNum + 1 <= 255)
475 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
476 else {
477 write_MASTER_CTL(iface, 0xff << 6);
478 iface->manual_stop = 1;
479 }
480 /* Master enable */
481 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
482 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
483 break;
484 case TWI_I2C_MODE_COMBINED:
485 write_XMT_DATA8(iface, iface->command);
486 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
487 SSYNC();
488
489 if (iface->writeNum > 0)
490 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
491 else
492 write_MASTER_CTL(iface, 0x1 << 6);
493 /* Master enable */
494 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART |
495 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
496 break;
497 default:
498 write_MASTER_CTL(iface, 0);
499 if (size != I2C_SMBUS_QUICK) {
500 /* Don't access xmit data register when this is a
501 * read operation.
502 */
503 if (iface->read_write != I2C_SMBUS_READ) {
504 if (iface->writeNum > 0) {
505 write_XMT_DATA8(iface,
506 *(iface->transPtr++));
507 if (iface->writeNum <= 255)
508 write_MASTER_CTL(iface,
509 iface->writeNum << 6);
510 else {
511 write_MASTER_CTL(iface,
512 0xff << 6);
513 iface->manual_stop = 1;
514 }
515 iface->writeNum--;
516 } else {
517 write_XMT_DATA8(iface, iface->command);
518 write_MASTER_CTL(iface, 1 << 6);
519 }
520 } else {
521 if (iface->readNum > 0 && iface->readNum <= 255)
522 write_MASTER_CTL(iface,
523 iface->readNum << 6);
524 else if (iface->readNum > 255) {
525 write_MASTER_CTL(iface, 0xff << 6);
526 iface->manual_stop = 1;
527 } else
528 break;
529 }
530 }
531 write_INT_MASK(iface, MCOMP | MERR |
532 ((iface->read_write == I2C_SMBUS_READ) ?
533 RCVSERV : XMTSERV));
534 SSYNC();
535
536 /* Master enable */
537 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
538 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
539 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
540 break;
541 }
542 SSYNC();
543
544 while (!iface->result) {
545 if (!wait_for_completion_timeout(&iface->complete,
546 adap->timeout)) {
547 iface->result = -1;
548 dev_err(&adap->dev, "smbus transfer timeout\n");
549 }
550 }
551
552 rc = (iface->result >= 0) ? 0 : -1;
553
554 return rc;
555 }
556
557 /*
558 * Generic I2C SMBus transfer entrypoint
559 */
560 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
561 unsigned short flags, char read_write,
562 u8 command, int size, union i2c_smbus_data *data)
563 {
564 return bfin_twi_do_smbus_xfer(adap, addr, flags,
565 read_write, command, size, data);
566 }
567
568 /*
569 * Return what the adapter supports
570 */
571 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
572 {
573 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
574 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
575 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
576 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
577 }
578
579 static struct i2c_algorithm bfin_twi_algorithm = {
580 .master_xfer = bfin_twi_master_xfer,
581 .smbus_xfer = bfin_twi_smbus_xfer,
582 .functionality = bfin_twi_functionality,
583 };
584
585 #ifdef CONFIG_PM_SLEEP
586 static int i2c_bfin_twi_suspend(struct device *dev)
587 {
588 struct bfin_twi_iface *iface = dev_get_drvdata(dev);
589
590 iface->saved_clkdiv = read_CLKDIV(iface);
591 iface->saved_control = read_CONTROL(iface);
592
593 free_irq(iface->irq, iface);
594
595 /* Disable TWI */
596 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
597
598 return 0;
599 }
600
601 static int i2c_bfin_twi_resume(struct device *dev)
602 {
603 struct bfin_twi_iface *iface = dev_get_drvdata(dev);
604
605 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
606 0, to_platform_device(dev)->name, iface);
607 if (rc) {
608 dev_err(dev, "Can't get IRQ %d !\n", iface->irq);
609 return -ENODEV;
610 }
611
612 /* Resume TWI interface clock as specified */
613 write_CLKDIV(iface, iface->saved_clkdiv);
614
615 /* Resume TWI */
616 write_CONTROL(iface, iface->saved_control);
617
618 return 0;
619 }
620
621 static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm,
622 i2c_bfin_twi_suspend, i2c_bfin_twi_resume);
623 #define I2C_BFIN_TWI_PM_OPS (&i2c_bfin_twi_pm)
624 #else
625 #define I2C_BFIN_TWI_PM_OPS NULL
626 #endif
627
628 static int i2c_bfin_twi_probe(struct platform_device *pdev)
629 {
630 struct bfin_twi_iface *iface;
631 struct i2c_adapter *p_adap;
632 struct resource *res;
633 int rc;
634 unsigned int clkhilow;
635
636 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
637 if (!iface) {
638 dev_err(&pdev->dev, "Cannot allocate memory\n");
639 rc = -ENOMEM;
640 goto out_error_nomem;
641 }
642
643 spin_lock_init(&(iface->lock));
644
645 /* Find and map our resources */
646 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
647 if (res == NULL) {
648 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
649 rc = -ENOENT;
650 goto out_error_get_res;
651 }
652
653 iface->regs_base = ioremap(res->start, resource_size(res));
654 if (iface->regs_base == NULL) {
655 dev_err(&pdev->dev, "Cannot map IO\n");
656 rc = -ENXIO;
657 goto out_error_ioremap;
658 }
659
660 iface->irq = platform_get_irq(pdev, 0);
661 if (iface->irq < 0) {
662 dev_err(&pdev->dev, "No IRQ specified\n");
663 rc = -ENOENT;
664 goto out_error_no_irq;
665 }
666
667 p_adap = &iface->adap;
668 p_adap->nr = pdev->id;
669 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
670 p_adap->algo = &bfin_twi_algorithm;
671 p_adap->algo_data = iface;
672 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
673 p_adap->dev.parent = &pdev->dev;
674 p_adap->timeout = 5 * HZ;
675 p_adap->retries = 3;
676
677 rc = peripheral_request_list(
678 dev_get_platdata(&pdev->dev),
679 "i2c-bfin-twi");
680 if (rc) {
681 dev_err(&pdev->dev, "Can't setup pin mux!\n");
682 goto out_error_pin_mux;
683 }
684
685 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
686 0, pdev->name, iface);
687 if (rc) {
688 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
689 rc = -ENODEV;
690 goto out_error_req_irq;
691 }
692
693 /* Set TWI internal clock as 10MHz */
694 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
695
696 /*
697 * We will not end up with a CLKDIV=0 because no one will specify
698 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
699 */
700 clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
701
702 /* Set Twi interface clock as specified */
703 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
704
705 /* Enable TWI */
706 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
707 SSYNC();
708
709 rc = i2c_add_numbered_adapter(p_adap);
710 if (rc < 0) {
711 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
712 goto out_error_add_adapter;
713 }
714
715 platform_set_drvdata(pdev, iface);
716
717 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
718 "regs_base@%p\n", iface->regs_base);
719
720 return 0;
721
722 out_error_add_adapter:
723 free_irq(iface->irq, iface);
724 out_error_req_irq:
725 out_error_no_irq:
726 peripheral_free_list(dev_get_platdata(&pdev->dev));
727 out_error_pin_mux:
728 iounmap(iface->regs_base);
729 out_error_ioremap:
730 out_error_get_res:
731 kfree(iface);
732 out_error_nomem:
733 return rc;
734 }
735
736 static int i2c_bfin_twi_remove(struct platform_device *pdev)
737 {
738 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
739
740 i2c_del_adapter(&(iface->adap));
741 free_irq(iface->irq, iface);
742 peripheral_free_list(dev_get_platdata(&pdev->dev));
743 iounmap(iface->regs_base);
744 kfree(iface);
745
746 return 0;
747 }
748
749 static struct platform_driver i2c_bfin_twi_driver = {
750 .probe = i2c_bfin_twi_probe,
751 .remove = i2c_bfin_twi_remove,
752 .driver = {
753 .name = "i2c-bfin-twi",
754 .owner = THIS_MODULE,
755 .pm = I2C_BFIN_TWI_PM_OPS,
756 },
757 };
758
759 static int __init i2c_bfin_twi_init(void)
760 {
761 return platform_driver_register(&i2c_bfin_twi_driver);
762 }
763
764 static void __exit i2c_bfin_twi_exit(void)
765 {
766 platform_driver_unregister(&i2c_bfin_twi_driver);
767 }
768
769 subsys_initcall(i2c_bfin_twi_init);
770 module_exit(i2c_bfin_twi_exit);
771
772 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
773 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
774 MODULE_LICENSE("GPL");
775 MODULE_ALIAS("platform:i2c-bfin-twi");
Linux with added FPC-III support