drivers/i2c/busses/i2c-pnx.c

   1 /*
   2  * Provides I2C support for Philips PNX010x/PNX4008 boards.
   3  *
   4  * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
   5  *          Vitaly Wool <vwool@ru.mvista.com>
   6  *
   7  * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
   8  * the terms of the GNU General Public License version 2. This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/ioport.h>
  16 #include <linux/delay.h>
  17 #include <linux/i2c.h>
  18 #include <linux/timer.h>
  19 #include <linux/completion.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/i2c-pnx.h>
  22 #include <linux/io.h>
  23 #include <linux/err.h>
  24 #include <linux/clk.h>
  25 #include <linux/slab.h>
  26 #include <linux/of.h>
  27
  28 #define I2C_PNX_TIMEOUT_DEFAULT         10 /* msec */
  29 #define I2C_PNX_SPEED_KHZ_DEFAULT       100
  30 #define I2C_PNX_REGION_SIZE             0x100
  31
  32 enum {
  33         mstatus_tdi = 0x00000001,
  34         mstatus_afi = 0x00000002,
  35         mstatus_nai = 0x00000004,
  36         mstatus_drmi = 0x00000008,
  37         mstatus_active = 0x00000020,
  38         mstatus_scl = 0x00000040,
  39         mstatus_sda = 0x00000080,
  40         mstatus_rff = 0x00000100,
  41         mstatus_rfe = 0x00000200,
  42         mstatus_tff = 0x00000400,
  43         mstatus_tfe = 0x00000800,
  44 };
  45
  46 enum {
  47         mcntrl_tdie = 0x00000001,
  48         mcntrl_afie = 0x00000002,
  49         mcntrl_naie = 0x00000004,
  50         mcntrl_drmie = 0x00000008,
  51         mcntrl_drsie = 0x00000010,
  52         mcntrl_rffie = 0x00000020,
  53         mcntrl_daie = 0x00000040,
  54         mcntrl_tffie = 0x00000080,
  55         mcntrl_reset = 0x00000100,
  56         mcntrl_cdbmode = 0x00000400,
  57 };
  58
  59 enum {
  60         rw_bit = 1 << 0,
  61         start_bit = 1 << 8,
  62         stop_bit = 1 << 9,
  63 };
  64
  65 #define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
  66 #define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
  67 #define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
  68 #define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
  69 #define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
  70 #define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
  71 #define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
  72 #define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
  73 #define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
  74 #define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
  75 #define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
  76 #define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
  77 #define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
  78
  79 static inline int wait_timeout(struct i2c_pnx_algo_data *data)
  80 {
  81         long timeout = data->timeout;
  82         while (timeout > 0 &&
  83                         (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
  84                 mdelay(1);
  85                 timeout--;
  86         }
  87         return (timeout <= 0);
  88 }
  89
  90 static inline int wait_reset(struct i2c_pnx_algo_data *data)
  91 {
  92         long timeout = data->timeout;
  93         while (timeout > 0 &&
  94                         (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
  95                 mdelay(1);
  96                 timeout--;
  97         }
  98         return (timeout <= 0);
  99 }
 100
 101 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
 102 {
 103         struct timer_list *timer = &alg_data->mif.timer;
 104         unsigned long expires = msecs_to_jiffies(alg_data->timeout);
 105
 106         if (expires <= 1)
 107                 expires = 2;
 108
 109         del_timer_sync(timer);
 110
 111         dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n",
 112                 jiffies, expires);
 113
 114         timer->expires = jiffies + expires;
 115         timer->data = (unsigned long)alg_data;
 116
 117         add_timer(timer);
 118 }
 119
 120 /**
 121  * i2c_pnx_start - start a device
 122  * @slave_addr:         slave address
 123  * @adap:               pointer to adapter structure
 124  *
 125  * Generate a START signal in the desired mode.
 126  */
 127 static int i2c_pnx_start(unsigned char slave_addr,
 128         struct i2c_pnx_algo_data *alg_data)
 129 {
 130         dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
 131                 slave_addr, alg_data->mif.mode);
 132
 133         /* Check for 7 bit slave addresses only */
 134         if (slave_addr & ~0x7f) {
 135                 dev_err(&alg_data->adapter.dev,
 136                         "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
 137                         alg_data->adapter.name, slave_addr);
 138                 return -EINVAL;
 139         }
 140
 141         /* First, make sure bus is idle */
 142         if (wait_timeout(alg_data)) {
 143                 /* Somebody else is monopolizing the bus */
 144                 dev_err(&alg_data->adapter.dev,
 145                         "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
 146                         alg_data->adapter.name, slave_addr,
 147                         ioread32(I2C_REG_CTL(alg_data)),
 148                         ioread32(I2C_REG_STS(alg_data)));
 149                 return -EBUSY;
 150         } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
 151                 /* Sorry, we lost the bus */
 152                 dev_err(&alg_data->adapter.dev,
 153                         "%s: Arbitration failure. Slave addr = %02x\n",
 154                         alg_data->adapter.name, slave_addr);
 155                 return -EIO;
 156         }
 157
 158         /*
 159          * OK, I2C is enabled and we have the bus.
 160          * Clear the current TDI and AFI status flags.
 161          */
 162         iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
 163                   I2C_REG_STS(alg_data));
 164
 165         dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
 166                 (slave_addr << 1) | start_bit | alg_data->mif.mode);
 167
 168         /* Write the slave address, START bit and R/W bit */
 169         iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
 170                   I2C_REG_TX(alg_data));
 171
 172         dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * i2c_pnx_stop - stop a device
 179  * @adap:               pointer to I2C adapter structure
 180  *
 181  * Generate a STOP signal to terminate the master transaction.
 182  */
 183 static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
 184 {
 185         /* Only 1 msec max timeout due to interrupt context */
 186         long timeout = 1000;
 187
 188         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 189                 __func__, ioread32(I2C_REG_STS(alg_data)));
 190
 191         /* Write a STOP bit to TX FIFO */
 192         iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
 193
 194         /* Wait until the STOP is seen. */
 195         while (timeout > 0 &&
 196                (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
 197                 /* may be called from interrupt context */
 198                 udelay(1);
 199                 timeout--;
 200         }
 201
 202         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 203                 __func__, ioread32(I2C_REG_STS(alg_data)));
 204 }
 205
 206 /**
 207  * i2c_pnx_master_xmit - transmit data to slave
 208  * @adap:               pointer to I2C adapter structure
 209  *
 210  * Sends one byte of data to the slave
 211  */
 212 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
 213 {
 214         u32 val;
 215
 216         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 217                 __func__, ioread32(I2C_REG_STS(alg_data)));
 218
 219         if (alg_data->mif.len > 0) {
 220                 /* We still have something to talk about... */
 221                 val = *alg_data->mif.buf++;
 222
 223                 if (alg_data->mif.len == 1)
 224                         val |= stop_bit;
 225
 226                 alg_data->mif.len--;
 227                 iowrite32(val, I2C_REG_TX(alg_data));
 228
 229                 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
 230                         __func__, val, alg_data->mif.len + 1);
 231
 232                 if (alg_data->mif.len == 0) {
 233                         if (alg_data->last) {
 234                                 /* Wait until the STOP is seen. */
 235                                 if (wait_timeout(alg_data))
 236                                         dev_err(&alg_data->adapter.dev,
 237                                                 "The bus is still active after timeout\n");
 238                         }
 239                         /* Disable master interrupts */
 240                         iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
 241                                 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
 242                                   I2C_REG_CTL(alg_data));
 243
 244                         del_timer_sync(&alg_data->mif.timer);
 245
 246                         dev_dbg(&alg_data->adapter.dev,
 247                                 "%s(): Waking up xfer routine.\n",
 248                                 __func__);
 249
 250                         complete(&alg_data->mif.complete);
 251                 }
 252         } else if (alg_data->mif.len == 0) {
 253                 /* zero-sized transfer */
 254                 i2c_pnx_stop(alg_data);
 255
 256                 /* Disable master interrupts. */
 257                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
 258                         ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
 259                           I2C_REG_CTL(alg_data));
 260
 261                 /* Stop timer. */
 262                 del_timer_sync(&alg_data->mif.timer);
 263                 dev_dbg(&alg_data->adapter.dev,
 264                         "%s(): Waking up xfer routine after zero-xfer.\n",
 265                         __func__);
 266
 267                 complete(&alg_data->mif.complete);
 268         }
 269
 270         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 271                 __func__, ioread32(I2C_REG_STS(alg_data)));
 272
 273         return 0;
 274 }
 275
 276 /**
 277  * i2c_pnx_master_rcv - receive data from slave
 278  * @adap:               pointer to I2C adapter structure
 279  *
 280  * Reads one byte data from the slave
 281  */
 282 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
 283 {
 284         unsigned int val = 0;
 285         u32 ctl = 0;
 286
 287         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 288                 __func__, ioread32(I2C_REG_STS(alg_data)));
 289
 290         /* Check, whether there is already data,
 291          * or we didn't 'ask' for it yet.
 292          */
 293         if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
 294                 /* 'Asking' is done asynchronously, e.g. dummy TX of several
 295                  * bytes is done before the first actual RX arrives in FIFO.
 296                  * Therefore, ordered bytes (via TX) are counted separately.
 297                  */
 298                 if (alg_data->mif.order) {
 299                         dev_dbg(&alg_data->adapter.dev,
 300                                 "%s(): Write dummy data to fill Rx-fifo...\n",
 301                                 __func__);
 302
 303                         if (alg_data->mif.order == 1) {
 304                                 /* Last byte, do not acknowledge next rcv. */
 305                                 val |= stop_bit;
 306
 307                                 /*
 308                                  * Enable interrupt RFDAIE (data in Rx fifo),
 309                                  * and disable DRMIE (need data for Tx)
 310                                  */
 311                                 ctl = ioread32(I2C_REG_CTL(alg_data));
 312                                 ctl |= mcntrl_rffie | mcntrl_daie;
 313                                 ctl &= ~mcntrl_drmie;
 314                                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 315                         }
 316
 317                         /*
 318                          * Now we'll 'ask' for data:
 319                          * For each byte we want to receive, we must
 320                          * write a (dummy) byte to the Tx-FIFO.
 321                          */
 322                         iowrite32(val, I2C_REG_TX(alg_data));
 323                         alg_data->mif.order--;
 324                 }
 325                 return 0;
 326         }
 327
 328         /* Handle data. */
 329         if (alg_data->mif.len > 0) {
 330                 val = ioread32(I2C_REG_RX(alg_data));
 331                 *alg_data->mif.buf++ = (u8) (val & 0xff);
 332                 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
 333                         __func__, val, alg_data->mif.len);
 334
 335                 alg_data->mif.len--;
 336                 if (alg_data->mif.len == 0) {
 337                         if (alg_data->last)
 338                                 /* Wait until the STOP is seen. */
 339                                 if (wait_timeout(alg_data))
 340                                         dev_err(&alg_data->adapter.dev,
 341                                                 "The bus is still active after timeout\n");
 342
 343                         /* Disable master interrupts */
 344                         ctl = ioread32(I2C_REG_CTL(alg_data));
 345                         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 346                                  mcntrl_drmie | mcntrl_daie);
 347                         iowrite32(ctl, I2C_REG_CTL(alg_data));
 348
 349                         /* Kill timer. */
 350                         del_timer_sync(&alg_data->mif.timer);
 351                         complete(&alg_data->mif.complete);
 352                 }
 353         }
 354
 355         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 356                 __func__, ioread32(I2C_REG_STS(alg_data)));
 357
 358         return 0;
 359 }
 360
 361 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
 362 {
 363         struct i2c_pnx_algo_data *alg_data = dev_id;
 364         u32 stat, ctl;
 365
 366         dev_dbg(&alg_data->adapter.dev,
 367                 "%s(): mstat = %x mctrl = %x, mode = %d\n",
 368                 __func__,
 369                 ioread32(I2C_REG_STS(alg_data)),
 370                 ioread32(I2C_REG_CTL(alg_data)),
 371                 alg_data->mif.mode);
 372         stat = ioread32(I2C_REG_STS(alg_data));
 373
 374         /* let's see what kind of event this is */
 375         if (stat & mstatus_afi) {
 376                 /* We lost arbitration in the midst of a transfer */
 377                 alg_data->mif.ret = -EIO;
 378
 379                 /* Disable master interrupts. */
 380                 ctl = ioread32(I2C_REG_CTL(alg_data));
 381                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 382                          mcntrl_drmie);
 383                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 384
 385                 /* Stop timer, to prevent timeout. */
 386                 del_timer_sync(&alg_data->mif.timer);
 387                 complete(&alg_data->mif.complete);
 388         } else if (stat & mstatus_nai) {
 389                 /* Slave did not acknowledge, generate a STOP */
 390                 dev_dbg(&alg_data->adapter.dev,
 391                         "%s(): Slave did not acknowledge, generating a STOP.\n",
 392                         __func__);
 393                 i2c_pnx_stop(alg_data);
 394
 395                 /* Disable master interrupts. */
 396                 ctl = ioread32(I2C_REG_CTL(alg_data));
 397                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 398                          mcntrl_drmie);
 399                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 400
 401                 /* Our return value. */
 402                 alg_data->mif.ret = -EIO;
 403
 404                 /* Stop timer, to prevent timeout. */
 405                 del_timer_sync(&alg_data->mif.timer);
 406                 complete(&alg_data->mif.complete);
 407         } else {
 408                 /*
 409                  * Two options:
 410                  * - Master Tx needs data.
 411                  * - There is data in the Rx-fifo
 412                  * The latter is only the case if we have requested for data,
 413                  * via a dummy write. (See 'i2c_pnx_master_rcv'.)
 414                  * We therefore check, as a sanity check, whether that interrupt
 415                  * has been enabled.
 416                  */
 417                 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
 418                         if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
 419                                 i2c_pnx_master_xmit(alg_data);
 420                         } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
 421                                 i2c_pnx_master_rcv(alg_data);
 422                         }
 423                 }
 424         }
 425
 426         /* Clear TDI and AFI bits */
 427         stat = ioread32(I2C_REG_STS(alg_data));
 428         iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
 429
 430         dev_dbg(&alg_data->adapter.dev,
 431                 "%s(): exiting, stat = %x ctrl = %x.\n",
 432                  __func__, ioread32(I2C_REG_STS(alg_data)),
 433                  ioread32(I2C_REG_CTL(alg_data)));
 434
 435         return IRQ_HANDLED;
 436 }
 437
 438 static void i2c_pnx_timeout(unsigned long data)
 439 {
 440         struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data;
 441         u32 ctl;
 442
 443         dev_err(&alg_data->adapter.dev,
 444                 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
 445                 ioread32(I2C_REG_STS(alg_data)),
 446                 ioread32(I2C_REG_CTL(alg_data)));
 447
 448         /* Reset master and disable interrupts */
 449         ctl = ioread32(I2C_REG_CTL(alg_data));
 450         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
 451         iowrite32(ctl, I2C_REG_CTL(alg_data));
 452
 453         ctl |= mcntrl_reset;
 454         iowrite32(ctl, I2C_REG_CTL(alg_data));
 455         wait_reset(alg_data);
 456         alg_data->mif.ret = -EIO;
 457         complete(&alg_data->mif.complete);
 458 }
 459
 460 static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
 461 {
 462         u32 stat;
 463
 464         if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
 465                 dev_err(&alg_data->adapter.dev,
 466                         "%s: Bus is still active after xfer. Reset it...\n",
 467                         alg_data->adapter.name);
 468                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 469                           I2C_REG_CTL(alg_data));
 470                 wait_reset(alg_data);
 471         } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
 472                 /* If there is data in the fifo's after transfer,
 473                  * flush fifo's by reset.
 474                  */
 475                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 476                           I2C_REG_CTL(alg_data));
 477                 wait_reset(alg_data);
 478         } else if (stat & mstatus_nai) {
 479                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 480                           I2C_REG_CTL(alg_data));
 481                 wait_reset(alg_data);
 482         }
 483 }
 484
 485 /**
 486  * i2c_pnx_xfer - generic transfer entry point
 487  * @adap:               pointer to I2C adapter structure
 488  * @msgs:               array of messages
 489  * @num:                number of messages
 490  *
 491  * Initiates the transfer
 492  */
 493 static int
 494 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 495 {
 496         struct i2c_msg *pmsg;
 497         int rc = 0, completed = 0, i;
 498         struct i2c_pnx_algo_data *alg_data = adap->algo_data;
 499         u32 stat = ioread32(I2C_REG_STS(alg_data));
 500
 501         dev_dbg(&alg_data->adapter.dev,
 502                 "%s(): entering: %d messages, stat = %04x.\n",
 503                 __func__, num, ioread32(I2C_REG_STS(alg_data)));
 504
 505         bus_reset_if_active(alg_data);
 506
 507         /* Process transactions in a loop. */
 508         for (i = 0; rc >= 0 && i < num; i++) {
 509                 u8 addr;
 510
 511                 pmsg = &msgs[i];
 512                 addr = pmsg->addr;
 513
 514                 if (pmsg->flags & I2C_M_TEN) {
 515                         dev_err(&alg_data->adapter.dev,
 516                                 "%s: 10 bits addr not supported!\n",
 517                                 alg_data->adapter.name);
 518                         rc = -EINVAL;
 519                         break;
 520                 }
 521
 522                 alg_data->mif.buf = pmsg->buf;
 523                 alg_data->mif.len = pmsg->len;
 524                 alg_data->mif.order = pmsg->len;
 525                 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
 526                         I2C_SMBUS_READ : I2C_SMBUS_WRITE;
 527                 alg_data->mif.ret = 0;
 528                 alg_data->last = (i == num - 1);
 529
 530                 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
 531                         __func__, alg_data->mif.mode, alg_data->mif.len);
 532
 533                 i2c_pnx_arm_timer(alg_data);
 534
 535                 /* initialize the completion var */
 536                 init_completion(&alg_data->mif.complete);
 537
 538                 /* Enable master interrupt */
 539                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
 540                                 mcntrl_naie | mcntrl_drmie,
 541                           I2C_REG_CTL(alg_data));
 542
 543                 /* Put start-code and slave-address on the bus. */
 544                 rc = i2c_pnx_start(addr, alg_data);
 545                 if (rc < 0)
 546                         break;
 547
 548                 /* Wait for completion */
 549                 wait_for_completion(&alg_data->mif.complete);
 550
 551                 if (!(rc = alg_data->mif.ret))
 552                         completed++;
 553                 dev_dbg(&alg_data->adapter.dev,
 554                         "%s(): Complete, return code = %d.\n",
 555                         __func__, rc);
 556
 557                 /* Clear TDI and AFI bits in case they are set. */
 558                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
 559                         dev_dbg(&alg_data->adapter.dev,
 560                                 "%s: TDI still set... clearing now.\n",
 561                                 alg_data->adapter.name);
 562                         iowrite32(stat, I2C_REG_STS(alg_data));
 563                 }
 564                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
 565                         dev_dbg(&alg_data->adapter.dev,
 566                                 "%s: AFI still set... clearing now.\n",
 567                                 alg_data->adapter.name);
 568                         iowrite32(stat, I2C_REG_STS(alg_data));
 569                 }
 570         }
 571
 572         bus_reset_if_active(alg_data);
 573
 574         /* Cleanup to be sure... */
 575         alg_data->mif.buf = NULL;
 576         alg_data->mif.len = 0;
 577         alg_data->mif.order = 0;
 578
 579         dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
 580                 __func__, ioread32(I2C_REG_STS(alg_data)));
 581
 582         if (completed != num)
 583                 return ((rc < 0) ? rc : -EREMOTEIO);
 584
 585         return num;
 586 }
 587
 588 static u32 i2c_pnx_func(struct i2c_adapter *adapter)
 589 {
 590         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 591 }
 592
 593 static struct i2c_algorithm pnx_algorithm = {
 594         .master_xfer = i2c_pnx_xfer,
 595         .functionality = i2c_pnx_func,
 596 };
 597
 598 #ifdef CONFIG_PM_SLEEP
 599 static int i2c_pnx_controller_suspend(struct device *dev)
 600 {
 601         struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
 602
 603         clk_disable(alg_data->clk);
 604
 605         return 0;
 606 }
 607
 608 static int i2c_pnx_controller_resume(struct device *dev)
 609 {
 610         struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
 611
 612         return clk_enable(alg_data->clk);
 613 }
 614
 615 static SIMPLE_DEV_PM_OPS(i2c_pnx_pm,
 616                          i2c_pnx_controller_suspend, i2c_pnx_controller_resume);
 617 #define PNX_I2C_PM      (&i2c_pnx_pm)
 618 #else
 619 #define PNX_I2C_PM      NULL
 620 #endif
 621
 622 static int i2c_pnx_probe(struct platform_device *pdev)
 623 {
 624         unsigned long tmp;
 625         int ret = 0;
 626         struct i2c_pnx_algo_data *alg_data;
 627         unsigned long freq;
 628         struct resource *res;
 629         u32 speed = I2C_PNX_SPEED_KHZ_DEFAULT * 1000;
 630
 631         alg_data = devm_kzalloc(&pdev->dev, sizeof(*alg_data), GFP_KERNEL);
 632         if (!alg_data)
 633                 return -ENOMEM;
 634
 635         platform_set_drvdata(pdev, alg_data);
 636
 637         alg_data->adapter.dev.parent = &pdev->dev;
 638         alg_data->adapter.algo = &pnx_algorithm;
 639         alg_data->adapter.algo_data = alg_data;
 640         alg_data->adapter.nr = pdev->id;
 641
 642         alg_data->timeout = I2C_PNX_TIMEOUT_DEFAULT;
 643 #ifdef CONFIG_OF
 644         alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node);
 645         if (pdev->dev.of_node) {
 646                 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 647                                      &speed);
 648                 /*
 649                  * At this point, it is planned to add an OF timeout property.
 650                  * As soon as there is a consensus about how to call and handle
 651                  * this, sth. like the following can be put here:
 652                  *
 653                  * of_property_read_u32(pdev->dev.of_node, "timeout",
 654                  *                      &alg_data->timeout);
 655                  */
 656         }
 657 #endif
 658         alg_data->clk = devm_clk_get(&pdev->dev, NULL);
 659         if (IS_ERR(alg_data->clk))
 660                 return PTR_ERR(alg_data->clk);
 661
 662         init_timer(&alg_data->mif.timer);
 663         alg_data->mif.timer.function = i2c_pnx_timeout;
 664         alg_data->mif.timer.data = (unsigned long)alg_data;
 665
 666         snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name),
 667                  "%s", pdev->name);
 668
 669         /* Register I/O resource */
 670         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 671         alg_data->ioaddr = devm_ioremap_resource(&pdev->dev, res);
 672         if (IS_ERR(alg_data->ioaddr))
 673                 return PTR_ERR(alg_data->ioaddr);
 674
 675         ret = clk_enable(alg_data->clk);
 676         if (ret)
 677                 return ret;
 678
 679         freq = clk_get_rate(alg_data->clk);
 680
 681         /*
 682          * Clock Divisor High This value is the number of system clocks
 683          * the serial clock (SCL) will be high.
 684          * For example, if the system clock period is 50 ns and the maximum
 685          * desired serial period is 10000 ns (100 kHz), then CLKHI would be
 686          * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
 687          * programmed into CLKHI will vary from this slightly due to
 688          * variations in the output pad's rise and fall times as well as
 689          * the deglitching filter length.
 690          */
 691
 692         tmp = (freq / speed) / 2 - 2;
 693         if (tmp > 0x3FF)
 694                 tmp = 0x3FF;
 695         iowrite32(tmp, I2C_REG_CKH(alg_data));
 696         iowrite32(tmp, I2C_REG_CKL(alg_data));
 697
 698         iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
 699         if (wait_reset(alg_data)) {
 700                 ret = -ENODEV;
 701                 goto out_clock;
 702         }
 703         init_completion(&alg_data->mif.complete);
 704
 705         alg_data->irq = platform_get_irq(pdev, 0);
 706         if (alg_data->irq < 0) {
 707                 dev_err(&pdev->dev, "Failed to get IRQ from platform resource\n");
 708                 ret = alg_data->irq;
 709                 goto out_clock;
 710         }
 711         ret = devm_request_irq(&pdev->dev, alg_data->irq, i2c_pnx_interrupt,
 712                                0, pdev->name, alg_data);
 713         if (ret)
 714                 goto out_clock;
 715
 716         /* Register this adapter with the I2C subsystem */
 717         ret = i2c_add_numbered_adapter(&alg_data->adapter);
 718         if (ret < 0) {
 719                 dev_err(&pdev->dev, "I2C: Failed to add bus\n");
 720                 goto out_clock;
 721         }
 722
 723         dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
 724                 alg_data->adapter.name, res->start, alg_data->irq);
 725
 726         return 0;
 727
 728 out_clock:
 729         clk_disable(alg_data->clk);
 730         return ret;
 731 }
 732
 733 static int i2c_pnx_remove(struct platform_device *pdev)
 734 {
 735         struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
 736
 737         i2c_del_adapter(&alg_data->adapter);
 738         clk_disable(alg_data->clk);
 739
 740         return 0;
 741 }
 742
 743 #ifdef CONFIG_OF
 744 static const struct of_device_id i2c_pnx_of_match[] = {
 745         { .compatible = "nxp,pnx-i2c" },
 746         { },
 747 };
 748 MODULE_DEVICE_TABLE(of, i2c_pnx_of_match);
 749 #endif
 750
 751 static struct platform_driver i2c_pnx_driver = {
 752         .driver = {
 753                 .name = "pnx-i2c",
 754                 .owner = THIS_MODULE,
 755                 .of_match_table = of_match_ptr(i2c_pnx_of_match),
 756                 .pm = PNX_I2C_PM,
 757         },
 758         .probe = i2c_pnx_probe,
 759         .remove = i2c_pnx_remove,
 760 };
 761
 762 static int __init i2c_adap_pnx_init(void)
 763 {
 764         return platform_driver_register(&i2c_pnx_driver);
 765 }
 766
 767 static void __exit i2c_adap_pnx_exit(void)
 768 {
 769         platform_driver_unregister(&i2c_pnx_driver);
 770 }
 771
 772 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
 773 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
 774 MODULE_LICENSE("GPL");
 775 MODULE_ALIAS("platform:pnx-i2c");
 776
 777 /* We need to make sure I2C is initialized before USB */
 778 subsys_initcall(i2c_adap_pnx_init);
 779 module_exit(i2c_adap_pnx_exit);