drivers/irqchip/irq-versatile-fpga.c

   1 /*
   2  *  Support for Versatile FPGA-based IRQ controllers
   3  */
   4 #include <linux/bitops.h>
   5 #include <linux/irq.h>
   6 #include <linux/io.h>
   7 #include <linux/irqchip/versatile-fpga.h>
   8 #include <linux/irqdomain.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12 #include <linux/of_irq.h>
  13
  14 #include <asm/exception.h>
  15 #include <asm/mach/irq.h>
  16
  17 #define IRQ_STATUS              0x00
  18 #define IRQ_RAW_STATUS          0x04
  19 #define IRQ_ENABLE_SET          0x08
  20 #define IRQ_ENABLE_CLEAR        0x0c
  21 #define INT_SOFT_SET            0x10
  22 #define INT_SOFT_CLEAR          0x14
  23 #define FIQ_STATUS              0x20
  24 #define FIQ_RAW_STATUS          0x24
  25 #define FIQ_ENABLE              0x28
  26 #define FIQ_ENABLE_SET          0x28
  27 #define FIQ_ENABLE_CLEAR        0x2C
  28
  29 /**
  30  * struct fpga_irq_data - irq data container for the FPGA IRQ controller
  31  * @base: memory offset in virtual memory
  32  * @chip: chip container for this instance
  33  * @domain: IRQ domain for this instance
  34  * @valid: mask for valid IRQs on this controller
  35  * @used_irqs: number of active IRQs on this controller
  36  */
  37 struct fpga_irq_data {
  38         void __iomem *base;
  39         struct irq_chip chip;
  40         u32 valid;
  41         struct irq_domain *domain;
  42         u8 used_irqs;
  43 };
  44
  45 /* we cannot allocate memory when the controllers are initially registered */
  46 static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
  47 static int fpga_irq_id;
  48
  49 static void fpga_irq_mask(struct irq_data *d)
  50 {
  51         struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
  52         u32 mask = 1 << d->hwirq;
  53
  54         writel(mask, f->base + IRQ_ENABLE_CLEAR);
  55 }
  56
  57 static void fpga_irq_unmask(struct irq_data *d)
  58 {
  59         struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
  60         u32 mask = 1 << d->hwirq;
  61
  62         writel(mask, f->base + IRQ_ENABLE_SET);
  63 }
  64
  65 static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
  66 {
  67         struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
  68         u32 status = readl(f->base + IRQ_STATUS);
  69
  70         if (status == 0) {
  71                 do_bad_IRQ(irq, desc);
  72                 return;
  73         }
  74
  75         do {
  76                 irq = ffs(status) - 1;
  77                 status &= ~(1 << irq);
  78                 generic_handle_irq(irq_find_mapping(f->domain, irq));
  79         } while (status);
  80 }
  81
  82 /*
  83  * Handle each interrupt in a single FPGA IRQ controller.  Returns non-zero
  84  * if we've handled at least one interrupt.  This does a single read of the
  85  * status register and handles all interrupts in order from LSB first.
  86  */
  87 static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
  88 {
  89         int handled = 0;
  90         int irq;
  91         u32 status;
  92
  93         while ((status  = readl(f->base + IRQ_STATUS))) {
  94                 irq = ffs(status) - 1;
  95                 handle_IRQ(irq_find_mapping(f->domain, irq), regs);
  96                 handled = 1;
  97         }
  98
  99         return handled;
 100 }
 101
 102 /*
 103  * Keep iterating over all registered FPGA IRQ controllers until there are
 104  * no pending interrupts.
 105  */
 106 asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
 107 {
 108         int i, handled;
 109
 110         do {
 111                 for (i = 0, handled = 0; i < fpga_irq_id; ++i)
 112                         handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
 113         } while (handled);
 114 }
 115
 116 static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
 117                 irq_hw_number_t hwirq)
 118 {
 119         struct fpga_irq_data *f = d->host_data;
 120
 121         /* Skip invalid IRQs, only register handlers for the real ones */
 122         if (!(f->valid & BIT(hwirq)))
 123                 return -EPERM;
 124         irq_set_chip_data(irq, f);
 125         irq_set_chip_and_handler(irq, &f->chip,
 126                                 handle_level_irq);
 127         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 128         return 0;
 129 }
 130
 131 static struct irq_domain_ops fpga_irqdomain_ops = {
 132         .map = fpga_irqdomain_map,
 133         .xlate = irq_domain_xlate_onetwocell,
 134 };
 135
 136 void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
 137                           int parent_irq, u32 valid, struct device_node *node)
 138 {
 139         struct fpga_irq_data *f;
 140         int i;
 141
 142         if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
 143                 pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
 144                 return;
 145         }
 146         f = &fpga_irq_devices[fpga_irq_id];
 147         f->base = base;
 148         f->chip.name = name;
 149         f->chip.irq_ack = fpga_irq_mask;
 150         f->chip.irq_mask = fpga_irq_mask;
 151         f->chip.irq_unmask = fpga_irq_unmask;
 152         f->valid = valid;
 153
 154         if (parent_irq != -1) {
 155                 irq_set_handler_data(parent_irq, f);
 156                 irq_set_chained_handler(parent_irq, fpga_irq_handle);
 157         }
 158
 159         /* This will also allocate irq descriptors */
 160         f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
 161                                           &fpga_irqdomain_ops, f);
 162
 163         /* This will allocate all valid descriptors in the linear case */
 164         for (i = 0; i < fls(valid); i++)
 165                 if (valid & BIT(i)) {
 166                         if (!irq_start)
 167                                 irq_create_mapping(f->domain, i);
 168                         f->used_irqs++;
 169                 }
 170
 171         pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
 172                 fpga_irq_id, name, base, f->used_irqs);
 173         if (parent_irq != -1)
 174                 pr_cont(", parent IRQ: %d\n", parent_irq);
 175         else
 176                 pr_cont("\n");
 177
 178         fpga_irq_id++;
 179 }
 180
 181 #ifdef CONFIG_OF
 182 int __init fpga_irq_of_init(struct device_node *node,
 183                             struct device_node *parent)
 184 {
 185         void __iomem *base;
 186         u32 clear_mask;
 187         u32 valid_mask;
 188         int parent_irq;
 189
 190         if (WARN_ON(!node))
 191                 return -ENODEV;
 192
 193         base = of_iomap(node, 0);
 194         WARN(!base, "unable to map fpga irq registers\n");
 195
 196         if (of_property_read_u32(node, "clear-mask", &clear_mask))
 197                 clear_mask = 0;
 198
 199         if (of_property_read_u32(node, "valid-mask", &valid_mask))
 200                 valid_mask = 0;
 201
 202         /* Some chips are cascaded from a parent IRQ */
 203         parent_irq = irq_of_parse_and_map(node, 0);
 204         if (!parent_irq)
 205                 parent_irq = -1;
 206
 207         fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
 208
 209         writel(clear_mask, base + IRQ_ENABLE_CLEAR);
 210         writel(clear_mask, base + FIQ_ENABLE_CLEAR);
 211
 212         return 0;
 213 }
 214 #endif