drivers/irqchip/irq-vic.c

   1 /*
   2  *  linux/arch/arm/common/vic.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <linux/export.h>
  23 #include <linux/init.h>
  24 #include <linux/list.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/syscore_ops.h>
  32 #include <linux/device.h>
  33 #include <linux/amba/bus.h>
  34 #include <linux/irqchip/arm-vic.h>
  35
  36 #include <asm/exception.h>
  37 #include <asm/irq.h>
  38
  39 #include "irqchip.h"
  40
  41 #define VIC_IRQ_STATUS                  0x00
  42 #define VIC_FIQ_STATUS                  0x04
  43 #define VIC_INT_SELECT                  0x0c    /* 1 = FIQ, 0 = IRQ */
  44 #define VIC_INT_SOFT                    0x18
  45 #define VIC_INT_SOFT_CLEAR              0x1c
  46 #define VIC_PROTECT                     0x20
  47 #define VIC_PL190_VECT_ADDR             0x30    /* PL190 only */
  48 #define VIC_PL190_DEF_VECT_ADDR         0x34    /* PL190 only */
  49
  50 #define VIC_VECT_ADDR0                  0x100   /* 0 to 15 (0..31 PL192) */
  51 #define VIC_VECT_CNTL0                  0x200   /* 0 to 15 (0..31 PL192) */
  52 #define VIC_ITCR                        0x300   /* VIC test control register */
  53
  54 #define VIC_VECT_CNTL_ENABLE            (1 << 5)
  55
  56 #define VIC_PL192_VECT_ADDR             0xF00
  57
  58 /**
  59  * struct vic_device - VIC PM device
  60  * @irq: The IRQ number for the base of the VIC.
  61  * @base: The register base for the VIC.
  62  * @valid_sources: A bitmask of valid interrupts
  63  * @resume_sources: A bitmask of interrupts for resume.
  64  * @resume_irqs: The IRQs enabled for resume.
  65  * @int_select: Save for VIC_INT_SELECT.
  66  * @int_enable: Save for VIC_INT_ENABLE.
  67  * @soft_int: Save for VIC_INT_SOFT.
  68  * @protect: Save for VIC_PROTECT.
  69  * @domain: The IRQ domain for the VIC.
  70  */
  71 struct vic_device {
  72         void __iomem    *base;
  73         int             irq;
  74         u32             valid_sources;
  75         u32             resume_sources;
  76         u32             resume_irqs;
  77         u32             int_select;
  78         u32             int_enable;
  79         u32             soft_int;
  80         u32             protect;
  81         struct irq_domain *domain;
  82 };
  83
  84 /* we cannot allocate memory when VICs are initially registered */
  85 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
  86
  87 static int vic_id;
  88
  89 static void vic_handle_irq(struct pt_regs *regs);
  90
  91 /**
  92  * vic_init2 - common initialisation code
  93  * @base: Base of the VIC.
  94  *
  95  * Common initialisation code for registration
  96  * and resume.
  97 */
  98 static void vic_init2(void __iomem *base)
  99 {
 100         int i;
 101
 102         for (i = 0; i < 16; i++) {
 103                 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
 104                 writel(VIC_VECT_CNTL_ENABLE | i, reg);
 105         }
 106
 107         writel(32, base + VIC_PL190_DEF_VECT_ADDR);
 108 }
 109
 110 #ifdef CONFIG_PM
 111 static void resume_one_vic(struct vic_device *vic)
 112 {
 113         void __iomem *base = vic->base;
 114
 115         printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
 116
 117         /* re-initialise static settings */
 118         vic_init2(base);
 119
 120         writel(vic->int_select, base + VIC_INT_SELECT);
 121         writel(vic->protect, base + VIC_PROTECT);
 122
 123         /* set the enabled ints and then clear the non-enabled */
 124         writel(vic->int_enable, base + VIC_INT_ENABLE);
 125         writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
 126
 127         /* and the same for the soft-int register */
 128
 129         writel(vic->soft_int, base + VIC_INT_SOFT);
 130         writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
 131 }
 132
 133 static void vic_resume(void)
 134 {
 135         int id;
 136
 137         for (id = vic_id - 1; id >= 0; id--)
 138                 resume_one_vic(vic_devices + id);
 139 }
 140
 141 static void suspend_one_vic(struct vic_device *vic)
 142 {
 143         void __iomem *base = vic->base;
 144
 145         printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
 146
 147         vic->int_select = readl(base + VIC_INT_SELECT);
 148         vic->int_enable = readl(base + VIC_INT_ENABLE);
 149         vic->soft_int = readl(base + VIC_INT_SOFT);
 150         vic->protect = readl(base + VIC_PROTECT);
 151
 152         /* set the interrupts (if any) that are used for
 153          * resuming the system */
 154
 155         writel(vic->resume_irqs, base + VIC_INT_ENABLE);
 156         writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
 157 }
 158
 159 static int vic_suspend(void)
 160 {
 161         int id;
 162
 163         for (id = 0; id < vic_id; id++)
 164                 suspend_one_vic(vic_devices + id);
 165
 166         return 0;
 167 }
 168
 169 struct syscore_ops vic_syscore_ops = {
 170         .suspend        = vic_suspend,
 171         .resume         = vic_resume,
 172 };
 173
 174 /**
 175  * vic_pm_init - initicall to register VIC pm
 176  *
 177  * This is called via late_initcall() to register
 178  * the resources for the VICs due to the early
 179  * nature of the VIC's registration.
 180 */
 181 static int __init vic_pm_init(void)
 182 {
 183         if (vic_id > 0)
 184                 register_syscore_ops(&vic_syscore_ops);
 185
 186         return 0;
 187 }
 188 late_initcall(vic_pm_init);
 189 #endif /* CONFIG_PM */
 190
 191 static struct irq_chip vic_chip;
 192
 193 static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 194                              irq_hw_number_t hwirq)
 195 {
 196         struct vic_device *v = d->host_data;
 197
 198         /* Skip invalid IRQs, only register handlers for the real ones */
 199         if (!(v->valid_sources & (1 << hwirq)))
 200                 return -EPERM;
 201         irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
 202         irq_set_chip_data(irq, v->base);
 203         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 204         return 0;
 205 }
 206
 207 /*
 208  * Handle each interrupt in a single VIC.  Returns non-zero if we've
 209  * handled at least one interrupt.  This reads the status register
 210  * before handling each interrupt, which is necessary given that
 211  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 212  */
 213 static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
 214 {
 215         u32 stat, irq;
 216         int handled = 0;
 217
 218         while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
 219                 irq = ffs(stat) - 1;
 220                 handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
 221                 handled = 1;
 222         }
 223
 224         return handled;
 225 }
 226
 227 /*
 228  * Keep iterating over all registered VIC's until there are no pending
 229  * interrupts.
 230  */
 231 static asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
 232 {
 233         int i, handled;
 234
 235         do {
 236                 for (i = 0, handled = 0; i < vic_id; ++i)
 237                         handled |= handle_one_vic(&vic_devices[i], regs);
 238         } while (handled);
 239 }
 240
 241 static struct irq_domain_ops vic_irqdomain_ops = {
 242         .map = vic_irqdomain_map,
 243         .xlate = irq_domain_xlate_onetwocell,
 244 };
 245
 246 /**
 247  * vic_register() - Register a VIC.
 248  * @base: The base address of the VIC.
 249  * @irq: The base IRQ for the VIC.
 250  * @valid_sources: bitmask of valid interrupts
 251  * @resume_sources: bitmask of interrupts allowed for resume sources.
 252  * @node: The device tree node associated with the VIC.
 253  *
 254  * Register the VIC with the system device tree so that it can be notified
 255  * of suspend and resume requests and ensure that the correct actions are
 256  * taken to re-instate the settings on resume.
 257  *
 258  * This also configures the IRQ domain for the VIC.
 259  */
 260 static void __init vic_register(void __iomem *base, unsigned int irq,
 261                                 u32 valid_sources, u32 resume_sources,
 262                                 struct device_node *node)
 263 {
 264         struct vic_device *v;
 265         int i;
 266
 267         if (vic_id >= ARRAY_SIZE(vic_devices)) {
 268                 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
 269                 return;
 270         }
 271
 272         v = &vic_devices[vic_id];
 273         v->base = base;
 274         v->valid_sources = valid_sources;
 275         v->resume_sources = resume_sources;
 276         v->irq = irq;
 277         set_handle_irq(vic_handle_irq);
 278         vic_id++;
 279         v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
 280                                           &vic_irqdomain_ops, v);
 281         /* create an IRQ mapping for each valid IRQ */
 282         for (i = 0; i < fls(valid_sources); i++)
 283                 if (valid_sources & (1 << i))
 284                         irq_create_mapping(v->domain, i);
 285 }
 286
 287 static void vic_ack_irq(struct irq_data *d)
 288 {
 289         void __iomem *base = irq_data_get_irq_chip_data(d);
 290         unsigned int irq = d->hwirq;
 291         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 292         /* moreover, clear the soft-triggered, in case it was the reason */
 293         writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
 294 }
 295
 296 static void vic_mask_irq(struct irq_data *d)
 297 {
 298         void __iomem *base = irq_data_get_irq_chip_data(d);
 299         unsigned int irq = d->hwirq;
 300         writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 301 }
 302
 303 static void vic_unmask_irq(struct irq_data *d)
 304 {
 305         void __iomem *base = irq_data_get_irq_chip_data(d);
 306         unsigned int irq = d->hwirq;
 307         writel(1 << irq, base + VIC_INT_ENABLE);
 308 }
 309
 310 #if defined(CONFIG_PM)
 311 static struct vic_device *vic_from_irq(unsigned int irq)
 312 {
 313         struct vic_device *v = vic_devices;
 314         unsigned int base_irq = irq & ~31;
 315         int id;
 316
 317         for (id = 0; id < vic_id; id++, v++) {
 318                 if (v->irq == base_irq)
 319                         return v;
 320         }
 321
 322         return NULL;
 323 }
 324
 325 static int vic_set_wake(struct irq_data *d, unsigned int on)
 326 {
 327         struct vic_device *v = vic_from_irq(d->irq);
 328         unsigned int off = d->hwirq;
 329         u32 bit = 1 << off;
 330
 331         if (!v)
 332                 return -EINVAL;
 333
 334         if (!(bit & v->resume_sources))
 335                 return -EINVAL;
 336
 337         if (on)
 338                 v->resume_irqs |= bit;
 339         else
 340                 v->resume_irqs &= ~bit;
 341
 342         return 0;
 343 }
 344 #else
 345 #define vic_set_wake NULL
 346 #endif /* CONFIG_PM */
 347
 348 static struct irq_chip vic_chip = {
 349         .name           = "VIC",
 350         .irq_ack        = vic_ack_irq,
 351         .irq_mask       = vic_mask_irq,
 352         .irq_unmask     = vic_unmask_irq,
 353         .irq_set_wake   = vic_set_wake,
 354 };
 355
 356 static void __init vic_disable(void __iomem *base)
 357 {
 358         writel(0, base + VIC_INT_SELECT);
 359         writel(0, base + VIC_INT_ENABLE);
 360         writel(~0, base + VIC_INT_ENABLE_CLEAR);
 361         writel(0, base + VIC_ITCR);
 362         writel(~0, base + VIC_INT_SOFT_CLEAR);
 363 }
 364
 365 static void __init vic_clear_interrupts(void __iomem *base)
 366 {
 367         unsigned int i;
 368
 369         writel(0, base + VIC_PL190_VECT_ADDR);
 370         for (i = 0; i < 19; i++) {
 371                 unsigned int value;
 372
 373                 value = readl(base + VIC_PL190_VECT_ADDR);
 374                 writel(value, base + VIC_PL190_VECT_ADDR);
 375         }
 376 }
 377
 378 /*
 379  * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
 380  * The original cell has 32 interrupts, while the modified one has 64,
 381  * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
 382  * the probe function is called twice, with base set to offset 000
 383  *  and 020 within the page. We call this "second block".
 384  */
 385 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
 386                                u32 vic_sources, struct device_node *node)
 387 {
 388         unsigned int i;
 389         int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
 390
 391         /* Disable all interrupts initially. */
 392         vic_disable(base);
 393
 394         /*
 395          * Make sure we clear all existing interrupts. The vector registers
 396          * in this cell are after the second block of general registers,
 397          * so we can address them using standard offsets, but only from
 398          * the second base address, which is 0x20 in the page
 399          */
 400         if (vic_2nd_block) {
 401                 vic_clear_interrupts(base);
 402
 403                 /* ST has 16 vectors as well, but we don't enable them by now */
 404                 for (i = 0; i < 16; i++) {
 405                         void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
 406                         writel(0, reg);
 407                 }
 408
 409                 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
 410         }
 411
 412         vic_register(base, irq_start, vic_sources, 0, node);
 413 }
 414
 415 void __init __vic_init(void __iomem *base, int irq_start,
 416                               u32 vic_sources, u32 resume_sources,
 417                               struct device_node *node)
 418 {
 419         unsigned int i;
 420         u32 cellid = 0;
 421         enum amba_vendor vendor;
 422
 423         /* Identify which VIC cell this one is, by reading the ID */
 424         for (i = 0; i < 4; i++) {
 425                 void __iomem *addr;
 426                 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
 427                 cellid |= (readl(addr) & 0xff) << (8 * i);
 428         }
 429         vendor = (cellid >> 12) & 0xff;
 430         printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
 431                base, cellid, vendor);
 432
 433         switch(vendor) {
 434         case AMBA_VENDOR_ST:
 435                 vic_init_st(base, irq_start, vic_sources, node);
 436                 return;
 437         default:
 438                 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
 439                 /* fall through */
 440         case AMBA_VENDOR_ARM:
 441                 break;
 442         }
 443
 444         /* Disable all interrupts initially. */
 445         vic_disable(base);
 446
 447         /* Make sure we clear all existing interrupts */
 448         vic_clear_interrupts(base);
 449
 450         vic_init2(base);
 451
 452         vic_register(base, irq_start, vic_sources, resume_sources, node);
 453 }
 454
 455 /**
 456  * vic_init() - initialise a vectored interrupt controller
 457  * @base: iomem base address
 458  * @irq_start: starting interrupt number, must be muliple of 32
 459  * @vic_sources: bitmask of interrupt sources to allow
 460  * @resume_sources: bitmask of interrupt sources to allow for resume
 461  */
 462 void __init vic_init(void __iomem *base, unsigned int irq_start,
 463                      u32 vic_sources, u32 resume_sources)
 464 {
 465         __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
 466 }
 467
 468 #ifdef CONFIG_OF
 469 int __init vic_of_init(struct device_node *node, struct device_node *parent)
 470 {
 471         void __iomem *regs;
 472         u32 interrupt_mask = ~0;
 473         u32 wakeup_mask = ~0;
 474
 475         if (WARN(parent, "non-root VICs are not supported"))
 476                 return -EINVAL;
 477
 478         regs = of_iomap(node, 0);
 479         if (WARN_ON(!regs))
 480                 return -EIO;
 481
 482         of_property_read_u32(node, "valid-mask", &interrupt_mask);
 483         of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
 484
 485         /*
 486          * Passing 0 as first IRQ makes the simple domain allocate descriptors
 487          */
 488         __vic_init(regs, 0, interrupt_mask, wakeup_mask, node);
 489
 490         return 0;
 491 }
 492 IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init);
 493 IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init);
 494 IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init);
 495 #endif /* CONFIG OF */