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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / dvb-frontends / af9033.c
blob65728c25ea05adcd50bd658c96a6c54dd6fb569b
1 /*
2 * Afatech AF9033 demodulator driver
3 *
4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
5 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22 #include "af9033_priv.h"
23
24 /* Max transfer size done by I2C transfer functions */
25 #define MAX_XFER_SIZE 64
26
27 struct af9033_state {
28 struct i2c_adapter *i2c;
29 struct dvb_frontend fe;
30 struct af9033_config cfg;
31
32 u32 bandwidth_hz;
33 bool ts_mode_parallel;
34 bool ts_mode_serial;
35
36 u32 ber;
37 u32 ucb;
38 unsigned long last_stat_check;
39 };
40
41 /* write multiple registers */
42 static int af9033_wr_regs(struct af9033_state *state, u32 reg, const u8 *val,
43 int len)
44 {
45 int ret;
46 u8 buf[MAX_XFER_SIZE];
47 struct i2c_msg msg[1] = {
48 {
49 .addr = state->cfg.i2c_addr,
50 .flags = 0,
51 .len = 3 + len,
52 .buf = buf,
53 }
54 };
55
56 if (3 + len > sizeof(buf)) {
57 dev_warn(&state->i2c->dev,
58 "%s: i2c wr reg=%04x: len=%d is too big!\n",
59 KBUILD_MODNAME, reg, len);
60 return -EINVAL;
61 }
62
63 buf[0] = (reg >> 16) & 0xff;
64 buf[1] = (reg >> 8) & 0xff;
65 buf[2] = (reg >> 0) & 0xff;
66 memcpy(&buf[3], val, len);
67
68 ret = i2c_transfer(state->i2c, msg, 1);
69 if (ret == 1) {
70 ret = 0;
71 } else {
72 dev_warn(&state->i2c->dev, "%s: i2c wr failed=%d reg=%06x " \
73 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
74 ret = -EREMOTEIO;
75 }
76
77 return ret;
78 }
79
80 /* read multiple registers */
81 static int af9033_rd_regs(struct af9033_state *state, u32 reg, u8 *val, int len)
82 {
83 int ret;
84 u8 buf[3] = { (reg >> 16) & 0xff, (reg >> 8) & 0xff,
85 (reg >> 0) & 0xff };
86 struct i2c_msg msg[2] = {
87 {
88 .addr = state->cfg.i2c_addr,
89 .flags = 0,
90 .len = sizeof(buf),
91 .buf = buf
92 }, {
93 .addr = state->cfg.i2c_addr,
94 .flags = I2C_M_RD,
95 .len = len,
96 .buf = val
97 }
98 };
99
100 ret = i2c_transfer(state->i2c, msg, 2);
101 if (ret == 2) {
102 ret = 0;
103 } else {
104 dev_warn(&state->i2c->dev, "%s: i2c rd failed=%d reg=%06x " \
105 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
106 ret = -EREMOTEIO;
107 }
108
109 return ret;
110 }
111
112
113 /* write single register */
114 static int af9033_wr_reg(struct af9033_state *state, u32 reg, u8 val)
115 {
116 return af9033_wr_regs(state, reg, &val, 1);
117 }
118
119 /* read single register */
120 static int af9033_rd_reg(struct af9033_state *state, u32 reg, u8 *val)
121 {
122 return af9033_rd_regs(state, reg, val, 1);
123 }
124
125 /* write single register with mask */
126 static int af9033_wr_reg_mask(struct af9033_state *state, u32 reg, u8 val,
127 u8 mask)
128 {
129 int ret;
130 u8 tmp;
131
132 /* no need for read if whole reg is written */
133 if (mask != 0xff) {
134 ret = af9033_rd_regs(state, reg, &tmp, 1);
135 if (ret)
136 return ret;
137
138 val &= mask;
139 tmp &= ~mask;
140 val |= tmp;
141 }
142
143 return af9033_wr_regs(state, reg, &val, 1);
144 }
145
146 /* read single register with mask */
147 static int af9033_rd_reg_mask(struct af9033_state *state, u32 reg, u8 *val,
148 u8 mask)
149 {
150 int ret, i;
151 u8 tmp;
152
153 ret = af9033_rd_regs(state, reg, &tmp, 1);
154 if (ret)
155 return ret;
156
157 tmp &= mask;
158
159 /* find position of the first bit */
160 for (i = 0; i < 8; i++) {
161 if ((mask >> i) & 0x01)
162 break;
163 }
164 *val = tmp >> i;
165
166 return 0;
167 }
168
169 /* write reg val table using reg addr auto increment */
170 static int af9033_wr_reg_val_tab(struct af9033_state *state,
171 const struct reg_val *tab, int tab_len)
172 {
173 #define MAX_TAB_LEN 212
174 int ret, i, j;
175 u8 buf[1 + MAX_TAB_LEN];
176
177 dev_dbg(&state->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
178
179 if (tab_len > sizeof(buf)) {
180 dev_warn(&state->i2c->dev, "%s: tab len %d is too big\n",
181 KBUILD_MODNAME, tab_len);
182 return -EINVAL;
183 }
184
185 for (i = 0, j = 0; i < tab_len; i++) {
186 buf[j] = tab[i].val;
187
188 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
189 ret = af9033_wr_regs(state, tab[i].reg - j, buf, j + 1);
190 if (ret < 0)
191 goto err;
192
193 j = 0;
194 } else {
195 j++;
196 }
197 }
198
199 return 0;
200
201 err:
202 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
203
204 return ret;
205 }
206
207 static u32 af9033_div(struct af9033_state *state, u32 a, u32 b, u32 x)
208 {
209 u32 r = 0, c = 0, i;
210
211 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d\n", __func__, a, b, x);
212
213 if (a > b) {
214 c = a / b;
215 a = a - c * b;
216 }
217
218 for (i = 0; i < x; i++) {
219 if (a >= b) {
220 r += 1;
221 a -= b;
222 }
223 a <<= 1;
224 r <<= 1;
225 }
226 r = (c << (u32)x) + r;
227
228 dev_dbg(&state->i2c->dev, "%s: a=%d b=%d x=%d r=%d r=%x\n",
229 __func__, a, b, x, r, r);
230
231 return r;
232 }
233
234 static void af9033_release(struct dvb_frontend *fe)
235 {
236 struct af9033_state *state = fe->demodulator_priv;
237
238 kfree(state);
239 }
240
241 static int af9033_init(struct dvb_frontend *fe)
242 {
243 struct af9033_state *state = fe->demodulator_priv;
244 int ret, i, len;
245 const struct reg_val *init;
246 u8 buf[4];
247 u32 adc_cw, clock_cw;
248 struct reg_val_mask tab[] = {
249 { 0x80fb24, 0x00, 0x08 },
250 { 0x80004c, 0x00, 0xff },
251 { 0x00f641, state->cfg.tuner, 0xff },
252 { 0x80f5ca, 0x01, 0x01 },
253 { 0x80f715, 0x01, 0x01 },
254 { 0x00f41f, 0x04, 0x04 },
255 { 0x00f41a, 0x01, 0x01 },
256 { 0x80f731, 0x00, 0x01 },
257 { 0x00d91e, 0x00, 0x01 },
258 { 0x00d919, 0x00, 0x01 },
259 { 0x80f732, 0x00, 0x01 },
260 { 0x00d91f, 0x00, 0x01 },
261 { 0x00d91a, 0x00, 0x01 },
262 { 0x80f730, 0x00, 0x01 },
263 { 0x80f778, 0x00, 0xff },
264 { 0x80f73c, 0x01, 0x01 },
265 { 0x80f776, 0x00, 0x01 },
266 { 0x00d8fd, 0x01, 0xff },
267 { 0x00d830, 0x01, 0xff },
268 { 0x00d831, 0x00, 0xff },
269 { 0x00d832, 0x00, 0xff },
270 { 0x80f985, state->ts_mode_serial, 0x01 },
271 { 0x80f986, state->ts_mode_parallel, 0x01 },
272 { 0x00d827, 0x00, 0xff },
273 { 0x00d829, 0x00, 0xff },
274 { 0x800045, state->cfg.adc_multiplier, 0xff },
275 };
276
277 /* program clock control */
278 clock_cw = af9033_div(state, state->cfg.clock, 1000000ul, 19ul);
279 buf[0] = (clock_cw >> 0) & 0xff;
280 buf[1] = (clock_cw >> 8) & 0xff;
281 buf[2] = (clock_cw >> 16) & 0xff;
282 buf[3] = (clock_cw >> 24) & 0xff;
283
284 dev_dbg(&state->i2c->dev, "%s: clock=%d clock_cw=%08x\n",
285 __func__, state->cfg.clock, clock_cw);
286
287 ret = af9033_wr_regs(state, 0x800025, buf, 4);
288 if (ret < 0)
289 goto err;
290
291 /* program ADC control */
292 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
293 if (clock_adc_lut[i].clock == state->cfg.clock)
294 break;
295 }
296
297 adc_cw = af9033_div(state, clock_adc_lut[i].adc, 1000000ul, 19ul);
298 buf[0] = (adc_cw >> 0) & 0xff;
299 buf[1] = (adc_cw >> 8) & 0xff;
300 buf[2] = (adc_cw >> 16) & 0xff;
301
302 dev_dbg(&state->i2c->dev, "%s: adc=%d adc_cw=%06x\n",
303 __func__, clock_adc_lut[i].adc, adc_cw);
304
305 ret = af9033_wr_regs(state, 0x80f1cd, buf, 3);
306 if (ret < 0)
307 goto err;
308
309 /* program register table */
310 for (i = 0; i < ARRAY_SIZE(tab); i++) {
311 ret = af9033_wr_reg_mask(state, tab[i].reg, tab[i].val,
312 tab[i].mask);
313 if (ret < 0)
314 goto err;
315 }
316
317 /* settings for TS interface */
318 if (state->cfg.ts_mode == AF9033_TS_MODE_USB) {
319 ret = af9033_wr_reg_mask(state, 0x80f9a5, 0x00, 0x01);
320 if (ret < 0)
321 goto err;
322
323 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x01, 0x01);
324 if (ret < 0)
325 goto err;
326 } else {
327 ret = af9033_wr_reg_mask(state, 0x80f990, 0x00, 0x01);
328 if (ret < 0)
329 goto err;
330
331 ret = af9033_wr_reg_mask(state, 0x80f9b5, 0x00, 0x01);
332 if (ret < 0)
333 goto err;
334 }
335
336 /* load OFSM settings */
337 dev_dbg(&state->i2c->dev, "%s: load ofsm settings\n", __func__);
338 switch (state->cfg.tuner) {
339 case AF9033_TUNER_IT9135_38:
340 case AF9033_TUNER_IT9135_51:
341 case AF9033_TUNER_IT9135_52:
342 len = ARRAY_SIZE(ofsm_init_it9135_v1);
343 init = ofsm_init_it9135_v1;
344 break;
345 case AF9033_TUNER_IT9135_60:
346 case AF9033_TUNER_IT9135_61:
347 case AF9033_TUNER_IT9135_62:
348 len = ARRAY_SIZE(ofsm_init_it9135_v2);
349 init = ofsm_init_it9135_v2;
350 break;
351 default:
352 len = ARRAY_SIZE(ofsm_init);
353 init = ofsm_init;
354 break;
355 }
356
357 ret = af9033_wr_reg_val_tab(state, init, len);
358 if (ret < 0)
359 goto err;
360
361 /* load tuner specific settings */
362 dev_dbg(&state->i2c->dev, "%s: load tuner specific settings\n",
363 __func__);
364 switch (state->cfg.tuner) {
365 case AF9033_TUNER_TUA9001:
366 len = ARRAY_SIZE(tuner_init_tua9001);
367 init = tuner_init_tua9001;
368 break;
369 case AF9033_TUNER_FC0011:
370 len = ARRAY_SIZE(tuner_init_fc0011);
371 init = tuner_init_fc0011;
372 break;
373 case AF9033_TUNER_MXL5007T:
374 len = ARRAY_SIZE(tuner_init_mxl5007t);
375 init = tuner_init_mxl5007t;
376 break;
377 case AF9033_TUNER_TDA18218:
378 len = ARRAY_SIZE(tuner_init_tda18218);
379 init = tuner_init_tda18218;
380 break;
381 case AF9033_TUNER_FC2580:
382 len = ARRAY_SIZE(tuner_init_fc2580);
383 init = tuner_init_fc2580;
384 break;
385 case AF9033_TUNER_FC0012:
386 len = ARRAY_SIZE(tuner_init_fc0012);
387 init = tuner_init_fc0012;
388 break;
389 case AF9033_TUNER_IT9135_38:
390 len = ARRAY_SIZE(tuner_init_it9135_38);
391 init = tuner_init_it9135_38;
392 break;
393 case AF9033_TUNER_IT9135_51:
394 len = ARRAY_SIZE(tuner_init_it9135_51);
395 init = tuner_init_it9135_51;
396 break;
397 case AF9033_TUNER_IT9135_52:
398 len = ARRAY_SIZE(tuner_init_it9135_52);
399 init = tuner_init_it9135_52;
400 break;
401 case AF9033_TUNER_IT9135_60:
402 len = ARRAY_SIZE(tuner_init_it9135_60);
403 init = tuner_init_it9135_60;
404 break;
405 case AF9033_TUNER_IT9135_61:
406 len = ARRAY_SIZE(tuner_init_it9135_61);
407 init = tuner_init_it9135_61;
408 break;
409 case AF9033_TUNER_IT9135_62:
410 len = ARRAY_SIZE(tuner_init_it9135_62);
411 init = tuner_init_it9135_62;
412 break;
413 default:
414 dev_dbg(&state->i2c->dev, "%s: unsupported tuner ID=%d\n",
415 __func__, state->cfg.tuner);
416 ret = -ENODEV;
417 goto err;
418 }
419
420 ret = af9033_wr_reg_val_tab(state, init, len);
421 if (ret < 0)
422 goto err;
423
424 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
425 ret = af9033_wr_reg_mask(state, 0x00d91c, 0x01, 0x01);
426 if (ret < 0)
427 goto err;
428
429 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01);
430 if (ret < 0)
431 goto err;
432
433 ret = af9033_wr_reg_mask(state, 0x00d916, 0x00, 0x01);
434 if (ret < 0)
435 goto err;
436 }
437
438 switch (state->cfg.tuner) {
439 case AF9033_TUNER_IT9135_60:
440 case AF9033_TUNER_IT9135_61:
441 case AF9033_TUNER_IT9135_62:
442 ret = af9033_wr_reg(state, 0x800000, 0x01);
443 if (ret < 0)
444 goto err;
445 }
446
447 state->bandwidth_hz = 0; /* force to program all parameters */
448
449 return 0;
450
451 err:
452 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
453
454 return ret;
455 }
456
457 static int af9033_sleep(struct dvb_frontend *fe)
458 {
459 struct af9033_state *state = fe->demodulator_priv;
460 int ret, i;
461 u8 tmp;
462
463 ret = af9033_wr_reg(state, 0x80004c, 1);
464 if (ret < 0)
465 goto err;
466
467 ret = af9033_wr_reg(state, 0x800000, 0);
468 if (ret < 0)
469 goto err;
470
471 for (i = 100, tmp = 1; i && tmp; i--) {
472 ret = af9033_rd_reg(state, 0x80004c, &tmp);
473 if (ret < 0)
474 goto err;
475
476 usleep_range(200, 10000);
477 }
478
479 dev_dbg(&state->i2c->dev, "%s: loop=%d\n", __func__, i);
480
481 if (i == 0) {
482 ret = -ETIMEDOUT;
483 goto err;
484 }
485
486 ret = af9033_wr_reg_mask(state, 0x80fb24, 0x08, 0x08);
487 if (ret < 0)
488 goto err;
489
490 /* prevent current leak (?) */
491 if (state->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
492 /* enable parallel TS */
493 ret = af9033_wr_reg_mask(state, 0x00d917, 0x00, 0x01);
494 if (ret < 0)
495 goto err;
496
497 ret = af9033_wr_reg_mask(state, 0x00d916, 0x01, 0x01);
498 if (ret < 0)
499 goto err;
500 }
501
502 return 0;
503
504 err:
505 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
506
507 return ret;
508 }
509
510 static int af9033_get_tune_settings(struct dvb_frontend *fe,
511 struct dvb_frontend_tune_settings *fesettings)
512 {
513 /* 800 => 2000 because IT9135 v2 is slow to gain lock */
514 fesettings->min_delay_ms = 2000;
515 fesettings->step_size = 0;
516 fesettings->max_drift = 0;
517
518 return 0;
519 }
520
521 static int af9033_set_frontend(struct dvb_frontend *fe)
522 {
523 struct af9033_state *state = fe->demodulator_priv;
524 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
525 int ret, i, spec_inv, sampling_freq;
526 u8 tmp, buf[3], bandwidth_reg_val;
527 u32 if_frequency, freq_cw, adc_freq;
528
529 dev_dbg(&state->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n",
530 __func__, c->frequency, c->bandwidth_hz);
531
532 /* check bandwidth */
533 switch (c->bandwidth_hz) {
534 case 6000000:
535 bandwidth_reg_val = 0x00;
536 break;
537 case 7000000:
538 bandwidth_reg_val = 0x01;
539 break;
540 case 8000000:
541 bandwidth_reg_val = 0x02;
542 break;
543 default:
544 dev_dbg(&state->i2c->dev, "%s: invalid bandwidth_hz\n",
545 __func__);
546 ret = -EINVAL;
547 goto err;
548 }
549
550 /* program tuner */
551 if (fe->ops.tuner_ops.set_params)
552 fe->ops.tuner_ops.set_params(fe);
553
554 /* program CFOE coefficients */
555 if (c->bandwidth_hz != state->bandwidth_hz) {
556 for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
557 if (coeff_lut[i].clock == state->cfg.clock &&
558 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
559 break;
560 }
561 }
562 ret = af9033_wr_regs(state, 0x800001,
563 coeff_lut[i].val, sizeof(coeff_lut[i].val));
564 }
565
566 /* program frequency control */
567 if (c->bandwidth_hz != state->bandwidth_hz) {
568 spec_inv = state->cfg.spec_inv ? -1 : 1;
569
570 for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
571 if (clock_adc_lut[i].clock == state->cfg.clock)
572 break;
573 }
574 adc_freq = clock_adc_lut[i].adc;
575
576 /* get used IF frequency */
577 if (fe->ops.tuner_ops.get_if_frequency)
578 fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
579 else
580 if_frequency = 0;
581
582 sampling_freq = if_frequency;
583
584 while (sampling_freq > (adc_freq / 2))
585 sampling_freq -= adc_freq;
586
587 if (sampling_freq >= 0)
588 spec_inv *= -1;
589 else
590 sampling_freq *= -1;
591
592 freq_cw = af9033_div(state, sampling_freq, adc_freq, 23ul);
593
594 if (spec_inv == -1)
595 freq_cw = 0x800000 - freq_cw;
596
597 if (state->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
598 freq_cw /= 2;
599
600 buf[0] = (freq_cw >> 0) & 0xff;
601 buf[1] = (freq_cw >> 8) & 0xff;
602 buf[2] = (freq_cw >> 16) & 0x7f;
603
604 /* FIXME: there seems to be calculation error here... */
605 if (if_frequency == 0)
606 buf[2] = 0;
607
608 ret = af9033_wr_regs(state, 0x800029, buf, 3);
609 if (ret < 0)
610 goto err;
611
612 state->bandwidth_hz = c->bandwidth_hz;
613 }
614
615 ret = af9033_wr_reg_mask(state, 0x80f904, bandwidth_reg_val, 0x03);
616 if (ret < 0)
617 goto err;
618
619 ret = af9033_wr_reg(state, 0x800040, 0x00);
620 if (ret < 0)
621 goto err;
622
623 ret = af9033_wr_reg(state, 0x800047, 0x00);
624 if (ret < 0)
625 goto err;
626
627 ret = af9033_wr_reg_mask(state, 0x80f999, 0x00, 0x01);
628 if (ret < 0)
629 goto err;
630
631 if (c->frequency <= 230000000)
632 tmp = 0x00; /* VHF */
633 else
634 tmp = 0x01; /* UHF */
635
636 ret = af9033_wr_reg(state, 0x80004b, tmp);
637 if (ret < 0)
638 goto err;
639
640 ret = af9033_wr_reg(state, 0x800000, 0x00);
641 if (ret < 0)
642 goto err;
643
644 return 0;
645
646 err:
647 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
648
649 return ret;
650 }
651
652 static int af9033_get_frontend(struct dvb_frontend *fe)
653 {
654 struct af9033_state *state = fe->demodulator_priv;
655 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
656 int ret;
657 u8 buf[8];
658
659 dev_dbg(&state->i2c->dev, "%s:\n", __func__);
660
661 /* read all needed registers */
662 ret = af9033_rd_regs(state, 0x80f900, buf, sizeof(buf));
663 if (ret < 0)
664 goto err;
665
666 switch ((buf[0] >> 0) & 3) {
667 case 0:
668 c->transmission_mode = TRANSMISSION_MODE_2K;
669 break;
670 case 1:
671 c->transmission_mode = TRANSMISSION_MODE_8K;
672 break;
673 }
674
675 switch ((buf[1] >> 0) & 3) {
676 case 0:
677 c->guard_interval = GUARD_INTERVAL_1_32;
678 break;
679 case 1:
680 c->guard_interval = GUARD_INTERVAL_1_16;
681 break;
682 case 2:
683 c->guard_interval = GUARD_INTERVAL_1_8;
684 break;
685 case 3:
686 c->guard_interval = GUARD_INTERVAL_1_4;
687 break;
688 }
689
690 switch ((buf[2] >> 0) & 7) {
691 case 0:
692 c->hierarchy = HIERARCHY_NONE;
693 break;
694 case 1:
695 c->hierarchy = HIERARCHY_1;
696 break;
697 case 2:
698 c->hierarchy = HIERARCHY_2;
699 break;
700 case 3:
701 c->hierarchy = HIERARCHY_4;
702 break;
703 }
704
705 switch ((buf[3] >> 0) & 3) {
706 case 0:
707 c->modulation = QPSK;
708 break;
709 case 1:
710 c->modulation = QAM_16;
711 break;
712 case 2:
713 c->modulation = QAM_64;
714 break;
715 }
716
717 switch ((buf[4] >> 0) & 3) {
718 case 0:
719 c->bandwidth_hz = 6000000;
720 break;
721 case 1:
722 c->bandwidth_hz = 7000000;
723 break;
724 case 2:
725 c->bandwidth_hz = 8000000;
726 break;
727 }
728
729 switch ((buf[6] >> 0) & 7) {
730 case 0:
731 c->code_rate_HP = FEC_1_2;
732 break;
733 case 1:
734 c->code_rate_HP = FEC_2_3;
735 break;
736 case 2:
737 c->code_rate_HP = FEC_3_4;
738 break;
739 case 3:
740 c->code_rate_HP = FEC_5_6;
741 break;
742 case 4:
743 c->code_rate_HP = FEC_7_8;
744 break;
745 case 5:
746 c->code_rate_HP = FEC_NONE;
747 break;
748 }
749
750 switch ((buf[7] >> 0) & 7) {
751 case 0:
752 c->code_rate_LP = FEC_1_2;
753 break;
754 case 1:
755 c->code_rate_LP = FEC_2_3;
756 break;
757 case 2:
758 c->code_rate_LP = FEC_3_4;
759 break;
760 case 3:
761 c->code_rate_LP = FEC_5_6;
762 break;
763 case 4:
764 c->code_rate_LP = FEC_7_8;
765 break;
766 case 5:
767 c->code_rate_LP = FEC_NONE;
768 break;
769 }
770
771 return 0;
772
773 err:
774 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
775
776 return ret;
777 }
778
779 static int af9033_read_status(struct dvb_frontend *fe, fe_status_t *status)
780 {
781 struct af9033_state *state = fe->demodulator_priv;
782 int ret;
783 u8 tmp;
784
785 *status = 0;
786
787 /* radio channel status, 0=no result, 1=has signal, 2=no signal */
788 ret = af9033_rd_reg(state, 0x800047, &tmp);
789 if (ret < 0)
790 goto err;
791
792 /* has signal */
793 if (tmp == 0x01)
794 *status |= FE_HAS_SIGNAL;
795
796 if (tmp != 0x02) {
797 /* TPS lock */
798 ret = af9033_rd_reg_mask(state, 0x80f5a9, &tmp, 0x01);
799 if (ret < 0)
800 goto err;
801
802 if (tmp)
803 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
804 FE_HAS_VITERBI;
805
806 /* full lock */
807 ret = af9033_rd_reg_mask(state, 0x80f999, &tmp, 0x01);
808 if (ret < 0)
809 goto err;
810
811 if (tmp)
812 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
813 FE_HAS_VITERBI | FE_HAS_SYNC |
814 FE_HAS_LOCK;
815 }
816
817 return 0;
818
819 err:
820 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
821
822 return ret;
823 }
824
825 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
826 {
827 struct af9033_state *state = fe->demodulator_priv;
828 int ret, i, len;
829 u8 buf[3], tmp;
830 u32 snr_val;
831 const struct val_snr *uninitialized_var(snr_lut);
832
833 /* read value */
834 ret = af9033_rd_regs(state, 0x80002c, buf, 3);
835 if (ret < 0)
836 goto err;
837
838 snr_val = (buf[2] << 16) | (buf[1] << 8) | buf[0];
839
840 /* read current modulation */
841 ret = af9033_rd_reg(state, 0x80f903, &tmp);
842 if (ret < 0)
843 goto err;
844
845 switch ((tmp >> 0) & 3) {
846 case 0:
847 len = ARRAY_SIZE(qpsk_snr_lut);
848 snr_lut = qpsk_snr_lut;
849 break;
850 case 1:
851 len = ARRAY_SIZE(qam16_snr_lut);
852 snr_lut = qam16_snr_lut;
853 break;
854 case 2:
855 len = ARRAY_SIZE(qam64_snr_lut);
856 snr_lut = qam64_snr_lut;
857 break;
858 default:
859 goto err;
860 }
861
862 for (i = 0; i < len; i++) {
863 tmp = snr_lut[i].snr;
864
865 if (snr_val < snr_lut[i].val)
866 break;
867 }
868
869 *snr = tmp * 10; /* dB/10 */
870
871 return 0;
872
873 err:
874 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
875
876 return ret;
877 }
878
879 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
880 {
881 struct af9033_state *state = fe->demodulator_priv;
882 int ret;
883 u8 strength2;
884
885 /* read signal strength of 0-100 scale */
886 ret = af9033_rd_reg(state, 0x800048, &strength2);
887 if (ret < 0)
888 goto err;
889
890 /* scale value to 0x0000-0xffff */
891 *strength = strength2 * 0xffff / 100;
892
893 return 0;
894
895 err:
896 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
897
898 return ret;
899 }
900
901 static int af9033_update_ch_stat(struct af9033_state *state)
902 {
903 int ret = 0;
904 u32 err_cnt, bit_cnt;
905 u16 abort_cnt;
906 u8 buf[7];
907
908 /* only update data every half second */
909 if (time_after(jiffies, state->last_stat_check + msecs_to_jiffies(500))) {
910 ret = af9033_rd_regs(state, 0x800032, buf, sizeof(buf));
911 if (ret < 0)
912 goto err;
913 /* in 8 byte packets? */
914 abort_cnt = (buf[1] << 8) + buf[0];
915 /* in bits */
916 err_cnt = (buf[4] << 16) + (buf[3] << 8) + buf[2];
917 /* in 8 byte packets? always(?) 0x2710 = 10000 */
918 bit_cnt = (buf[6] << 8) + buf[5];
919
920 if (bit_cnt < abort_cnt) {
921 abort_cnt = 1000;
922 state->ber = 0xffffffff;
923 } else {
924 /* 8 byte packets, that have not been rejected already */
925 bit_cnt -= (u32)abort_cnt;
926 if (bit_cnt == 0) {
927 state->ber = 0xffffffff;
928 } else {
929 err_cnt -= (u32)abort_cnt * 8 * 8;
930 bit_cnt *= 8 * 8;
931 state->ber = err_cnt * (0xffffffff / bit_cnt);
932 }
933 }
934 state->ucb += abort_cnt;
935 state->last_stat_check = jiffies;
936 }
937
938 return 0;
939 err:
940 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
941
942 return ret;
943 }
944
945 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
946 {
947 struct af9033_state *state = fe->demodulator_priv;
948 int ret;
949
950 ret = af9033_update_ch_stat(state);
951 if (ret < 0)
952 return ret;
953
954 *ber = state->ber;
955
956 return 0;
957 }
958
959 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
960 {
961 struct af9033_state *state = fe->demodulator_priv;
962 int ret;
963
964 ret = af9033_update_ch_stat(state);
965 if (ret < 0)
966 return ret;
967
968 *ucblocks = state->ucb;
969
970 return 0;
971 }
972
973 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
974 {
975 struct af9033_state *state = fe->demodulator_priv;
976 int ret;
977
978 dev_dbg(&state->i2c->dev, "%s: enable=%d\n", __func__, enable);
979
980 ret = af9033_wr_reg_mask(state, 0x00fa04, enable, 0x01);
981 if (ret < 0)
982 goto err;
983
984 return 0;
985
986 err:
987 dev_dbg(&state->i2c->dev, "%s: failed=%d\n", __func__, ret);
988
989 return ret;
990 }
991
992 static struct dvb_frontend_ops af9033_ops;
993
994 struct dvb_frontend *af9033_attach(const struct af9033_config *config,
995 struct i2c_adapter *i2c)
996 {
997 int ret;
998 struct af9033_state *state;
999 u8 buf[8];
1000
1001 dev_dbg(&i2c->dev, "%s:\n", __func__);
1002
1003 /* allocate memory for the internal state */
1004 state = kzalloc(sizeof(struct af9033_state), GFP_KERNEL);
1005 if (state == NULL)
1006 goto err;
1007
1008 /* setup the state */
1009 state->i2c = i2c;
1010 memcpy(&state->cfg, config, sizeof(struct af9033_config));
1011
1012 if (state->cfg.clock != 12000000) {
1013 dev_err(&state->i2c->dev, "%s: af9033: unsupported clock=%d, " \
1014 "only 12000000 Hz is supported currently\n",
1015 KBUILD_MODNAME, state->cfg.clock);
1016 goto err;
1017 }
1018
1019 /* firmware version */
1020 ret = af9033_rd_regs(state, 0x0083e9, &buf[0], 4);
1021 if (ret < 0)
1022 goto err;
1023
1024 ret = af9033_rd_regs(state, 0x804191, &buf[4], 4);
1025 if (ret < 0)
1026 goto err;
1027
1028 dev_info(&state->i2c->dev, "%s: firmware version: LINK=%d.%d.%d.%d " \
1029 "OFDM=%d.%d.%d.%d\n", KBUILD_MODNAME, buf[0], buf[1],
1030 buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
1031
1032 /* sleep */
1033 switch (state->cfg.tuner) {
1034 case AF9033_TUNER_IT9135_38:
1035 case AF9033_TUNER_IT9135_51:
1036 case AF9033_TUNER_IT9135_52:
1037 case AF9033_TUNER_IT9135_60:
1038 case AF9033_TUNER_IT9135_61:
1039 case AF9033_TUNER_IT9135_62:
1040 /* IT9135 did not like to sleep at that early */
1041 break;
1042 default:
1043 ret = af9033_wr_reg(state, 0x80004c, 1);
1044 if (ret < 0)
1045 goto err;
1046
1047 ret = af9033_wr_reg(state, 0x800000, 0);
1048 if (ret < 0)
1049 goto err;
1050 }
1051
1052 /* configure internal TS mode */
1053 switch (state->cfg.ts_mode) {
1054 case AF9033_TS_MODE_PARALLEL:
1055 state->ts_mode_parallel = true;
1056 break;
1057 case AF9033_TS_MODE_SERIAL:
1058 state->ts_mode_serial = true;
1059 break;
1060 case AF9033_TS_MODE_USB:
1061 /* usb mode for AF9035 */
1062 default:
1063 break;
1064 }
1065
1066 /* create dvb_frontend */
1067 memcpy(&state->fe.ops, &af9033_ops, sizeof(struct dvb_frontend_ops));
1068 state->fe.demodulator_priv = state;
1069
1070 return &state->fe;
1071
1072 err:
1073 kfree(state);
1074 return NULL;
1075 }
1076 EXPORT_SYMBOL(af9033_attach);
1077
1078 static struct dvb_frontend_ops af9033_ops = {
1079 .delsys = { SYS_DVBT },
1080 .info = {
1081 .name = "Afatech AF9033 (DVB-T)",
1082 .frequency_min = 174000000,
1083 .frequency_max = 862000000,
1084 .frequency_stepsize = 250000,
1085 .frequency_tolerance = 0,
1086 .caps = FE_CAN_FEC_1_2 |
1087 FE_CAN_FEC_2_3 |
1088 FE_CAN_FEC_3_4 |
1089 FE_CAN_FEC_5_6 |
1090 FE_CAN_FEC_7_8 |
1091 FE_CAN_FEC_AUTO |
1092 FE_CAN_QPSK |
1093 FE_CAN_QAM_16 |
1094 FE_CAN_QAM_64 |
1095 FE_CAN_QAM_AUTO |
1096 FE_CAN_TRANSMISSION_MODE_AUTO |
1097 FE_CAN_GUARD_INTERVAL_AUTO |
1098 FE_CAN_HIERARCHY_AUTO |
1099 FE_CAN_RECOVER |
1100 FE_CAN_MUTE_TS
1101 },
1102
1103 .release = af9033_release,
1104
1105 .init = af9033_init,
1106 .sleep = af9033_sleep,
1107
1108 .get_tune_settings = af9033_get_tune_settings,
1109 .set_frontend = af9033_set_frontend,
1110 .get_frontend = af9033_get_frontend,
1111
1112 .read_status = af9033_read_status,
1113 .read_snr = af9033_read_snr,
1114 .read_signal_strength = af9033_read_signal_strength,
1115 .read_ber = af9033_read_ber,
1116 .read_ucblocks = af9033_read_ucblocks,
1117
1118 .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
1119 };
1120
1121 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1122 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1123 MODULE_LICENSE("GPL");
Linux with added FPC-III support