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[linux/fpc-iii.git] / drivers / media / dvb-frontends / cxd2820r_t2.c
blob2ba130e245b63d3f7b4fa5a33298129f0c654c49
1 /*
2 * Sony CXD2820R demodulator driver
4 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "cxd2820r_priv.h"
24 int cxd2820r_set_frontend_t2(struct dvb_frontend *fe)
26 struct cxd2820r_priv *priv = fe->demodulator_priv;
27 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
28 int ret, i, bw_i;
29 u32 if_freq, if_ctl;
30 u64 num;
31 u8 buf[3], bw_param;
32 u8 bw_params1[][5] = {
33 { 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */
34 { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
35 { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
36 { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
38 struct reg_val_mask tab[] = {
39 { 0x00080, 0x02, 0xff },
40 { 0x00081, 0x20, 0xff },
41 { 0x00085, 0x07, 0xff },
42 { 0x00088, 0x01, 0xff },
43 { 0x02069, 0x01, 0xff },
45 { 0x0207f, 0x2a, 0xff },
46 { 0x02082, 0x0a, 0xff },
47 { 0x02083, 0x0a, 0xff },
48 { 0x020cb, priv->cfg.if_agc_polarity << 6, 0x40 },
49 { 0x02070, priv->cfg.ts_mode, 0xff },
50 { 0x020b5, priv->cfg.spec_inv << 4, 0x10 },
51 { 0x02567, 0x07, 0x0f },
52 { 0x02569, 0x03, 0x03 },
53 { 0x02595, 0x1a, 0xff },
54 { 0x02596, 0x50, 0xff },
55 { 0x02a8c, 0x00, 0xff },
56 { 0x02a8d, 0x34, 0xff },
57 { 0x02a45, 0x06, 0x07 },
58 { 0x03f10, 0x0d, 0xff },
59 { 0x03f11, 0x02, 0xff },
60 { 0x03f12, 0x01, 0xff },
61 { 0x03f23, 0x2c, 0xff },
62 { 0x03f51, 0x13, 0xff },
63 { 0x03f52, 0x01, 0xff },
64 { 0x03f53, 0x00, 0xff },
65 { 0x027e6, 0x14, 0xff },
66 { 0x02786, 0x02, 0x07 },
67 { 0x02787, 0x40, 0xe0 },
68 { 0x027ef, 0x10, 0x18 },
71 dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", __func__,
72 c->frequency, c->bandwidth_hz);
74 switch (c->bandwidth_hz) {
75 case 5000000:
76 bw_i = 0;
77 bw_param = 3;
78 break;
79 case 6000000:
80 bw_i = 1;
81 bw_param = 2;
82 break;
83 case 7000000:
84 bw_i = 2;
85 bw_param = 1;
86 break;
87 case 8000000:
88 bw_i = 3;
89 bw_param = 0;
90 break;
91 default:
92 return -EINVAL;
95 /* program tuner */
96 if (fe->ops.tuner_ops.set_params)
97 fe->ops.tuner_ops.set_params(fe);
99 if (priv->delivery_system != SYS_DVBT2) {
100 for (i = 0; i < ARRAY_SIZE(tab); i++) {
101 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
102 tab[i].val, tab[i].mask);
103 if (ret)
104 goto error;
108 priv->delivery_system = SYS_DVBT2;
110 /* program IF frequency */
111 if (fe->ops.tuner_ops.get_if_frequency) {
112 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
113 if (ret)
114 goto error;
115 } else
116 if_freq = 0;
118 dev_dbg(&priv->i2c->dev, "%s: if_freq=%d\n", __func__, if_freq);
120 num = if_freq / 1000; /* Hz => kHz */
121 num *= 0x1000000;
122 if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
123 buf[0] = ((if_ctl >> 16) & 0xff);
124 buf[1] = ((if_ctl >> 8) & 0xff);
125 buf[2] = ((if_ctl >> 0) & 0xff);
127 /* PLP filtering */
128 if (c->stream_id > 255) {
129 dev_dbg(&priv->i2c->dev, "%s: Disable PLP filtering\n", __func__);
130 ret = cxd2820r_wr_reg(priv, 0x023ad , 0);
131 if (ret)
132 goto error;
133 } else {
134 dev_dbg(&priv->i2c->dev, "%s: Enable PLP filtering = %d\n", __func__,
135 c->stream_id);
136 ret = cxd2820r_wr_reg(priv, 0x023af , c->stream_id & 0xFF);
137 if (ret)
138 goto error;
139 ret = cxd2820r_wr_reg(priv, 0x023ad , 1);
140 if (ret)
141 goto error;
144 ret = cxd2820r_wr_regs(priv, 0x020b6, buf, 3);
145 if (ret)
146 goto error;
148 ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[bw_i], 5);
149 if (ret)
150 goto error;
152 ret = cxd2820r_wr_reg_mask(priv, 0x020d7, bw_param << 6, 0xc0);
153 if (ret)
154 goto error;
156 ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
157 if (ret)
158 goto error;
160 ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
161 if (ret)
162 goto error;
164 return ret;
165 error:
166 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
167 return ret;
171 int cxd2820r_get_frontend_t2(struct dvb_frontend *fe)
173 struct cxd2820r_priv *priv = fe->demodulator_priv;
174 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
175 int ret;
176 u8 buf[2];
178 ret = cxd2820r_rd_regs(priv, 0x0205c, buf, 2);
179 if (ret)
180 goto error;
182 switch ((buf[0] >> 0) & 0x07) {
183 case 0:
184 c->transmission_mode = TRANSMISSION_MODE_2K;
185 break;
186 case 1:
187 c->transmission_mode = TRANSMISSION_MODE_8K;
188 break;
189 case 2:
190 c->transmission_mode = TRANSMISSION_MODE_4K;
191 break;
192 case 3:
193 c->transmission_mode = TRANSMISSION_MODE_1K;
194 break;
195 case 4:
196 c->transmission_mode = TRANSMISSION_MODE_16K;
197 break;
198 case 5:
199 c->transmission_mode = TRANSMISSION_MODE_32K;
200 break;
203 switch ((buf[1] >> 4) & 0x07) {
204 case 0:
205 c->guard_interval = GUARD_INTERVAL_1_32;
206 break;
207 case 1:
208 c->guard_interval = GUARD_INTERVAL_1_16;
209 break;
210 case 2:
211 c->guard_interval = GUARD_INTERVAL_1_8;
212 break;
213 case 3:
214 c->guard_interval = GUARD_INTERVAL_1_4;
215 break;
216 case 4:
217 c->guard_interval = GUARD_INTERVAL_1_128;
218 break;
219 case 5:
220 c->guard_interval = GUARD_INTERVAL_19_128;
221 break;
222 case 6:
223 c->guard_interval = GUARD_INTERVAL_19_256;
224 break;
227 ret = cxd2820r_rd_regs(priv, 0x0225b, buf, 2);
228 if (ret)
229 goto error;
231 switch ((buf[0] >> 0) & 0x07) {
232 case 0:
233 c->fec_inner = FEC_1_2;
234 break;
235 case 1:
236 c->fec_inner = FEC_3_5;
237 break;
238 case 2:
239 c->fec_inner = FEC_2_3;
240 break;
241 case 3:
242 c->fec_inner = FEC_3_4;
243 break;
244 case 4:
245 c->fec_inner = FEC_4_5;
246 break;
247 case 5:
248 c->fec_inner = FEC_5_6;
249 break;
252 switch ((buf[1] >> 0) & 0x07) {
253 case 0:
254 c->modulation = QPSK;
255 break;
256 case 1:
257 c->modulation = QAM_16;
258 break;
259 case 2:
260 c->modulation = QAM_64;
261 break;
262 case 3:
263 c->modulation = QAM_256;
264 break;
267 ret = cxd2820r_rd_reg(priv, 0x020b5, &buf[0]);
268 if (ret)
269 goto error;
271 switch ((buf[0] >> 4) & 0x01) {
272 case 0:
273 c->inversion = INVERSION_OFF;
274 break;
275 case 1:
276 c->inversion = INVERSION_ON;
277 break;
280 return ret;
281 error:
282 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
283 return ret;
286 int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status)
288 struct cxd2820r_priv *priv = fe->demodulator_priv;
289 int ret;
290 u8 buf[1];
291 *status = 0;
293 ret = cxd2820r_rd_reg(priv, 0x02010 , &buf[0]);
294 if (ret)
295 goto error;
297 if ((buf[0] & 0x07) == 6) {
298 if (((buf[0] >> 5) & 0x01) == 1) {
299 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
300 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
301 } else {
302 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
303 FE_HAS_VITERBI | FE_HAS_SYNC;
307 dev_dbg(&priv->i2c->dev, "%s: lock=%02x\n", __func__, buf[0]);
309 return ret;
310 error:
311 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
312 return ret;
315 int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber)
317 struct cxd2820r_priv *priv = fe->demodulator_priv;
318 int ret;
319 u8 buf[4];
320 unsigned int errbits;
321 *ber = 0;
322 /* FIXME: correct calculation */
324 ret = cxd2820r_rd_regs(priv, 0x02039, buf, sizeof(buf));
325 if (ret)
326 goto error;
328 if ((buf[0] >> 4) & 0x01) {
329 errbits = (buf[0] & 0x0f) << 24 | buf[1] << 16 |
330 buf[2] << 8 | buf[3];
332 if (errbits)
333 *ber = errbits * 64 / 16588800;
336 return ret;
337 error:
338 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
339 return ret;
342 int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe,
343 u16 *strength)
345 struct cxd2820r_priv *priv = fe->demodulator_priv;
346 int ret;
347 u8 buf[2];
348 u16 tmp;
350 ret = cxd2820r_rd_regs(priv, 0x02026, buf, sizeof(buf));
351 if (ret)
352 goto error;
354 tmp = (buf[0] & 0x0f) << 8 | buf[1];
355 tmp = ~tmp & 0x0fff;
357 /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
358 *strength = tmp * 0xffff / 0x0fff;
360 return ret;
361 error:
362 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
363 return ret;
366 int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr)
368 struct cxd2820r_priv *priv = fe->demodulator_priv;
369 int ret;
370 u8 buf[2];
371 u16 tmp;
372 /* report SNR in dB * 10 */
374 ret = cxd2820r_rd_regs(priv, 0x02028, buf, sizeof(buf));
375 if (ret)
376 goto error;
378 tmp = (buf[0] & 0x0f) << 8 | buf[1];
379 #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
380 if (tmp)
381 *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
382 / 100);
383 else
384 *snr = 0;
386 dev_dbg(&priv->i2c->dev, "%s: dBx10=%d val=%04x\n", __func__, *snr,
387 tmp);
389 return ret;
390 error:
391 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
392 return ret;
395 int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks)
397 *ucblocks = 0;
398 /* no way to read ? */
399 return 0;
402 int cxd2820r_sleep_t2(struct dvb_frontend *fe)
404 struct cxd2820r_priv *priv = fe->demodulator_priv;
405 int ret, i;
406 struct reg_val_mask tab[] = {
407 { 0x000ff, 0x1f, 0xff },
408 { 0x00085, 0x00, 0xff },
409 { 0x00088, 0x01, 0xff },
410 { 0x02069, 0x00, 0xff },
411 { 0x00081, 0x00, 0xff },
412 { 0x00080, 0x00, 0xff },
415 dev_dbg(&priv->i2c->dev, "%s\n", __func__);
417 for (i = 0; i < ARRAY_SIZE(tab); i++) {
418 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
419 tab[i].mask);
420 if (ret)
421 goto error;
424 priv->delivery_system = SYS_UNDEFINED;
426 return ret;
427 error:
428 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
429 return ret;
432 int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
433 struct dvb_frontend_tune_settings *s)
435 s->min_delay_ms = 1500;
436 s->step_size = fe->ops.info.frequency_stepsize * 2;
437 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
439 return 0;