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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / dvb-frontends / m88ds3103.c
blobb8a7897e7bd81210e4f35f43d551541385c37c27
1 /*
2 * Montage M88DS3103 demodulator driver
3 *
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include "m88ds3103_priv.h"
18
19 static struct dvb_frontend_ops m88ds3103_ops;
20
21 /* write multiple registers */
22 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
23 u8 reg, const u8 *val, int len)
24 {
25 #define MAX_WR_LEN 32
26 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
27 int ret;
28 u8 buf[MAX_WR_XFER_LEN];
29 struct i2c_msg msg[1] = {
30 {
31 .addr = priv->cfg->i2c_addr,
32 .flags = 0,
33 .len = 1 + len,
34 .buf = buf,
35 }
36 };
37
38 if (WARN_ON(len > MAX_WR_LEN))
39 return -EINVAL;
40
41 buf[0] = reg;
42 memcpy(&buf[1], val, len);
43
44 mutex_lock(&priv->i2c_mutex);
45 ret = i2c_transfer(priv->i2c, msg, 1);
46 mutex_unlock(&priv->i2c_mutex);
47 if (ret == 1) {
48 ret = 0;
49 } else {
50 dev_warn(&priv->i2c->dev,
51 "%s: i2c wr failed=%d reg=%02x len=%d\n",
52 KBUILD_MODNAME, ret, reg, len);
53 ret = -EREMOTEIO;
54 }
55
56 return ret;
57 }
58
59 /* read multiple registers */
60 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
61 u8 reg, u8 *val, int len)
62 {
63 #define MAX_RD_LEN 3
64 #define MAX_RD_XFER_LEN (MAX_RD_LEN)
65 int ret;
66 u8 buf[MAX_RD_XFER_LEN];
67 struct i2c_msg msg[2] = {
68 {
69 .addr = priv->cfg->i2c_addr,
70 .flags = 0,
71 .len = 1,
72 .buf = &reg,
73 }, {
74 .addr = priv->cfg->i2c_addr,
75 .flags = I2C_M_RD,
76 .len = len,
77 .buf = buf,
78 }
79 };
80
81 if (WARN_ON(len > MAX_RD_LEN))
82 return -EINVAL;
83
84 mutex_lock(&priv->i2c_mutex);
85 ret = i2c_transfer(priv->i2c, msg, 2);
86 mutex_unlock(&priv->i2c_mutex);
87 if (ret == 2) {
88 memcpy(val, buf, len);
89 ret = 0;
90 } else {
91 dev_warn(&priv->i2c->dev,
92 "%s: i2c rd failed=%d reg=%02x len=%d\n",
93 KBUILD_MODNAME, ret, reg, len);
94 ret = -EREMOTEIO;
95 }
96
97 return ret;
98 }
99
100 /* write single register */
101 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
102 {
103 return m88ds3103_wr_regs(priv, reg, &val, 1);
104 }
105
106 /* read single register */
107 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
108 {
109 return m88ds3103_rd_regs(priv, reg, val, 1);
110 }
111
112 /* write single register with mask */
113 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
114 u8 reg, u8 val, u8 mask)
115 {
116 int ret;
117 u8 u8tmp;
118
119 /* no need for read if whole reg is written */
120 if (mask != 0xff) {
121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
122 if (ret)
123 return ret;
124
125 val &= mask;
126 u8tmp &= ~mask;
127 val |= u8tmp;
128 }
129
130 return m88ds3103_wr_regs(priv, reg, &val, 1);
131 }
132
133 /* read single register with mask */
134 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
135 u8 reg, u8 *val, u8 mask)
136 {
137 int ret, i;
138 u8 u8tmp;
139
140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
141 if (ret)
142 return ret;
143
144 u8tmp &= mask;
145
146 /* find position of the first bit */
147 for (i = 0; i < 8; i++) {
148 if ((mask >> i) & 0x01)
149 break;
150 }
151 *val = u8tmp >> i;
152
153 return 0;
154 }
155
156 /* write reg val table using reg addr auto increment */
157 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
158 const struct m88ds3103_reg_val *tab, int tab_len)
159 {
160 int ret, i, j;
161 u8 buf[83];
162 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
163
164 if (tab_len > 83) {
165 ret = -EINVAL;
166 goto err;
167 }
168
169 for (i = 0, j = 0; i < tab_len; i++, j++) {
170 buf[j] = tab[i].val;
171
172 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
173 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
174 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
175 if (ret)
176 goto err;
177
178 j = -1;
179 }
180 }
181
182 return 0;
183 err:
184 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
185 return ret;
186 }
187
188 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
189 {
190 struct m88ds3103_priv *priv = fe->demodulator_priv;
191 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
192 int ret;
193 u8 u8tmp;
194
195 *status = 0;
196
197 if (!priv->warm) {
198 ret = -EAGAIN;
199 goto err;
200 }
201
202 switch (c->delivery_system) {
203 case SYS_DVBS:
204 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
205 if (ret)
206 goto err;
207
208 if (u8tmp == 0x07)
209 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
210 FE_HAS_VITERBI | FE_HAS_SYNC |
211 FE_HAS_LOCK;
212 break;
213 case SYS_DVBS2:
214 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
215 if (ret)
216 goto err;
217
218 if (u8tmp == 0x8f)
219 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
220 FE_HAS_VITERBI | FE_HAS_SYNC |
221 FE_HAS_LOCK;
222 break;
223 default:
224 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
225 __func__);
226 ret = -EINVAL;
227 goto err;
228 }
229
230 priv->fe_status = *status;
231
232 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
233 __func__, u8tmp, *status);
234
235 return 0;
236 err:
237 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
238 return ret;
239 }
240
241 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
242 {
243 struct m88ds3103_priv *priv = fe->demodulator_priv;
244 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
245 int ret, len;
246 const struct m88ds3103_reg_val *init;
247 u8 u8tmp, u8tmp1, u8tmp2;
248 u8 buf[2];
249 u16 u16tmp, divide_ratio;
250 u32 tuner_frequency, target_mclk, ts_clk;
251 s32 s32tmp;
252 dev_dbg(&priv->i2c->dev,
253 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
254 __func__, c->delivery_system,
255 c->modulation, c->frequency, c->symbol_rate,
256 c->inversion, c->pilot, c->rolloff);
257
258 if (!priv->warm) {
259 ret = -EAGAIN;
260 goto err;
261 }
262
263 /* program tuner */
264 if (fe->ops.tuner_ops.set_params) {
265 ret = fe->ops.tuner_ops.set_params(fe);
266 if (ret)
267 goto err;
268 }
269
270 if (fe->ops.tuner_ops.get_frequency) {
271 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
272 if (ret)
273 goto err;
274 }
275
276 /* reset */
277 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
278 if (ret)
279 goto err;
280
281 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
282 if (ret)
283 goto err;
284
285 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
286 if (ret)
287 goto err;
288
289 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
290 if (ret)
291 goto err;
292
293 switch (c->delivery_system) {
294 case SYS_DVBS:
295 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
296 init = m88ds3103_dvbs_init_reg_vals;
297 target_mclk = 96000;
298 break;
299 case SYS_DVBS2:
300 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
301 init = m88ds3103_dvbs2_init_reg_vals;
302
303 switch (priv->cfg->ts_mode) {
304 case M88DS3103_TS_SERIAL:
305 case M88DS3103_TS_SERIAL_D7:
306 if (c->symbol_rate < 18000000)
307 target_mclk = 96000;
308 else
309 target_mclk = 144000;
310 break;
311 case M88DS3103_TS_PARALLEL:
312 case M88DS3103_TS_PARALLEL_12:
313 case M88DS3103_TS_PARALLEL_16:
314 case M88DS3103_TS_PARALLEL_19_2:
315 case M88DS3103_TS_CI:
316 if (c->symbol_rate < 18000000)
317 target_mclk = 96000;
318 else if (c->symbol_rate < 28000000)
319 target_mclk = 144000;
320 else
321 target_mclk = 192000;
322 break;
323 default:
324 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
325 __func__);
326 ret = -EINVAL;
327 goto err;
328 }
329 break;
330 default:
331 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
332 __func__);
333 ret = -EINVAL;
334 goto err;
335 }
336
337 /* program init table */
338 if (c->delivery_system != priv->delivery_system) {
339 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
340 if (ret)
341 goto err;
342 }
343
344 u8tmp1 = 0; /* silence compiler warning */
345 switch (priv->cfg->ts_mode) {
346 case M88DS3103_TS_SERIAL:
347 u8tmp1 = 0x00;
348 ts_clk = 0;
349 u8tmp = 0x46;
350 break;
351 case M88DS3103_TS_SERIAL_D7:
352 u8tmp1 = 0x20;
353 ts_clk = 0;
354 u8tmp = 0x46;
355 break;
356 case M88DS3103_TS_PARALLEL:
357 ts_clk = 24000;
358 u8tmp = 0x42;
359 break;
360 case M88DS3103_TS_PARALLEL_12:
361 ts_clk = 12000;
362 u8tmp = 0x42;
363 break;
364 case M88DS3103_TS_PARALLEL_16:
365 ts_clk = 16000;
366 u8tmp = 0x42;
367 break;
368 case M88DS3103_TS_PARALLEL_19_2:
369 ts_clk = 19200;
370 u8tmp = 0x42;
371 break;
372 case M88DS3103_TS_CI:
373 ts_clk = 6000;
374 u8tmp = 0x43;
375 break;
376 default:
377 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
378 ret = -EINVAL;
379 goto err;
380 }
381
382 /* TS mode */
383 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
384 if (ret)
385 goto err;
386
387 switch (priv->cfg->ts_mode) {
388 case M88DS3103_TS_SERIAL:
389 case M88DS3103_TS_SERIAL_D7:
390 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
391 if (ret)
392 goto err;
393 }
394
395 if (ts_clk) {
396 divide_ratio = DIV_ROUND_UP(target_mclk, ts_clk);
397 u8tmp1 = divide_ratio / 2;
398 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
399 } else {
400 divide_ratio = 0;
401 u8tmp1 = 0;
402 u8tmp2 = 0;
403 }
404
405 dev_dbg(&priv->i2c->dev,
406 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
407 __func__, target_mclk, ts_clk, divide_ratio);
408
409 u8tmp1--;
410 u8tmp2--;
411 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
412 u8tmp1 &= 0x3f;
413 /* u8tmp2[5:0] => ea[5:0] */
414 u8tmp2 &= 0x3f;
415
416 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
417 if (ret)
418 goto err;
419
420 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
421 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
422 if (ret)
423 goto err;
424
425 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
426 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
427 if (ret)
428 goto err;
429
430 switch (target_mclk) {
431 case 72000:
432 u8tmp1 = 0x00; /* 0b00 */
433 u8tmp2 = 0x03; /* 0b11 */
434 break;
435 case 96000:
436 u8tmp1 = 0x02; /* 0b10 */
437 u8tmp2 = 0x01; /* 0b01 */
438 break;
439 case 115200:
440 u8tmp1 = 0x01; /* 0b01 */
441 u8tmp2 = 0x01; /* 0b01 */
442 break;
443 case 144000:
444 u8tmp1 = 0x00; /* 0b00 */
445 u8tmp2 = 0x01; /* 0b01 */
446 break;
447 case 192000:
448 u8tmp1 = 0x03; /* 0b11 */
449 u8tmp2 = 0x00; /* 0b00 */
450 break;
451 default:
452 dev_dbg(&priv->i2c->dev, "%s: invalid target_mclk\n", __func__);
453 ret = -EINVAL;
454 goto err;
455 }
456
457 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
458 if (ret)
459 goto err;
460
461 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
462 if (ret)
463 goto err;
464
465 if (c->symbol_rate <= 3000000)
466 u8tmp = 0x20;
467 else if (c->symbol_rate <= 10000000)
468 u8tmp = 0x10;
469 else
470 u8tmp = 0x06;
471
472 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
473 if (ret)
474 goto err;
475
476 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
477 if (ret)
478 goto err;
479
480 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
481 if (ret)
482 goto err;
483
484 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
485 if (ret)
486 goto err;
487
488 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, M88DS3103_MCLK_KHZ / 2);
489 buf[0] = (u16tmp >> 0) & 0xff;
490 buf[1] = (u16tmp >> 8) & 0xff;
491 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
492 if (ret)
493 goto err;
494
495 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
496 if (ret)
497 goto err;
498
499 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
500 if (ret)
501 goto err;
502
503 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
504 if (ret)
505 goto err;
506
507 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
508 (tuner_frequency - c->frequency));
509
510 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
511 s32tmp = DIV_ROUND_CLOSEST(s32tmp, M88DS3103_MCLK_KHZ);
512 if (s32tmp < 0)
513 s32tmp += 0x10000;
514
515 buf[0] = (s32tmp >> 0) & 0xff;
516 buf[1] = (s32tmp >> 8) & 0xff;
517 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
518 if (ret)
519 goto err;
520
521 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
522 if (ret)
523 goto err;
524
525 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
526 if (ret)
527 goto err;
528
529 priv->delivery_system = c->delivery_system;
530
531 return 0;
532 err:
533 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
534 return ret;
535 }
536
537 static int m88ds3103_init(struct dvb_frontend *fe)
538 {
539 struct m88ds3103_priv *priv = fe->demodulator_priv;
540 int ret, len, remaining;
541 const struct firmware *fw = NULL;
542 u8 *fw_file = M88DS3103_FIRMWARE;
543 u8 u8tmp;
544 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
545
546 /* set cold state by default */
547 priv->warm = false;
548
549 /* wake up device from sleep */
550 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
551 if (ret)
552 goto err;
553
554 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
555 if (ret)
556 goto err;
557
558 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
559 if (ret)
560 goto err;
561
562 /* reset */
563 ret = m88ds3103_wr_reg(priv, 0x07, 0x60);
564 if (ret)
565 goto err;
566
567 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
568 if (ret)
569 goto err;
570
571 /* firmware status */
572 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
573 if (ret)
574 goto err;
575
576 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
577
578 if (u8tmp)
579 goto skip_fw_download;
580
581 /* cold state - try to download firmware */
582 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
583 KBUILD_MODNAME, m88ds3103_ops.info.name);
584
585 /* request the firmware, this will block and timeout */
586 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
587 if (ret) {
588 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n",
589 KBUILD_MODNAME, fw_file);
590 goto err;
591 }
592
593 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
594 KBUILD_MODNAME, fw_file);
595
596 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
597 if (ret)
598 goto err;
599
600 for (remaining = fw->size; remaining > 0;
601 remaining -= (priv->cfg->i2c_wr_max - 1)) {
602 len = remaining;
603 if (len > (priv->cfg->i2c_wr_max - 1))
604 len = (priv->cfg->i2c_wr_max - 1);
605
606 ret = m88ds3103_wr_regs(priv, 0xb0,
607 &fw->data[fw->size - remaining], len);
608 if (ret) {
609 dev_err(&priv->i2c->dev,
610 "%s: firmware download failed=%d\n",
611 KBUILD_MODNAME, ret);
612 goto err;
613 }
614 }
615
616 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
617 if (ret)
618 goto err;
619
620 release_firmware(fw);
621 fw = NULL;
622
623 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
624 if (ret)
625 goto err;
626
627 if (!u8tmp) {
628 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
629 KBUILD_MODNAME);
630 ret = -EFAULT;
631 goto err;
632 }
633
634 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
635 KBUILD_MODNAME, m88ds3103_ops.info.name);
636 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
637 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
638
639 skip_fw_download:
640 /* warm state */
641 priv->warm = true;
642
643 return 0;
644 err:
645 if (fw)
646 release_firmware(fw);
647
648 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
649 return ret;
650 }
651
652 static int m88ds3103_sleep(struct dvb_frontend *fe)
653 {
654 struct m88ds3103_priv *priv = fe->demodulator_priv;
655 int ret;
656 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
657
658 priv->delivery_system = SYS_UNDEFINED;
659
660 /* TS Hi-Z */
661 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01);
662 if (ret)
663 goto err;
664
665 /* sleep */
666 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
667 if (ret)
668 goto err;
669
670 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
671 if (ret)
672 goto err;
673
674 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
675 if (ret)
676 goto err;
677
678 return 0;
679 err:
680 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
681 return ret;
682 }
683
684 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
685 {
686 struct m88ds3103_priv *priv = fe->demodulator_priv;
687 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
688 int ret;
689 u8 buf[3];
690 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
691
692 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
693 ret = -EAGAIN;
694 goto err;
695 }
696
697 switch (c->delivery_system) {
698 case SYS_DVBS:
699 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
700 if (ret)
701 goto err;
702
703 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
704 if (ret)
705 goto err;
706
707 switch ((buf[0] >> 2) & 0x01) {
708 case 0:
709 c->inversion = INVERSION_OFF;
710 break;
711 case 1:
712 c->inversion = INVERSION_ON;
713 break;
714 default:
715 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n",
716 __func__);
717 }
718
719 switch ((buf[1] >> 5) & 0x07) {
720 case 0:
721 c->fec_inner = FEC_7_8;
722 break;
723 case 1:
724 c->fec_inner = FEC_5_6;
725 break;
726 case 2:
727 c->fec_inner = FEC_3_4;
728 break;
729 case 3:
730 c->fec_inner = FEC_2_3;
731 break;
732 case 4:
733 c->fec_inner = FEC_1_2;
734 break;
735 default:
736 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
737 __func__);
738 }
739
740 c->modulation = QPSK;
741
742 break;
743 case SYS_DVBS2:
744 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
745 if (ret)
746 goto err;
747
748 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
749 if (ret)
750 goto err;
751
752 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
753 if (ret)
754 goto err;
755
756 switch ((buf[0] >> 0) & 0x0f) {
757 case 2:
758 c->fec_inner = FEC_2_5;
759 break;
760 case 3:
761 c->fec_inner = FEC_1_2;
762 break;
763 case 4:
764 c->fec_inner = FEC_3_5;
765 break;
766 case 5:
767 c->fec_inner = FEC_2_3;
768 break;
769 case 6:
770 c->fec_inner = FEC_3_4;
771 break;
772 case 7:
773 c->fec_inner = FEC_4_5;
774 break;
775 case 8:
776 c->fec_inner = FEC_5_6;
777 break;
778 case 9:
779 c->fec_inner = FEC_8_9;
780 break;
781 case 10:
782 c->fec_inner = FEC_9_10;
783 break;
784 default:
785 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
786 __func__);
787 }
788
789 switch ((buf[0] >> 5) & 0x01) {
790 case 0:
791 c->pilot = PILOT_OFF;
792 break;
793 case 1:
794 c->pilot = PILOT_ON;
795 break;
796 default:
797 dev_dbg(&priv->i2c->dev, "%s: invalid pilot\n",
798 __func__);
799 }
800
801 switch ((buf[0] >> 6) & 0x07) {
802 case 0:
803 c->modulation = QPSK;
804 break;
805 case 1:
806 c->modulation = PSK_8;
807 break;
808 case 2:
809 c->modulation = APSK_16;
810 break;
811 case 3:
812 c->modulation = APSK_32;
813 break;
814 default:
815 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
816 __func__);
817 }
818
819 switch ((buf[1] >> 7) & 0x01) {
820 case 0:
821 c->inversion = INVERSION_OFF;
822 break;
823 case 1:
824 c->inversion = INVERSION_ON;
825 break;
826 default:
827 dev_dbg(&priv->i2c->dev, "%s: invalid inversion\n",
828 __func__);
829 }
830
831 switch ((buf[2] >> 0) & 0x03) {
832 case 0:
833 c->rolloff = ROLLOFF_35;
834 break;
835 case 1:
836 c->rolloff = ROLLOFF_25;
837 break;
838 case 2:
839 c->rolloff = ROLLOFF_20;
840 break;
841 default:
842 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
843 __func__);
844 }
845 break;
846 default:
847 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
848 __func__);
849 ret = -EINVAL;
850 goto err;
851 }
852
853 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
854 if (ret)
855 goto err;
856
857 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
858 M88DS3103_MCLK_KHZ * 1000 / 0x10000;
859
860 return 0;
861 err:
862 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
863 return ret;
864 }
865
866 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
867 {
868 struct m88ds3103_priv *priv = fe->demodulator_priv;
869 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
870 int ret, i, tmp;
871 u8 buf[3];
872 u16 noise, signal;
873 u32 noise_tot, signal_tot;
874 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
875 /* reports SNR in resolution of 0.1 dB */
876
877 /* more iterations for more accurate estimation */
878 #define M88DS3103_SNR_ITERATIONS 3
879
880 switch (c->delivery_system) {
881 case SYS_DVBS:
882 tmp = 0;
883
884 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
885 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
886 if (ret)
887 goto err;
888
889 tmp += buf[0];
890 }
891
892 /* use of one register limits max value to 15 dB */
893 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
894 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
895 if (tmp)
896 *snr = 100ul * intlog2(tmp) / intlog2(10);
897 else
898 *snr = 0;
899 break;
900 case SYS_DVBS2:
901 noise_tot = 0;
902 signal_tot = 0;
903
904 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
905 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
906 if (ret)
907 goto err;
908
909 noise = buf[1] << 6; /* [13:6] */
910 noise |= buf[0] & 0x3f; /* [5:0] */
911 noise >>= 2;
912 signal = buf[2] * buf[2];
913 signal >>= 1;
914
915 noise_tot += noise;
916 signal_tot += signal;
917 }
918
919 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
920 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
921
922 /* SNR(X) dB = 10 * log10(X) dB */
923 if (signal > noise) {
924 tmp = signal / noise;
925 *snr = 100ul * intlog10(tmp) / (1 << 24);
926 } else {
927 *snr = 0;
928 }
929 break;
930 default:
931 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
932 __func__);
933 ret = -EINVAL;
934 goto err;
935 }
936
937 return 0;
938 err:
939 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
940 return ret;
941 }
942
943
944 static int m88ds3103_set_tone(struct dvb_frontend *fe,
945 fe_sec_tone_mode_t fe_sec_tone_mode)
946 {
947 struct m88ds3103_priv *priv = fe->demodulator_priv;
948 int ret;
949 u8 u8tmp, tone, reg_a1_mask;
950 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
951 fe_sec_tone_mode);
952
953 if (!priv->warm) {
954 ret = -EAGAIN;
955 goto err;
956 }
957
958 switch (fe_sec_tone_mode) {
959 case SEC_TONE_ON:
960 tone = 0;
961 reg_a1_mask = 0x87;
962 break;
963 case SEC_TONE_OFF:
964 tone = 1;
965 reg_a1_mask = 0x00;
966 break;
967 default:
968 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
969 __func__);
970 ret = -EINVAL;
971 goto err;
972 }
973
974 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
975 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
976 if (ret)
977 goto err;
978
979 u8tmp = 1 << 2;
980 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
981 if (ret)
982 goto err;
983
984 return 0;
985 err:
986 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
987 return ret;
988 }
989
990 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
991 struct dvb_diseqc_master_cmd *diseqc_cmd)
992 {
993 struct m88ds3103_priv *priv = fe->demodulator_priv;
994 int ret, i;
995 u8 u8tmp;
996 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
997 diseqc_cmd->msg_len, diseqc_cmd->msg);
998
999 if (!priv->warm) {
1000 ret = -EAGAIN;
1001 goto err;
1002 }
1003
1004 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1005 ret = -EINVAL;
1006 goto err;
1007 }
1008
1009 u8tmp = priv->cfg->envelope_mode << 5;
1010 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1011 if (ret)
1012 goto err;
1013
1014 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
1015 diseqc_cmd->msg_len);
1016 if (ret)
1017 goto err;
1018
1019 ret = m88ds3103_wr_reg(priv, 0xa1,
1020 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1021 if (ret)
1022 goto err;
1023
1024 /* DiSEqC message typical period is 54 ms */
1025 usleep_range(40000, 60000);
1026
1027 /* wait DiSEqC TX ready */
1028 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1029 usleep_range(5000, 10000);
1030
1031 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1032 if (ret)
1033 goto err;
1034 }
1035
1036 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1037
1038 if (i == 0) {
1039 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1040
1041 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1042 if (ret)
1043 goto err;
1044 }
1045
1046 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1047 if (ret)
1048 goto err;
1049
1050 if (i == 0) {
1051 ret = -ETIMEDOUT;
1052 goto err;
1053 }
1054
1055 return 0;
1056 err:
1057 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1058 return ret;
1059 }
1060
1061 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1062 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1063 {
1064 struct m88ds3103_priv *priv = fe->demodulator_priv;
1065 int ret, i;
1066 u8 u8tmp, burst;
1067 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1068 fe_sec_mini_cmd);
1069
1070 if (!priv->warm) {
1071 ret = -EAGAIN;
1072 goto err;
1073 }
1074
1075 u8tmp = priv->cfg->envelope_mode << 5;
1076 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1077 if (ret)
1078 goto err;
1079
1080 switch (fe_sec_mini_cmd) {
1081 case SEC_MINI_A:
1082 burst = 0x02;
1083 break;
1084 case SEC_MINI_B:
1085 burst = 0x01;
1086 break;
1087 default:
1088 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1089 __func__);
1090 ret = -EINVAL;
1091 goto err;
1092 }
1093
1094 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1095 if (ret)
1096 goto err;
1097
1098 /* DiSEqC ToneBurst period is 12.5 ms */
1099 usleep_range(11000, 20000);
1100
1101 /* wait DiSEqC TX ready */
1102 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1103 usleep_range(800, 2000);
1104
1105 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1106 if (ret)
1107 goto err;
1108 }
1109
1110 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1111
1112 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1113 if (ret)
1114 goto err;
1115
1116 if (i == 0) {
1117 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1118 ret = -ETIMEDOUT;
1119 goto err;
1120 }
1121
1122 return 0;
1123 err:
1124 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1125 return ret;
1126 }
1127
1128 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1129 struct dvb_frontend_tune_settings *s)
1130 {
1131 s->min_delay_ms = 3000;
1132
1133 return 0;
1134 }
1135
1136 static void m88ds3103_release(struct dvb_frontend *fe)
1137 {
1138 struct m88ds3103_priv *priv = fe->demodulator_priv;
1139 i2c_del_mux_adapter(priv->i2c_adapter);
1140 kfree(priv);
1141 }
1142
1143 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1144 {
1145 struct m88ds3103_priv *priv = mux_priv;
1146 int ret;
1147 struct i2c_msg gate_open_msg[1] = {
1148 {
1149 .addr = priv->cfg->i2c_addr,
1150 .flags = 0,
1151 .len = 2,
1152 .buf = "\x03\x11",
1153 }
1154 };
1155
1156 mutex_lock(&priv->i2c_mutex);
1157
1158 /* open tuner I2C repeater for 1 xfer, closes automatically */
1159 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
1160 if (ret != 1) {
1161 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
1162 KBUILD_MODNAME, ret);
1163 if (ret >= 0)
1164 ret = -EREMOTEIO;
1165
1166 return ret;
1167 }
1168
1169 return 0;
1170 }
1171
1172 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1173 u32 chan)
1174 {
1175 struct m88ds3103_priv *priv = mux_priv;
1176
1177 mutex_unlock(&priv->i2c_mutex);
1178
1179 return 0;
1180 }
1181
1182 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1183 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1184 {
1185 int ret;
1186 struct m88ds3103_priv *priv;
1187 u8 chip_id, u8tmp;
1188
1189 /* allocate memory for the internal priv */
1190 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1191 if (!priv) {
1192 ret = -ENOMEM;
1193 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1194 goto err;
1195 }
1196
1197 priv->cfg = cfg;
1198 priv->i2c = i2c;
1199 mutex_init(&priv->i2c_mutex);
1200
1201 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id);
1202 if (ret)
1203 goto err;
1204
1205 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
1206
1207 switch (chip_id) {
1208 case 0xd0:
1209 break;
1210 default:
1211 goto err;
1212 }
1213
1214 switch (priv->cfg->clock_out) {
1215 case M88DS3103_CLOCK_OUT_DISABLED:
1216 u8tmp = 0x80;
1217 break;
1218 case M88DS3103_CLOCK_OUT_ENABLED:
1219 u8tmp = 0x00;
1220 break;
1221 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1222 u8tmp = 0x10;
1223 break;
1224 default:
1225 goto err;
1226 }
1227
1228 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1229 if (ret)
1230 goto err;
1231
1232 /* sleep */
1233 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1234 if (ret)
1235 goto err;
1236
1237 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1238 if (ret)
1239 goto err;
1240
1241 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1242 if (ret)
1243 goto err;
1244
1245 /* create mux i2c adapter for tuner */
1246 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1247 m88ds3103_select, m88ds3103_deselect);
1248 if (priv->i2c_adapter == NULL)
1249 goto err;
1250
1251 *tuner_i2c_adapter = priv->i2c_adapter;
1252
1253 /* create dvb_frontend */
1254 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1255 priv->fe.demodulator_priv = priv;
1256
1257 return &priv->fe;
1258 err:
1259 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1260 kfree(priv);
1261 return NULL;
1262 }
1263 EXPORT_SYMBOL(m88ds3103_attach);
1264
1265 static struct dvb_frontend_ops m88ds3103_ops = {
1266 .delsys = { SYS_DVBS, SYS_DVBS2 },
1267 .info = {
1268 .name = "Montage M88DS3103",
1269 .frequency_min = 950000,
1270 .frequency_max = 2150000,
1271 .frequency_tolerance = 5000,
1272 .symbol_rate_min = 1000000,
1273 .symbol_rate_max = 45000000,
1274 .caps = FE_CAN_INVERSION_AUTO |
1275 FE_CAN_FEC_1_2 |
1276 FE_CAN_FEC_2_3 |
1277 FE_CAN_FEC_3_4 |
1278 FE_CAN_FEC_4_5 |
1279 FE_CAN_FEC_5_6 |
1280 FE_CAN_FEC_6_7 |
1281 FE_CAN_FEC_7_8 |
1282 FE_CAN_FEC_8_9 |
1283 FE_CAN_FEC_AUTO |
1284 FE_CAN_QPSK |
1285 FE_CAN_RECOVER |
1286 FE_CAN_2G_MODULATION
1287 },
1288
1289 .release = m88ds3103_release,
1290
1291 .get_tune_settings = m88ds3103_get_tune_settings,
1292
1293 .init = m88ds3103_init,
1294 .sleep = m88ds3103_sleep,
1295
1296 .set_frontend = m88ds3103_set_frontend,
1297 .get_frontend = m88ds3103_get_frontend,
1298
1299 .read_status = m88ds3103_read_status,
1300 .read_snr = m88ds3103_read_snr,
1301
1302 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1303 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1304
1305 .set_tone = m88ds3103_set_tone,
1306 };
1307
1308 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1309 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1310 MODULE_LICENSE("GPL");
1311 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
Linux with added FPC-III support