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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / i2c / ad9389b.c
blob83225d6a0dd96069f62976ae5255deeee4374005
1 /*
2 * Analog Devices AD9389B/AD9889B video encoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 */
19
20 /*
21 * References (c = chapter, p = page):
22 * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
23 * HDMI Transitter, Rev. A, October 2010
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/slab.h>
29 #include <linux/i2c.h>
30 #include <linux/delay.h>
31 #include <linux/videodev2.h>
32 #include <linux/workqueue.h>
33 #include <linux/v4l2-dv-timings.h>
34 #include <media/v4l2-device.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-dv-timings.h>
37 #include <media/v4l2-ctrls.h>
38 #include <media/ad9389b.h>
39
40 static int debug;
41 module_param(debug, int, 0644);
42 MODULE_PARM_DESC(debug, "debug level (0-2)");
43
44 MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
46 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
47 MODULE_LICENSE("GPL");
48
49 #define MASK_AD9389B_EDID_RDY_INT 0x04
50 #define MASK_AD9389B_MSEN_INT 0x40
51 #define MASK_AD9389B_HPD_INT 0x80
52
53 #define MASK_AD9389B_HPD_DETECT 0x40
54 #define MASK_AD9389B_MSEN_DETECT 0x20
55 #define MASK_AD9389B_EDID_RDY 0x10
56
57 #define EDID_MAX_RETRIES (8)
58 #define EDID_DELAY 250
59 #define EDID_MAX_SEGM 8
60
61 /*
62 **********************************************************************
63 *
64 * Arrays with configuration parameters for the AD9389B
65 *
66 **********************************************************************
67 */
68
69 struct ad9389b_state_edid {
70 /* total number of blocks */
71 u32 blocks;
72 /* Number of segments read */
73 u32 segments;
74 u8 data[EDID_MAX_SEGM * 256];
75 /* Number of EDID read retries left */
76 unsigned read_retries;
77 };
78
79 struct ad9389b_state {
80 struct ad9389b_platform_data pdata;
81 struct v4l2_subdev sd;
82 struct media_pad pad;
83 struct v4l2_ctrl_handler hdl;
84 int chip_revision;
85 /* Is the ad9389b powered on? */
86 bool power_on;
87 /* Did we receive hotplug and rx-sense signals? */
88 bool have_monitor;
89 /* timings from s_dv_timings */
90 struct v4l2_dv_timings dv_timings;
91 /* controls */
92 struct v4l2_ctrl *hdmi_mode_ctrl;
93 struct v4l2_ctrl *hotplug_ctrl;
94 struct v4l2_ctrl *rx_sense_ctrl;
95 struct v4l2_ctrl *have_edid0_ctrl;
96 struct v4l2_ctrl *rgb_quantization_range_ctrl;
97 struct i2c_client *edid_i2c_client;
98 struct ad9389b_state_edid edid;
99 /* Running counter of the number of detected EDIDs (for debugging) */
100 unsigned edid_detect_counter;
101 struct workqueue_struct *work_queue;
102 struct delayed_work edid_handler; /* work entry */
103 };
104
105 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
106 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
107 static void ad9389b_setup(struct v4l2_subdev *sd);
108 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
109 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
110
111 static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
112 {
113 return container_of(sd, struct ad9389b_state, sd);
114 }
115
116 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
117 {
118 return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
119 }
120
121 /* ------------------------ I2C ----------------------------------------------- */
122
123 static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
124 {
125 struct i2c_client *client = v4l2_get_subdevdata(sd);
126
127 return i2c_smbus_read_byte_data(client, reg);
128 }
129
130 static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
131 {
132 struct i2c_client *client = v4l2_get_subdevdata(sd);
133 int ret;
134 int i;
135
136 for (i = 0; i < 3; i++) {
137 ret = i2c_smbus_write_byte_data(client, reg, val);
138 if (ret == 0)
139 return 0;
140 }
141 v4l2_err(sd, "%s: failed reg 0x%x, val 0x%x\n", __func__, reg, val);
142 return ret;
143 }
144
145 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
146 and then the value-mask (to be OR-ed). */
147 static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
148 u8 clr_mask, u8 val_mask)
149 {
150 ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
151 }
152
153 static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
154 {
155 struct ad9389b_state *state = get_ad9389b_state(sd);
156 int i;
157
158 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
159
160 for (i = 0; i < len; i++)
161 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
162 }
163
164 static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
165 {
166 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
167 }
168
169 static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
170 {
171 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
172 }
173
174 static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
175 {
176 ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
177 ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
178 }
179
180 static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
181 u16 A1, u16 A2, u16 A3, u16 A4,
182 u16 B1, u16 B2, u16 B3, u16 B4,
183 u16 C1, u16 C2, u16 C3, u16 C4)
184 {
185 /* A */
186 ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
187 ad9389b_wr(sd, 0x19, A1);
188 ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
189 ad9389b_wr(sd, 0x1B, A2);
190 ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
191 ad9389b_wr(sd, 0x1d, A3);
192 ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
193 ad9389b_wr(sd, 0x1f, A4);
194
195 /* B */
196 ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
197 ad9389b_wr(sd, 0x21, B1);
198 ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
199 ad9389b_wr(sd, 0x23, B2);
200 ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
201 ad9389b_wr(sd, 0x25, B3);
202 ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
203 ad9389b_wr(sd, 0x27, B4);
204
205 /* C */
206 ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
207 ad9389b_wr(sd, 0x29, C1);
208 ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
209 ad9389b_wr(sd, 0x2B, C2);
210 ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
211 ad9389b_wr(sd, 0x2D, C3);
212 ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
213 ad9389b_wr(sd, 0x2F, C4);
214 }
215
216 static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
217 {
218 if (enable) {
219 u8 csc_mode = 0;
220
221 ad9389b_csc_conversion_mode(sd, csc_mode);
222 ad9389b_csc_coeff(sd,
223 4096-564, 0, 0, 256,
224 0, 4096-564, 0, 256,
225 0, 0, 4096-564, 256);
226 /* enable CSC */
227 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
228 /* AVI infoframe: Limited range RGB (16-235) */
229 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
230 } else {
231 /* disable CSC */
232 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
233 /* AVI infoframe: Full range RGB (0-255) */
234 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
235 }
236 }
237
238 static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
239 {
240 struct ad9389b_state *state = get_ad9389b_state(sd);
241
242 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
243 /* CEA format, not IT */
244 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
245 } else {
246 /* IT format */
247 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
248 }
249 }
250
251 static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
252 {
253 struct ad9389b_state *state = get_ad9389b_state(sd);
254
255 switch (ctrl->val) {
256 case V4L2_DV_RGB_RANGE_AUTO:
257 /* automatic */
258 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
259 /* cea format, RGB limited range (16-235) */
260 ad9389b_csc_rgb_full2limit(sd, true);
261 } else {
262 /* not cea format, RGB full range (0-255) */
263 ad9389b_csc_rgb_full2limit(sd, false);
264 }
265 break;
266 case V4L2_DV_RGB_RANGE_LIMITED:
267 /* RGB limited range (16-235) */
268 ad9389b_csc_rgb_full2limit(sd, true);
269 break;
270 case V4L2_DV_RGB_RANGE_FULL:
271 /* RGB full range (0-255) */
272 ad9389b_csc_rgb_full2limit(sd, false);
273 break;
274 default:
275 return -EINVAL;
276 }
277 return 0;
278 }
279
280 static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
281 {
282 u8 gear;
283
284 /* Workaround for TMDS PLL problem
285 * The TMDS PLL in AD9389b change gear when the chip is heated above a
286 * certain temperature. The output is disabled when the PLL change gear
287 * so the monitor has to lock on the signal again. A workaround for
288 * this is to use the manual PLL gears. This is a solution from Analog
289 * Devices that is not documented in the datasheets.
290 * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
291 *
292 * The pixel frequency ranges are based on readout of the gear the
293 * automatic gearing selects for different pixel clocks
294 * (read from 0x9e [3:1]).
295 */
296
297 if (pixelclock > 140000000)
298 gear = 0xc0; /* 4th gear */
299 else if (pixelclock > 117000000)
300 gear = 0xb0; /* 3rd gear */
301 else if (pixelclock > 87000000)
302 gear = 0xa0; /* 2nd gear */
303 else if (pixelclock > 60000000)
304 gear = 0x90; /* 1st gear */
305 else
306 gear = 0x80; /* 0th gear */
307
308 ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
309 }
310
311 /* ------------------------------ CTRL OPS ------------------------------ */
312
313 static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
314 {
315 struct v4l2_subdev *sd = to_sd(ctrl);
316 struct ad9389b_state *state = get_ad9389b_state(sd);
317
318 v4l2_dbg(1, debug, sd,
319 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
320
321 if (state->hdmi_mode_ctrl == ctrl) {
322 /* Set HDMI or DVI-D */
323 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
324 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
325 return 0;
326 }
327 if (state->rgb_quantization_range_ctrl == ctrl)
328 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
329 return -EINVAL;
330 }
331
332 static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
333 .s_ctrl = ad9389b_s_ctrl,
334 };
335
336 /* ---------------------------- CORE OPS ------------------------------------------- */
337
338 #ifdef CONFIG_VIDEO_ADV_DEBUG
339 static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
340 {
341 reg->val = ad9389b_rd(sd, reg->reg & 0xff);
342 reg->size = 1;
343 return 0;
344 }
345
346 static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
347 {
348 ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
349 return 0;
350 }
351 #endif
352
353 static int ad9389b_log_status(struct v4l2_subdev *sd)
354 {
355 struct ad9389b_state *state = get_ad9389b_state(sd);
356 struct ad9389b_state_edid *edid = &state->edid;
357
358 static const char * const states[] = {
359 "in reset",
360 "reading EDID",
361 "idle",
362 "initializing HDCP",
363 "HDCP enabled",
364 "initializing HDCP repeater",
365 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
366 };
367 static const char * const errors[] = {
368 "no error",
369 "bad receiver BKSV",
370 "Ri mismatch",
371 "Pj mismatch",
372 "i2c error",
373 "timed out",
374 "max repeater cascade exceeded",
375 "hash check failed",
376 "too many devices",
377 "9", "A", "B", "C", "D", "E", "F"
378 };
379
380 u8 manual_gear;
381
382 v4l2_info(sd, "chip revision %d\n", state->chip_revision);
383 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
384 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
385 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
386 "detected" : "no",
387 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
388 "detected" : "no",
389 edid->segments ? "found" : "no", edid->blocks);
390 v4l2_info(sd, "%s output %s\n",
391 (ad9389b_rd(sd, 0xaf) & 0x02) ?
392 "HDMI" : "DVI-D",
393 (ad9389b_rd(sd, 0xa1) & 0x3c) ?
394 "disabled" : "enabled");
395 v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
396 "encrypted" : "no encryption");
397 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
398 states[ad9389b_rd(sd, 0xc8) & 0xf],
399 errors[ad9389b_rd(sd, 0xc8) >> 4],
400 state->edid_detect_counter,
401 ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
402 manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
403 v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
404 ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
405 v4l2_info(sd, "ad9389b: %s gear %d\n",
406 manual_gear ? "manual" : "automatic",
407 manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
408 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
409 if (ad9389b_rd(sd, 0xaf) & 0x02) {
410 /* HDMI only */
411 u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
412 u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
413 ad9389b_rd(sd, 0x02) << 8 |
414 ad9389b_rd(sd, 0x03);
415 u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
416 u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
417 u32 CTS;
418
419 if (manual_cts)
420 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
421 ad9389b_rd(sd, 0x08) << 8 |
422 ad9389b_rd(sd, 0x09);
423 else
424 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
425 ad9389b_rd(sd, 0x05) << 8 |
426 ad9389b_rd(sd, 0x06);
427 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
428 ad9389b_rd(sd, 0x02) << 8 |
429 ad9389b_rd(sd, 0x03);
430
431 v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
432 manual_cts ? "manual" : "automatic", N, CTS);
433
434 v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
435 vic_detect, vic_sent);
436 }
437 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
438 v4l2_print_dv_timings(sd->name, "timings: ",
439 &state->dv_timings, false);
440 else
441 v4l2_info(sd, "no timings set\n");
442 return 0;
443 }
444
445 /* Power up/down ad9389b */
446 static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
447 {
448 struct ad9389b_state *state = get_ad9389b_state(sd);
449 struct ad9389b_platform_data *pdata = &state->pdata;
450 const int retries = 20;
451 int i;
452
453 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
454
455 state->power_on = on;
456
457 if (!on) {
458 /* Power down */
459 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
460 return true;
461 }
462
463 /* Power up */
464 /* The ad9389b does not always come up immediately.
465 Retry multiple times. */
466 for (i = 0; i < retries; i++) {
467 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
468 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
469 break;
470 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
471 msleep(10);
472 }
473 if (i == retries) {
474 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
475 ad9389b_s_power(sd, 0);
476 return false;
477 }
478 if (i > 1)
479 v4l2_dbg(1, debug, sd,
480 "needed %d retries to powerup the ad9389b\n", i);
481
482 /* Select chip: AD9389B */
483 ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
484
485 /* Reserved registers that must be set according to REF_01 p. 11*/
486 ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
487 ad9389b_wr(sd, 0x9c, 0x38);
488 ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
489
490 /* Differential output drive strength */
491 if (pdata->diff_data_drive_strength > 0)
492 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
493 else
494 ad9389b_wr(sd, 0xa2, 0x87);
495
496 if (pdata->diff_clk_drive_strength > 0)
497 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
498 else
499 ad9389b_wr(sd, 0xa3, 0x87);
500
501 ad9389b_wr(sd, 0x0a, 0x01);
502 ad9389b_wr(sd, 0xbb, 0xff);
503
504 /* Set number of attempts to read the EDID */
505 ad9389b_wr(sd, 0xc9, 0xf);
506 return true;
507 }
508
509 /* Enable interrupts */
510 static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
511 {
512 u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
513 u8 irqs_rd;
514 int retries = 100;
515
516 /* The datasheet says that the EDID ready interrupt should be
517 disabled if there is no hotplug. */
518 if (!enable)
519 irqs = 0;
520 else if (ad9389b_have_hotplug(sd))
521 irqs |= MASK_AD9389B_EDID_RDY_INT;
522
523 /*
524 * This i2c write can fail (approx. 1 in 1000 writes). But it
525 * is essential that this register is correct, so retry it
526 * multiple times.
527 *
528 * Note that the i2c write does not report an error, but the readback
529 * clearly shows the wrong value.
530 */
531 do {
532 ad9389b_wr(sd, 0x94, irqs);
533 irqs_rd = ad9389b_rd(sd, 0x94);
534 } while (retries-- && irqs_rd != irqs);
535
536 if (irqs_rd != irqs)
537 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
538 }
539
540 /* Interrupt handler */
541 static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
542 {
543 u8 irq_status;
544
545 /* disable interrupts to prevent a race condition */
546 ad9389b_set_isr(sd, false);
547 irq_status = ad9389b_rd(sd, 0x96);
548 /* clear detected interrupts */
549 ad9389b_wr(sd, 0x96, irq_status);
550 /* enable interrupts */
551 ad9389b_set_isr(sd, true);
552
553 v4l2_dbg(1, debug, sd, "%s: irq_status 0x%x\n", __func__, irq_status);
554
555 if (irq_status & (MASK_AD9389B_HPD_INT))
556 ad9389b_check_monitor_present_status(sd);
557 if (irq_status & MASK_AD9389B_EDID_RDY_INT)
558 ad9389b_check_edid_status(sd);
559
560 *handled = true;
561 return 0;
562 }
563
564 static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
565 .log_status = ad9389b_log_status,
566 #ifdef CONFIG_VIDEO_ADV_DEBUG
567 .g_register = ad9389b_g_register,
568 .s_register = ad9389b_s_register,
569 #endif
570 .s_power = ad9389b_s_power,
571 .interrupt_service_routine = ad9389b_isr,
572 };
573
574 /* ------------------------------ PAD OPS ------------------------------ */
575
576 static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
577 {
578 struct ad9389b_state *state = get_ad9389b_state(sd);
579
580 if (edid->pad != 0)
581 return -EINVAL;
582 if (edid->blocks == 0 || edid->blocks > 256)
583 return -EINVAL;
584 if (!edid->edid)
585 return -EINVAL;
586 if (!state->edid.segments) {
587 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
588 return -ENODATA;
589 }
590 if (edid->start_block >= state->edid.segments * 2)
591 return -E2BIG;
592 if (edid->blocks + edid->start_block >= state->edid.segments * 2)
593 edid->blocks = state->edid.segments * 2 - edid->start_block;
594 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
595 128 * edid->blocks);
596 return 0;
597 }
598
599 static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
600 .get_edid = ad9389b_get_edid,
601 };
602
603 /* ------------------------------ VIDEO OPS ------------------------------ */
604
605 /* Enable/disable ad9389b output */
606 static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
607 {
608 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
609
610 ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
611 if (enable) {
612 ad9389b_check_monitor_present_status(sd);
613 } else {
614 ad9389b_s_power(sd, 0);
615 }
616 return 0;
617 }
618
619 static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
620 .type = V4L2_DV_BT_656_1120,
621 /* keep this initialization for compatibility with GCC < 4.4.6 */
622 .reserved = { 0 },
623 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
624 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
625 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
626 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
627 V4L2_DV_BT_CAP_CUSTOM)
628 };
629
630 static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
631 struct v4l2_dv_timings *timings)
632 {
633 struct ad9389b_state *state = get_ad9389b_state(sd);
634
635 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
636
637 /* quick sanity check */
638 if (!v4l2_valid_dv_timings(timings, &ad9389b_timings_cap, NULL, NULL))
639 return -EINVAL;
640
641 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
642 if the format is one of the CEA or DMT timings. */
643 v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0, NULL, NULL);
644
645 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
646
647 /* save timings */
648 state->dv_timings = *timings;
649
650 /* update quantization range based on new dv_timings */
651 ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
652
653 /* update PLL gear based on new dv_timings */
654 if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
655 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
656
657 /* update AVI infoframe */
658 ad9389b_set_IT_content_AVI_InfoFrame(sd);
659
660 return 0;
661 }
662
663 static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
664 struct v4l2_dv_timings *timings)
665 {
666 struct ad9389b_state *state = get_ad9389b_state(sd);
667
668 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
669
670 if (!timings)
671 return -EINVAL;
672
673 *timings = state->dv_timings;
674
675 return 0;
676 }
677
678 static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
679 struct v4l2_enum_dv_timings *timings)
680 {
681 return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap,
682 NULL, NULL);
683 }
684
685 static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
686 struct v4l2_dv_timings_cap *cap)
687 {
688 *cap = ad9389b_timings_cap;
689 return 0;
690 }
691
692 static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
693 .s_stream = ad9389b_s_stream,
694 .s_dv_timings = ad9389b_s_dv_timings,
695 .g_dv_timings = ad9389b_g_dv_timings,
696 .enum_dv_timings = ad9389b_enum_dv_timings,
697 .dv_timings_cap = ad9389b_dv_timings_cap,
698 };
699
700 static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
701 {
702 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
703
704 if (enable)
705 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
706 else
707 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
708
709 return 0;
710 }
711
712 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
713 {
714 u32 N;
715
716 switch (freq) {
717 case 32000: N = 4096; break;
718 case 44100: N = 6272; break;
719 case 48000: N = 6144; break;
720 case 88200: N = 12544; break;
721 case 96000: N = 12288; break;
722 case 176400: N = 25088; break;
723 case 192000: N = 24576; break;
724 default:
725 return -EINVAL;
726 }
727
728 /* Set N (used with CTS to regenerate the audio clock) */
729 ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
730 ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
731 ad9389b_wr(sd, 0x03, N & 0xff);
732
733 return 0;
734 }
735
736 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
737 {
738 u32 i2s_sf;
739
740 switch (freq) {
741 case 32000: i2s_sf = 0x30; break;
742 case 44100: i2s_sf = 0x00; break;
743 case 48000: i2s_sf = 0x20; break;
744 case 88200: i2s_sf = 0x80; break;
745 case 96000: i2s_sf = 0xa0; break;
746 case 176400: i2s_sf = 0xc0; break;
747 case 192000: i2s_sf = 0xe0; break;
748 default:
749 return -EINVAL;
750 }
751
752 /* Set sampling frequency for I2S audio to 48 kHz */
753 ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
754
755 return 0;
756 }
757
758 static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
759 {
760 /* TODO based on input/output/config */
761 /* TODO See datasheet "Programmers guide" p. 39-40 */
762
763 /* Only 2 channels in use for application */
764 ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
765 /* Speaker mapping */
766 ad9389b_wr(sd, 0x51, 0x00);
767
768 /* TODO Where should this be placed? */
769 /* 16 bit audio word length */
770 ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
771
772 return 0;
773 }
774
775 static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
776 .s_stream = ad9389b_s_audio_stream,
777 .s_clock_freq = ad9389b_s_clock_freq,
778 .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
779 .s_routing = ad9389b_s_routing,
780 };
781
782 /* --------------------- SUBDEV OPS --------------------------------------- */
783
784 static const struct v4l2_subdev_ops ad9389b_ops = {
785 .core = &ad9389b_core_ops,
786 .video = &ad9389b_video_ops,
787 .audio = &ad9389b_audio_ops,
788 .pad = &ad9389b_pad_ops,
789 };
790
791 /* ----------------------------------------------------------------------- */
792 static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
793 int segment, u8 *buf)
794 {
795 int i, j;
796
797 if (debug < lvl)
798 return;
799
800 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
801 for (i = 0; i < 256; i += 16) {
802 u8 b[128];
803 u8 *bp = b;
804
805 if (i == 128)
806 v4l2_dbg(lvl, debug, sd, "\n");
807 for (j = i; j < i + 16; j++) {
808 sprintf(bp, "0x%02x, ", buf[j]);
809 bp += 6;
810 }
811 bp[0] = '\0';
812 v4l2_dbg(lvl, debug, sd, "%s\n", b);
813 }
814 }
815
816 static void ad9389b_edid_handler(struct work_struct *work)
817 {
818 struct delayed_work *dwork = to_delayed_work(work);
819 struct ad9389b_state *state =
820 container_of(dwork, struct ad9389b_state, edid_handler);
821 struct v4l2_subdev *sd = &state->sd;
822 struct ad9389b_edid_detect ed;
823
824 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
825
826 if (ad9389b_check_edid_status(sd)) {
827 /* Return if we received the EDID. */
828 return;
829 }
830
831 if (ad9389b_have_hotplug(sd)) {
832 /* We must retry reading the EDID several times, it is possible
833 * that initially the EDID couldn't be read due to i2c errors
834 * (DVI connectors are particularly prone to this problem). */
835 if (state->edid.read_retries) {
836 state->edid.read_retries--;
837 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
838 ad9389b_s_power(sd, false);
839 ad9389b_s_power(sd, true);
840 queue_delayed_work(state->work_queue,
841 &state->edid_handler, EDID_DELAY);
842 return;
843 }
844 }
845
846 /* We failed to read the EDID, so send an event for this. */
847 ed.present = false;
848 ed.segment = ad9389b_rd(sd, 0xc4);
849 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
850 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
851 }
852
853 static void ad9389b_audio_setup(struct v4l2_subdev *sd)
854 {
855 v4l2_dbg(1, debug, sd, "%s\n", __func__);
856
857 ad9389b_s_i2s_clock_freq(sd, 48000);
858 ad9389b_s_clock_freq(sd, 48000);
859 ad9389b_s_routing(sd, 0, 0, 0);
860 }
861
862 /* Initial setup of AD9389b */
863
864 /* Configure hdmi transmitter. */
865 static void ad9389b_setup(struct v4l2_subdev *sd)
866 {
867 struct ad9389b_state *state = get_ad9389b_state(sd);
868
869 v4l2_dbg(1, debug, sd, "%s\n", __func__);
870
871 /* Input format: RGB 4:4:4 */
872 ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
873 /* Output format: RGB 4:4:4 */
874 ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
875 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
876 Aspect ratio: 16:9 */
877 ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
878 /* Output format: RGB 4:4:4, Active Format Information is valid. */
879 ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
880 /* Underscanned */
881 ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
882 /* Setup video format */
883 ad9389b_wr(sd, 0x3c, 0x0);
884 /* Active format aspect ratio: same as picure. */
885 ad9389b_wr(sd, 0x47, 0x80);
886 /* No encryption */
887 ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
888 /* Positive clk edge capture for input video clock */
889 ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
890
891 ad9389b_audio_setup(sd);
892
893 v4l2_ctrl_handler_setup(&state->hdl);
894
895 ad9389b_set_IT_content_AVI_InfoFrame(sd);
896 }
897
898 static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
899 {
900 struct ad9389b_monitor_detect mdt;
901 struct ad9389b_state *state = get_ad9389b_state(sd);
902
903 mdt.present = state->have_monitor;
904 v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
905 }
906
907 static void ad9389b_update_monitor_present_status(struct v4l2_subdev *sd)
908 {
909 struct ad9389b_state *state = get_ad9389b_state(sd);
910 /* read hotplug and rx-sense state */
911 u8 status = ad9389b_rd(sd, 0x42);
912
913 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
914 __func__,
915 status,
916 status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
917 status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
918
919 if (status & MASK_AD9389B_HPD_DETECT) {
920 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
921 state->have_monitor = true;
922 if (!ad9389b_s_power(sd, true)) {
923 v4l2_dbg(1, debug, sd,
924 "%s: monitor detected, powerup failed\n", __func__);
925 return;
926 }
927 ad9389b_setup(sd);
928 ad9389b_notify_monitor_detect(sd);
929 state->edid.read_retries = EDID_MAX_RETRIES;
930 queue_delayed_work(state->work_queue,
931 &state->edid_handler, EDID_DELAY);
932 } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
933 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
934 state->have_monitor = false;
935 ad9389b_notify_monitor_detect(sd);
936 ad9389b_s_power(sd, false);
937 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
938 }
939
940 /* update read only ctrls */
941 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
942 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
943 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
944
945 /* update with setting from ctrls */
946 ad9389b_s_ctrl(state->rgb_quantization_range_ctrl);
947 ad9389b_s_ctrl(state->hdmi_mode_ctrl);
948 }
949
950 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
951 {
952 struct ad9389b_state *state = get_ad9389b_state(sd);
953 int retry = 0;
954
955 ad9389b_update_monitor_present_status(sd);
956
957 /*
958 * Rapid toggling of the hotplug may leave the chip powered off,
959 * even if we think it is on. In that case reset and power up again.
960 */
961 while (state->power_on && (ad9389b_rd(sd, 0x41) & 0x40)) {
962 if (++retry > 5) {
963 v4l2_err(sd, "retried %d times, give up\n", retry);
964 return;
965 }
966 v4l2_dbg(1, debug, sd, "%s: reset and re-check status (%d)\n", __func__, retry);
967 ad9389b_notify_monitor_detect(sd);
968 cancel_delayed_work_sync(&state->edid_handler);
969 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
970 ad9389b_s_power(sd, false);
971 ad9389b_update_monitor_present_status(sd);
972 }
973 }
974
975 static bool edid_block_verify_crc(u8 *edid_block)
976 {
977 u8 sum = 0;
978 int i;
979
980 for (i = 0; i < 128; i++)
981 sum += edid_block[i];
982 return sum == 0;
983 }
984
985 static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
986 {
987 struct ad9389b_state *state = get_ad9389b_state(sd);
988 u32 blocks = state->edid.blocks;
989 u8 *data = state->edid.data;
990
991 if (edid_block_verify_crc(&data[segment * 256])) {
992 if ((segment + 1) * 2 <= blocks)
993 return edid_block_verify_crc(&data[segment * 256 + 128]);
994 return true;
995 }
996 return false;
997 }
998
999 static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
1000 {
1001 static const u8 hdmi_header[] = {
1002 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1003 };
1004 struct ad9389b_state *state = get_ad9389b_state(sd);
1005 u8 *data = state->edid.data;
1006 int i;
1007
1008 if (segment)
1009 return true;
1010
1011 for (i = 0; i < ARRAY_SIZE(hdmi_header); i++)
1012 if (data[i] != hdmi_header[i])
1013 return false;
1014
1015 return true;
1016 }
1017
1018 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1019 {
1020 struct ad9389b_state *state = get_ad9389b_state(sd);
1021 struct ad9389b_edid_detect ed;
1022 int segment;
1023 u8 edidRdy = ad9389b_rd(sd, 0xc5);
1024
1025 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1026 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1027
1028 if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1029 return false;
1030
1031 segment = ad9389b_rd(sd, 0xc4);
1032 if (segment >= EDID_MAX_SEGM) {
1033 v4l2_err(sd, "edid segment number too big\n");
1034 return false;
1035 }
1036 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1037 ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1038 ad9389b_dbg_dump_edid(2, debug, sd, segment,
1039 &state->edid.data[segment * 256]);
1040 if (segment == 0) {
1041 state->edid.blocks = state->edid.data[0x7e] + 1;
1042 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1043 __func__, state->edid.blocks);
1044 }
1045 if (!edid_verify_crc(sd, segment) ||
1046 !edid_verify_header(sd, segment)) {
1047 /* edid crc error, force reread of edid segment */
1048 v4l2_err(sd, "%s: edid crc or header error\n", __func__);
1049 ad9389b_s_power(sd, false);
1050 ad9389b_s_power(sd, true);
1051 return false;
1052 }
1053 /* one more segment read ok */
1054 state->edid.segments = segment + 1;
1055 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1056 /* Request next EDID segment */
1057 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1058 __func__, state->edid.segments);
1059 ad9389b_wr(sd, 0xc9, 0xf);
1060 ad9389b_wr(sd, 0xc4, state->edid.segments);
1061 state->edid.read_retries = EDID_MAX_RETRIES;
1062 queue_delayed_work(state->work_queue,
1063 &state->edid_handler, EDID_DELAY);
1064 return false;
1065 }
1066
1067 /* report when we have all segments but report only for segment 0 */
1068 ed.present = true;
1069 ed.segment = 0;
1070 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1071 state->edid_detect_counter++;
1072 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1073 return ed.present;
1074 }
1075
1076 /* ----------------------------------------------------------------------- */
1077
1078 static void ad9389b_init_setup(struct v4l2_subdev *sd)
1079 {
1080 struct ad9389b_state *state = get_ad9389b_state(sd);
1081 struct ad9389b_state_edid *edid = &state->edid;
1082
1083 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1084
1085 /* clear all interrupts */
1086 ad9389b_wr(sd, 0x96, 0xff);
1087
1088 memset(edid, 0, sizeof(struct ad9389b_state_edid));
1089 state->have_monitor = false;
1090 ad9389b_set_isr(sd, false);
1091 }
1092
1093 static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1094 {
1095 const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1096 struct ad9389b_state *state;
1097 struct ad9389b_platform_data *pdata = client->dev.platform_data;
1098 struct v4l2_ctrl_handler *hdl;
1099 struct v4l2_subdev *sd;
1100 int err = -EIO;
1101
1102 /* Check if the adapter supports the needed features */
1103 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1104 return -EIO;
1105
1106 v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1107 client->addr << 1);
1108
1109 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1110 if (!state)
1111 return -ENOMEM;
1112
1113 /* Platform data */
1114 if (pdata == NULL) {
1115 v4l_err(client, "No platform data!\n");
1116 return -ENODEV;
1117 }
1118 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1119
1120 sd = &state->sd;
1121 v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1122 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1123
1124 hdl = &state->hdl;
1125 v4l2_ctrl_handler_init(hdl, 5);
1126
1127 /* private controls */
1128
1129 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1130 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1131 0, V4L2_DV_TX_MODE_DVI_D);
1132 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1133 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1134 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1135 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1136 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1137 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1138 state->rgb_quantization_range_ctrl =
1139 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1140 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1141 0, V4L2_DV_RGB_RANGE_AUTO);
1142 sd->ctrl_handler = hdl;
1143 if (hdl->error) {
1144 err = hdl->error;
1145
1146 goto err_hdl;
1147 }
1148 state->hdmi_mode_ctrl->is_private = true;
1149 state->hotplug_ctrl->is_private = true;
1150 state->rx_sense_ctrl->is_private = true;
1151 state->have_edid0_ctrl->is_private = true;
1152 state->rgb_quantization_range_ctrl->is_private = true;
1153
1154 state->pad.flags = MEDIA_PAD_FL_SINK;
1155 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1156 if (err)
1157 goto err_hdl;
1158
1159 state->chip_revision = ad9389b_rd(sd, 0x0);
1160 if (state->chip_revision != 2) {
1161 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1162 err = -EIO;
1163 goto err_entity;
1164 }
1165 v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1166 ad9389b_rd(sd, 0x41), state->chip_revision);
1167
1168 state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1169 if (state->edid_i2c_client == NULL) {
1170 v4l2_err(sd, "failed to register edid i2c client\n");
1171 err = -ENOMEM;
1172 goto err_entity;
1173 }
1174
1175 state->work_queue = create_singlethread_workqueue(sd->name);
1176 if (state->work_queue == NULL) {
1177 v4l2_err(sd, "could not create workqueue\n");
1178 err = -ENOMEM;
1179 goto err_unreg;
1180 }
1181
1182 INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1183 state->dv_timings = dv1080p60;
1184
1185 ad9389b_init_setup(sd);
1186 ad9389b_set_isr(sd, true);
1187
1188 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1189 client->addr << 1, client->adapter->name);
1190 return 0;
1191
1192 err_unreg:
1193 i2c_unregister_device(state->edid_i2c_client);
1194 err_entity:
1195 media_entity_cleanup(&sd->entity);
1196 err_hdl:
1197 v4l2_ctrl_handler_free(&state->hdl);
1198 return err;
1199 }
1200
1201 /* ----------------------------------------------------------------------- */
1202
1203 static int ad9389b_remove(struct i2c_client *client)
1204 {
1205 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1206 struct ad9389b_state *state = get_ad9389b_state(sd);
1207
1208 state->chip_revision = -1;
1209
1210 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1211 client->addr << 1, client->adapter->name);
1212
1213 ad9389b_s_stream(sd, false);
1214 ad9389b_s_audio_stream(sd, false);
1215 ad9389b_init_setup(sd);
1216 cancel_delayed_work(&state->edid_handler);
1217 i2c_unregister_device(state->edid_i2c_client);
1218 destroy_workqueue(state->work_queue);
1219 v4l2_device_unregister_subdev(sd);
1220 media_entity_cleanup(&sd->entity);
1221 v4l2_ctrl_handler_free(sd->ctrl_handler);
1222 return 0;
1223 }
1224
1225 /* ----------------------------------------------------------------------- */
1226
1227 static struct i2c_device_id ad9389b_id[] = {
1228 { "ad9389b", 0 },
1229 { "ad9889b", 0 },
1230 { }
1231 };
1232 MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1233
1234 static struct i2c_driver ad9389b_driver = {
1235 .driver = {
1236 .owner = THIS_MODULE,
1237 .name = "ad9389b",
1238 },
1239 .probe = ad9389b_probe,
1240 .remove = ad9389b_remove,
1241 .id_table = ad9389b_id,
1242 };
1243
1244 module_i2c_driver(ad9389b_driver);
Linux with added FPC-III support