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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / i2c / soc_camera / ov6650.c
blobab01598ec83fefb759587b87ae905f8a8c3174f5
1 /*
2 * V4L2 SoC Camera driver for OmniVision OV6650 Camera Sensor
3 *
4 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
5 *
6 * Based on OmniVision OV96xx Camera Driver
7 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
8 *
9 * Based on ov772x camera driver:
10 * Copyright (C) 2008 Renesas Solutions Corp.
11 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
12 *
13 * Based on ov7670 and soc_camera_platform driver,
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
15 * Copyright (C) 2008 Magnus Damm
16 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 *
18 * Hardware specific bits initialy based on former work by Matt Callow
19 * drivers/media/video/omap/sensor_ov6650.c
20 * Copyright (C) 2006 Matt Callow
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 */
26
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/v4l2-mediabus.h>
32 #include <linux/module.h>
33
34 #include <media/soc_camera.h>
35 #include <media/v4l2-clk.h>
36 #include <media/v4l2-ctrls.h>
37
38 /* Register definitions */
39 #define REG_GAIN 0x00 /* range 00 - 3F */
40 #define REG_BLUE 0x01
41 #define REG_RED 0x02
42 #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
43 #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
44
45 #define REG_BRT 0x06
46
47 #define REG_PIDH 0x0a
48 #define REG_PIDL 0x0b
49
50 #define REG_AECH 0x10
51 #define REG_CLKRC 0x11 /* Data Format and Internal Clock */
52 /* [7:6] Input system clock (MHz)*/
53 /* 00=8, 01=12, 10=16, 11=24 */
54 /* [5:0]: Internal Clock Pre-Scaler */
55 #define REG_COMA 0x12 /* [7] Reset */
56 #define REG_COMB 0x13
57 #define REG_COMC 0x14
58 #define REG_COMD 0x15
59 #define REG_COML 0x16
60 #define REG_HSTRT 0x17
61 #define REG_HSTOP 0x18
62 #define REG_VSTRT 0x19
63 #define REG_VSTOP 0x1a
64 #define REG_PSHFT 0x1b
65 #define REG_MIDH 0x1c
66 #define REG_MIDL 0x1d
67 #define REG_HSYNS 0x1e
68 #define REG_HSYNE 0x1f
69 #define REG_COME 0x20
70 #define REG_YOFF 0x21
71 #define REG_UOFF 0x22
72 #define REG_VOFF 0x23
73 #define REG_AEW 0x24
74 #define REG_AEB 0x25
75 #define REG_COMF 0x26
76 #define REG_COMG 0x27
77 #define REG_COMH 0x28
78 #define REG_COMI 0x29
79
80 #define REG_FRARL 0x2b
81 #define REG_COMJ 0x2c
82 #define REG_COMK 0x2d
83 #define REG_AVGY 0x2e
84 #define REG_REF0 0x2f
85 #define REG_REF1 0x30
86 #define REG_REF2 0x31
87 #define REG_FRAJH 0x32
88 #define REG_FRAJL 0x33
89 #define REG_FACT 0x34
90 #define REG_L1AEC 0x35
91 #define REG_AVGU 0x36
92 #define REG_AVGV 0x37
93
94 #define REG_SPCB 0x60
95 #define REG_SPCC 0x61
96 #define REG_GAM1 0x62
97 #define REG_GAM2 0x63
98 #define REG_GAM3 0x64
99 #define REG_SPCD 0x65
100
101 #define REG_SPCE 0x68
102 #define REG_ADCL 0x69
103
104 #define REG_RMCO 0x6c
105 #define REG_GMCO 0x6d
106 #define REG_BMCO 0x6e
107
108
109 /* Register bits, values, etc. */
110 #define OV6650_PIDH 0x66 /* high byte of product ID number */
111 #define OV6650_PIDL 0x50 /* low byte of product ID number */
112 #define OV6650_MIDH 0x7F /* high byte of mfg ID */
113 #define OV6650_MIDL 0xA2 /* low byte of mfg ID */
114
115 #define DEF_GAIN 0x00
116 #define DEF_BLUE 0x80
117 #define DEF_RED 0x80
118
119 #define SAT_SHIFT 4
120 #define SAT_MASK (0xf << SAT_SHIFT)
121 #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
122
123 #define HUE_EN BIT(5)
124 #define HUE_MASK 0x1f
125 #define DEF_HUE 0x10
126 #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
127
128 #define DEF_AECH 0x4D
129
130 #define CLKRC_6MHz 0x00
131 #define CLKRC_12MHz 0x40
132 #define CLKRC_16MHz 0x80
133 #define CLKRC_24MHz 0xc0
134 #define CLKRC_DIV_MASK 0x3f
135 #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
136
137 #define COMA_RESET BIT(7)
138 #define COMA_QCIF BIT(5)
139 #define COMA_RAW_RGB BIT(4)
140 #define COMA_RGB BIT(3)
141 #define COMA_BW BIT(2)
142 #define COMA_WORD_SWAP BIT(1)
143 #define COMA_BYTE_SWAP BIT(0)
144 #define DEF_COMA 0x00
145
146 #define COMB_FLIP_V BIT(7)
147 #define COMB_FLIP_H BIT(5)
148 #define COMB_BAND_FILTER BIT(4)
149 #define COMB_AWB BIT(2)
150 #define COMB_AGC BIT(1)
151 #define COMB_AEC BIT(0)
152 #define DEF_COMB 0x5f
153
154 #define COML_ONE_CHANNEL BIT(7)
155
156 #define DEF_HSTRT 0x24
157 #define DEF_HSTOP 0xd4
158 #define DEF_VSTRT 0x04
159 #define DEF_VSTOP 0x94
160
161 #define COMF_HREF_LOW BIT(4)
162
163 #define COMJ_PCLK_RISING BIT(4)
164 #define COMJ_VSYNC_HIGH BIT(0)
165
166 /* supported resolutions */
167 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
168 #define W_CIF (W_QCIF << 1)
169 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
170 #define H_CIF (H_QCIF << 1)
171
172 #define FRAME_RATE_MAX 30
173
174
175 struct ov6650_reg {
176 u8 reg;
177 u8 val;
178 };
179
180 struct ov6650 {
181 struct v4l2_subdev subdev;
182 struct v4l2_ctrl_handler hdl;
183 struct {
184 /* exposure/autoexposure cluster */
185 struct v4l2_ctrl *autoexposure;
186 struct v4l2_ctrl *exposure;
187 };
188 struct {
189 /* gain/autogain cluster */
190 struct v4l2_ctrl *autogain;
191 struct v4l2_ctrl *gain;
192 };
193 struct {
194 /* blue/red/autowhitebalance cluster */
195 struct v4l2_ctrl *autowb;
196 struct v4l2_ctrl *blue;
197 struct v4l2_ctrl *red;
198 };
199 struct v4l2_clk *clk;
200 bool half_scale; /* scale down output by 2 */
201 struct v4l2_rect rect; /* sensor cropping window */
202 unsigned long pclk_limit; /* from host */
203 unsigned long pclk_max; /* from resolution and format */
204 struct v4l2_fract tpf; /* as requested with s_parm */
205 enum v4l2_mbus_pixelcode code;
206 enum v4l2_colorspace colorspace;
207 };
208
209
210 static enum v4l2_mbus_pixelcode ov6650_codes[] = {
211 V4L2_MBUS_FMT_YUYV8_2X8,
212 V4L2_MBUS_FMT_UYVY8_2X8,
213 V4L2_MBUS_FMT_YVYU8_2X8,
214 V4L2_MBUS_FMT_VYUY8_2X8,
215 V4L2_MBUS_FMT_SBGGR8_1X8,
216 V4L2_MBUS_FMT_Y8_1X8,
217 };
218
219 /* read a register */
220 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
221 {
222 int ret;
223 u8 data = reg;
224 struct i2c_msg msg = {
225 .addr = client->addr,
226 .flags = 0,
227 .len = 1,
228 .buf = &data,
229 };
230
231 ret = i2c_transfer(client->adapter, &msg, 1);
232 if (ret < 0)
233 goto err;
234
235 msg.flags = I2C_M_RD;
236 ret = i2c_transfer(client->adapter, &msg, 1);
237 if (ret < 0)
238 goto err;
239
240 *val = data;
241 return 0;
242
243 err:
244 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
245 return ret;
246 }
247
248 /* write a register */
249 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
250 {
251 int ret;
252 unsigned char data[2] = { reg, val };
253 struct i2c_msg msg = {
254 .addr = client->addr,
255 .flags = 0,
256 .len = 2,
257 .buf = data,
258 };
259
260 ret = i2c_transfer(client->adapter, &msg, 1);
261 udelay(100);
262
263 if (ret < 0) {
264 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
265 return ret;
266 }
267 return 0;
268 }
269
270
271 /* Read a register, alter its bits, write it back */
272 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
273 {
274 u8 val;
275 int ret;
276
277 ret = ov6650_reg_read(client, reg, &val);
278 if (ret) {
279 dev_err(&client->dev,
280 "[Read]-Modify-Write of register 0x%02x failed!\n",
281 reg);
282 return ret;
283 }
284
285 val &= ~mask;
286 val |= set;
287
288 ret = ov6650_reg_write(client, reg, val);
289 if (ret)
290 dev_err(&client->dev,
291 "Read-Modify-[Write] of register 0x%02x failed!\n",
292 reg);
293
294 return ret;
295 }
296
297 static struct ov6650 *to_ov6650(const struct i2c_client *client)
298 {
299 return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
300 }
301
302 /* Start/Stop streaming from the device */
303 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
304 {
305 return 0;
306 }
307
308 /* Get status of additional camera capabilities */
309 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
310 {
311 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
312 struct v4l2_subdev *sd = &priv->subdev;
313 struct i2c_client *client = v4l2_get_subdevdata(sd);
314 uint8_t reg, reg2;
315 int ret;
316
317 switch (ctrl->id) {
318 case V4L2_CID_AUTOGAIN:
319 ret = ov6650_reg_read(client, REG_GAIN, &reg);
320 if (!ret)
321 priv->gain->val = reg;
322 return ret;
323 case V4L2_CID_AUTO_WHITE_BALANCE:
324 ret = ov6650_reg_read(client, REG_BLUE, &reg);
325 if (!ret)
326 ret = ov6650_reg_read(client, REG_RED, &reg2);
327 if (!ret) {
328 priv->blue->val = reg;
329 priv->red->val = reg2;
330 }
331 return ret;
332 case V4L2_CID_EXPOSURE_AUTO:
333 ret = ov6650_reg_read(client, REG_AECH, &reg);
334 if (!ret)
335 priv->exposure->val = reg;
336 return ret;
337 }
338 return -EINVAL;
339 }
340
341 /* Set status of additional camera capabilities */
342 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
343 {
344 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
345 struct v4l2_subdev *sd = &priv->subdev;
346 struct i2c_client *client = v4l2_get_subdevdata(sd);
347 int ret;
348
349 switch (ctrl->id) {
350 case V4L2_CID_AUTOGAIN:
351 ret = ov6650_reg_rmw(client, REG_COMB,
352 ctrl->val ? COMB_AGC : 0, COMB_AGC);
353 if (!ret && !ctrl->val)
354 ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
355 return ret;
356 case V4L2_CID_AUTO_WHITE_BALANCE:
357 ret = ov6650_reg_rmw(client, REG_COMB,
358 ctrl->val ? COMB_AWB : 0, COMB_AWB);
359 if (!ret && !ctrl->val) {
360 ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
361 if (!ret)
362 ret = ov6650_reg_write(client, REG_RED,
363 priv->red->val);
364 }
365 return ret;
366 case V4L2_CID_SATURATION:
367 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
368 SAT_MASK);
369 case V4L2_CID_HUE:
370 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
371 HUE_MASK);
372 case V4L2_CID_BRIGHTNESS:
373 return ov6650_reg_write(client, REG_BRT, ctrl->val);
374 case V4L2_CID_EXPOSURE_AUTO:
375 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
376 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
377 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
378 ret = ov6650_reg_write(client, REG_AECH,
379 priv->exposure->val);
380 return ret;
381 case V4L2_CID_GAMMA:
382 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
383 case V4L2_CID_VFLIP:
384 return ov6650_reg_rmw(client, REG_COMB,
385 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
386 case V4L2_CID_HFLIP:
387 return ov6650_reg_rmw(client, REG_COMB,
388 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
389 }
390
391 return -EINVAL;
392 }
393
394 #ifdef CONFIG_VIDEO_ADV_DEBUG
395 static int ov6650_get_register(struct v4l2_subdev *sd,
396 struct v4l2_dbg_register *reg)
397 {
398 struct i2c_client *client = v4l2_get_subdevdata(sd);
399 int ret;
400 u8 val;
401
402 if (reg->reg & ~0xff)
403 return -EINVAL;
404
405 reg->size = 1;
406
407 ret = ov6650_reg_read(client, reg->reg, &val);
408 if (!ret)
409 reg->val = (__u64)val;
410
411 return ret;
412 }
413
414 static int ov6650_set_register(struct v4l2_subdev *sd,
415 const struct v4l2_dbg_register *reg)
416 {
417 struct i2c_client *client = v4l2_get_subdevdata(sd);
418
419 if (reg->reg & ~0xff || reg->val & ~0xff)
420 return -EINVAL;
421
422 return ov6650_reg_write(client, reg->reg, reg->val);
423 }
424 #endif
425
426 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
427 {
428 struct i2c_client *client = v4l2_get_subdevdata(sd);
429 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
430 struct ov6650 *priv = to_ov6650(client);
431
432 return soc_camera_set_power(&client->dev, ssdd, priv->clk, on);
433 }
434
435 static int ov6650_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
436 {
437 struct i2c_client *client = v4l2_get_subdevdata(sd);
438 struct ov6650 *priv = to_ov6650(client);
439
440 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
441 a->c = priv->rect;
442
443 return 0;
444 }
445
446 static int ov6650_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
447 {
448 struct i2c_client *client = v4l2_get_subdevdata(sd);
449 struct ov6650 *priv = to_ov6650(client);
450 struct v4l2_rect rect = a->c;
451 int ret;
452
453 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
454 return -EINVAL;
455
456 rect.left = ALIGN(rect.left, 2);
457 rect.width = ALIGN(rect.width, 2);
458 rect.top = ALIGN(rect.top, 2);
459 rect.height = ALIGN(rect.height, 2);
460 soc_camera_limit_side(&rect.left, &rect.width,
461 DEF_HSTRT << 1, 2, W_CIF);
462 soc_camera_limit_side(&rect.top, &rect.height,
463 DEF_VSTRT << 1, 2, H_CIF);
464
465 ret = ov6650_reg_write(client, REG_HSTRT, rect.left >> 1);
466 if (!ret) {
467 priv->rect.left = rect.left;
468 ret = ov6650_reg_write(client, REG_HSTOP,
469 (rect.left + rect.width) >> 1);
470 }
471 if (!ret) {
472 priv->rect.width = rect.width;
473 ret = ov6650_reg_write(client, REG_VSTRT, rect.top >> 1);
474 }
475 if (!ret) {
476 priv->rect.top = rect.top;
477 ret = ov6650_reg_write(client, REG_VSTOP,
478 (rect.top + rect.height) >> 1);
479 }
480 if (!ret)
481 priv->rect.height = rect.height;
482
483 return ret;
484 }
485
486 static int ov6650_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
487 {
488 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
489 return -EINVAL;
490
491 a->bounds.left = DEF_HSTRT << 1;
492 a->bounds.top = DEF_VSTRT << 1;
493 a->bounds.width = W_CIF;
494 a->bounds.height = H_CIF;
495 a->defrect = a->bounds;
496 a->pixelaspect.numerator = 1;
497 a->pixelaspect.denominator = 1;
498
499 return 0;
500 }
501
502 static int ov6650_g_fmt(struct v4l2_subdev *sd,
503 struct v4l2_mbus_framefmt *mf)
504 {
505 struct i2c_client *client = v4l2_get_subdevdata(sd);
506 struct ov6650 *priv = to_ov6650(client);
507
508 mf->width = priv->rect.width >> priv->half_scale;
509 mf->height = priv->rect.height >> priv->half_scale;
510 mf->code = priv->code;
511 mf->colorspace = priv->colorspace;
512 mf->field = V4L2_FIELD_NONE;
513
514 return 0;
515 }
516
517 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
518 {
519 return width > rect->width >> 1 || height > rect->height >> 1;
520 }
521
522 static u8 to_clkrc(struct v4l2_fract *timeperframe,
523 unsigned long pclk_limit, unsigned long pclk_max)
524 {
525 unsigned long pclk;
526
527 if (timeperframe->numerator && timeperframe->denominator)
528 pclk = pclk_max * timeperframe->denominator /
529 (FRAME_RATE_MAX * timeperframe->numerator);
530 else
531 pclk = pclk_max;
532
533 if (pclk_limit && pclk_limit < pclk)
534 pclk = pclk_limit;
535
536 return (pclk_max - 1) / pclk;
537 }
538
539 /* set the format we will capture in */
540 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
541 {
542 struct i2c_client *client = v4l2_get_subdevdata(sd);
543 struct soc_camera_device *icd = v4l2_get_subdev_hostdata(sd);
544 struct soc_camera_sense *sense = icd->sense;
545 struct ov6650 *priv = to_ov6650(client);
546 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
547 struct v4l2_crop a = {
548 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
549 .c = {
550 .left = priv->rect.left + (priv->rect.width >> 1) -
551 (mf->width >> (1 - half_scale)),
552 .top = priv->rect.top + (priv->rect.height >> 1) -
553 (mf->height >> (1 - half_scale)),
554 .width = mf->width << half_scale,
555 .height = mf->height << half_scale,
556 },
557 };
558 enum v4l2_mbus_pixelcode code = mf->code;
559 unsigned long mclk, pclk;
560 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
561 int ret;
562
563 /* select color matrix configuration for given color encoding */
564 switch (code) {
565 case V4L2_MBUS_FMT_Y8_1X8:
566 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
567 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
568 coma_set |= COMA_BW;
569 break;
570 case V4L2_MBUS_FMT_YUYV8_2X8:
571 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
572 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
573 coma_set |= COMA_WORD_SWAP;
574 break;
575 case V4L2_MBUS_FMT_YVYU8_2X8:
576 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
577 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
578 COMA_BYTE_SWAP;
579 break;
580 case V4L2_MBUS_FMT_UYVY8_2X8:
581 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
582 if (half_scale) {
583 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
584 coma_set |= COMA_BYTE_SWAP;
585 } else {
586 coma_mask |= COMA_RGB | COMA_BW;
587 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
588 }
589 break;
590 case V4L2_MBUS_FMT_VYUY8_2X8:
591 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
592 if (half_scale) {
593 coma_mask |= COMA_RGB | COMA_BW;
594 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
595 } else {
596 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
597 coma_set |= COMA_BYTE_SWAP;
598 }
599 break;
600 case V4L2_MBUS_FMT_SBGGR8_1X8:
601 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
602 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
603 coma_set |= COMA_RAW_RGB | COMA_RGB;
604 break;
605 default:
606 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
607 return -EINVAL;
608 }
609 priv->code = code;
610
611 if (code == V4L2_MBUS_FMT_Y8_1X8 ||
612 code == V4L2_MBUS_FMT_SBGGR8_1X8) {
613 coml_mask = COML_ONE_CHANNEL;
614 coml_set = 0;
615 priv->pclk_max = 4000000;
616 } else {
617 coml_mask = 0;
618 coml_set = COML_ONE_CHANNEL;
619 priv->pclk_max = 8000000;
620 }
621
622 if (code == V4L2_MBUS_FMT_SBGGR8_1X8)
623 priv->colorspace = V4L2_COLORSPACE_SRGB;
624 else if (code != 0)
625 priv->colorspace = V4L2_COLORSPACE_JPEG;
626
627 if (half_scale) {
628 dev_dbg(&client->dev, "max resolution: QCIF\n");
629 coma_set |= COMA_QCIF;
630 priv->pclk_max /= 2;
631 } else {
632 dev_dbg(&client->dev, "max resolution: CIF\n");
633 coma_mask |= COMA_QCIF;
634 }
635 priv->half_scale = half_scale;
636
637 if (sense) {
638 if (sense->master_clock == 8000000) {
639 dev_dbg(&client->dev, "8MHz input clock\n");
640 clkrc = CLKRC_6MHz;
641 } else if (sense->master_clock == 12000000) {
642 dev_dbg(&client->dev, "12MHz input clock\n");
643 clkrc = CLKRC_12MHz;
644 } else if (sense->master_clock == 16000000) {
645 dev_dbg(&client->dev, "16MHz input clock\n");
646 clkrc = CLKRC_16MHz;
647 } else if (sense->master_clock == 24000000) {
648 dev_dbg(&client->dev, "24MHz input clock\n");
649 clkrc = CLKRC_24MHz;
650 } else {
651 dev_err(&client->dev,
652 "unsupported input clock, check platform data\n");
653 return -EINVAL;
654 }
655 mclk = sense->master_clock;
656 priv->pclk_limit = sense->pixel_clock_max;
657 } else {
658 clkrc = CLKRC_24MHz;
659 mclk = 24000000;
660 priv->pclk_limit = 0;
661 dev_dbg(&client->dev, "using default 24MHz input clock\n");
662 }
663
664 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
665
666 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
667 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
668 mclk / pclk, 10 * mclk % pclk / pclk);
669
670 ret = ov6650_s_crop(sd, &a);
671 if (!ret)
672 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
673 if (!ret)
674 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
675 if (!ret)
676 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
677
678 if (!ret) {
679 mf->colorspace = priv->colorspace;
680 mf->width = priv->rect.width >> half_scale;
681 mf->height = priv->rect.height >> half_scale;
682 }
683
684 return ret;
685 }
686
687 static int ov6650_try_fmt(struct v4l2_subdev *sd,
688 struct v4l2_mbus_framefmt *mf)
689 {
690 struct i2c_client *client = v4l2_get_subdevdata(sd);
691 struct ov6650 *priv = to_ov6650(client);
692
693 if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
694 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
695 &mf->height, 2, H_CIF, 1, 0);
696
697 mf->field = V4L2_FIELD_NONE;
698
699 switch (mf->code) {
700 case V4L2_MBUS_FMT_Y10_1X10:
701 mf->code = V4L2_MBUS_FMT_Y8_1X8;
702 case V4L2_MBUS_FMT_Y8_1X8:
703 case V4L2_MBUS_FMT_YVYU8_2X8:
704 case V4L2_MBUS_FMT_YUYV8_2X8:
705 case V4L2_MBUS_FMT_VYUY8_2X8:
706 case V4L2_MBUS_FMT_UYVY8_2X8:
707 mf->colorspace = V4L2_COLORSPACE_JPEG;
708 break;
709 default:
710 mf->code = V4L2_MBUS_FMT_SBGGR8_1X8;
711 case V4L2_MBUS_FMT_SBGGR8_1X8:
712 mf->colorspace = V4L2_COLORSPACE_SRGB;
713 break;
714 }
715
716 return 0;
717 }
718
719 static int ov6650_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
720 enum v4l2_mbus_pixelcode *code)
721 {
722 if (index >= ARRAY_SIZE(ov6650_codes))
723 return -EINVAL;
724
725 *code = ov6650_codes[index];
726 return 0;
727 }
728
729 static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
730 {
731 struct i2c_client *client = v4l2_get_subdevdata(sd);
732 struct ov6650 *priv = to_ov6650(client);
733 struct v4l2_captureparm *cp = &parms->parm.capture;
734
735 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
736 return -EINVAL;
737
738 memset(cp, 0, sizeof(*cp));
739 cp->capability = V4L2_CAP_TIMEPERFRAME;
740 cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
741 priv->pclk_limit, priv->pclk_max));
742 cp->timeperframe.denominator = FRAME_RATE_MAX;
743
744 dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
745 cp->timeperframe.numerator, cp->timeperframe.denominator);
746
747 return 0;
748 }
749
750 static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
751 {
752 struct i2c_client *client = v4l2_get_subdevdata(sd);
753 struct ov6650 *priv = to_ov6650(client);
754 struct v4l2_captureparm *cp = &parms->parm.capture;
755 struct v4l2_fract *tpf = &cp->timeperframe;
756 int div, ret;
757 u8 clkrc;
758
759 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
760 return -EINVAL;
761
762 if (cp->extendedmode != 0)
763 return -EINVAL;
764
765 if (tpf->numerator == 0 || tpf->denominator == 0)
766 div = 1; /* Reset to full rate */
767 else
768 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
769
770 if (div == 0)
771 div = 1;
772 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
773 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
774
775 /*
776 * Keep result to be used as tpf limit
777 * for subseqent clock divider calculations
778 */
779 priv->tpf.numerator = div;
780 priv->tpf.denominator = FRAME_RATE_MAX;
781
782 clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
783
784 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
785 if (!ret) {
786 tpf->numerator = GET_CLKRC_DIV(clkrc);
787 tpf->denominator = FRAME_RATE_MAX;
788 }
789
790 return ret;
791 }
792
793 /* Soft reset the camera. This has nothing to do with the RESET pin! */
794 static int ov6650_reset(struct i2c_client *client)
795 {
796 int ret;
797
798 dev_dbg(&client->dev, "reset\n");
799
800 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
801 if (ret)
802 dev_err(&client->dev,
803 "An error occurred while entering soft reset!\n");
804
805 return ret;
806 }
807
808 /* program default register values */
809 static int ov6650_prog_dflt(struct i2c_client *client)
810 {
811 int ret;
812
813 dev_dbg(&client->dev, "initializing\n");
814
815 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
816 if (!ret)
817 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
818
819 return ret;
820 }
821
822 static int ov6650_video_probe(struct i2c_client *client)
823 {
824 struct ov6650 *priv = to_ov6650(client);
825 u8 pidh, pidl, midh, midl;
826 int ret;
827
828 ret = ov6650_s_power(&priv->subdev, 1);
829 if (ret < 0)
830 return ret;
831
832 /*
833 * check and show product ID and manufacturer ID
834 */
835 ret = ov6650_reg_read(client, REG_PIDH, &pidh);
836 if (!ret)
837 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
838 if (!ret)
839 ret = ov6650_reg_read(client, REG_MIDH, &midh);
840 if (!ret)
841 ret = ov6650_reg_read(client, REG_MIDL, &midl);
842
843 if (ret)
844 goto done;
845
846 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
847 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
848 pidh, pidl);
849 ret = -ENODEV;
850 goto done;
851 }
852
853 dev_info(&client->dev,
854 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
855 pidh, pidl, midh, midl);
856
857 ret = ov6650_reset(client);
858 if (!ret)
859 ret = ov6650_prog_dflt(client);
860 if (!ret)
861 ret = v4l2_ctrl_handler_setup(&priv->hdl);
862
863 done:
864 ov6650_s_power(&priv->subdev, 0);
865 return ret;
866 }
867
868 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
869 .g_volatile_ctrl = ov6550_g_volatile_ctrl,
870 .s_ctrl = ov6550_s_ctrl,
871 };
872
873 static struct v4l2_subdev_core_ops ov6650_core_ops = {
874 #ifdef CONFIG_VIDEO_ADV_DEBUG
875 .g_register = ov6650_get_register,
876 .s_register = ov6650_set_register,
877 #endif
878 .s_power = ov6650_s_power,
879 };
880
881 /* Request bus settings on camera side */
882 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
883 struct v4l2_mbus_config *cfg)
884 {
885 struct i2c_client *client = v4l2_get_subdevdata(sd);
886 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
887
888 cfg->flags = V4L2_MBUS_MASTER |
889 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
890 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
891 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
892 V4L2_MBUS_DATA_ACTIVE_HIGH;
893 cfg->type = V4L2_MBUS_PARALLEL;
894 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
895
896 return 0;
897 }
898
899 /* Alter bus settings on camera side */
900 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
901 const struct v4l2_mbus_config *cfg)
902 {
903 struct i2c_client *client = v4l2_get_subdevdata(sd);
904 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
905 unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg);
906 int ret;
907
908 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
909 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
910 else
911 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
912 if (ret)
913 return ret;
914
915 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
916 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
917 else
918 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
919 if (ret)
920 return ret;
921
922 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
923 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
924 else
925 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
926
927 return ret;
928 }
929
930 static struct v4l2_subdev_video_ops ov6650_video_ops = {
931 .s_stream = ov6650_s_stream,
932 .g_mbus_fmt = ov6650_g_fmt,
933 .s_mbus_fmt = ov6650_s_fmt,
934 .try_mbus_fmt = ov6650_try_fmt,
935 .enum_mbus_fmt = ov6650_enum_fmt,
936 .cropcap = ov6650_cropcap,
937 .g_crop = ov6650_g_crop,
938 .s_crop = ov6650_s_crop,
939 .g_parm = ov6650_g_parm,
940 .s_parm = ov6650_s_parm,
941 .g_mbus_config = ov6650_g_mbus_config,
942 .s_mbus_config = ov6650_s_mbus_config,
943 };
944
945 static struct v4l2_subdev_ops ov6650_subdev_ops = {
946 .core = &ov6650_core_ops,
947 .video = &ov6650_video_ops,
948 };
949
950 /*
951 * i2c_driver function
952 */
953 static int ov6650_probe(struct i2c_client *client,
954 const struct i2c_device_id *did)
955 {
956 struct ov6650 *priv;
957 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
958 int ret;
959
960 if (!ssdd) {
961 dev_err(&client->dev, "Missing platform_data for driver\n");
962 return -EINVAL;
963 }
964
965 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
966 if (!priv) {
967 dev_err(&client->dev,
968 "Failed to allocate memory for private data!\n");
969 return -ENOMEM;
970 }
971
972 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
973 v4l2_ctrl_handler_init(&priv->hdl, 13);
974 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
975 V4L2_CID_VFLIP, 0, 1, 1, 0);
976 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
977 V4L2_CID_HFLIP, 0, 1, 1, 0);
978 priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
979 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
980 priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
981 V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
982 priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
983 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
984 priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
985 V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
986 priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
987 V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
988 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
989 V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
990 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
991 V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
992 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
993 V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
994 priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
995 &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
996 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
997 priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
998 V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
999 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1000 V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1001
1002 priv->subdev.ctrl_handler = &priv->hdl;
1003 if (priv->hdl.error)
1004 return priv->hdl.error;
1005
1006 v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1007 v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1008 v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1009 V4L2_EXPOSURE_MANUAL, true);
1010
1011 priv->rect.left = DEF_HSTRT << 1;
1012 priv->rect.top = DEF_VSTRT << 1;
1013 priv->rect.width = W_CIF;
1014 priv->rect.height = H_CIF;
1015 priv->half_scale = false;
1016 priv->code = V4L2_MBUS_FMT_YUYV8_2X8;
1017 priv->colorspace = V4L2_COLORSPACE_JPEG;
1018
1019 priv->clk = v4l2_clk_get(&client->dev, "mclk");
1020 if (IS_ERR(priv->clk)) {
1021 ret = PTR_ERR(priv->clk);
1022 goto eclkget;
1023 }
1024
1025 ret = ov6650_video_probe(client);
1026 if (ret) {
1027 v4l2_clk_put(priv->clk);
1028 eclkget:
1029 v4l2_ctrl_handler_free(&priv->hdl);
1030 }
1031
1032 return ret;
1033 }
1034
1035 static int ov6650_remove(struct i2c_client *client)
1036 {
1037 struct ov6650 *priv = to_ov6650(client);
1038
1039 v4l2_clk_put(priv->clk);
1040 v4l2_device_unregister_subdev(&priv->subdev);
1041 v4l2_ctrl_handler_free(&priv->hdl);
1042 return 0;
1043 }
1044
1045 static const struct i2c_device_id ov6650_id[] = {
1046 { "ov6650", 0 },
1047 { }
1048 };
1049 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1050
1051 static struct i2c_driver ov6650_i2c_driver = {
1052 .driver = {
1053 .name = "ov6650",
1054 },
1055 .probe = ov6650_probe,
1056 .remove = ov6650_remove,
1057 .id_table = ov6650_id,
1058 };
1059
1060 module_i2c_driver(ov6650_i2c_driver);
1061
1062 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1063 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1064 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support