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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / i2c / soc_camera / ov772x.c
blob7f2b3c8926afbfade0fca5c58bea1e9356dc9d3b
1 /*
2 * ov772x Camera Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov7670 and soc_camera_platform driver,
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * Copyright (C) 2008 Magnus Damm
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/i2c.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/v4l2-mediabus.h>
25 #include <linux/videodev2.h>
26
27 #include <media/ov772x.h>
28 #include <media/soc_camera.h>
29 #include <media/v4l2-clk.h>
30 #include <media/v4l2-ctrls.h>
31 #include <media/v4l2-subdev.h>
32
33 /*
34 * register offset
35 */
36 #define GAIN 0x00 /* AGC - Gain control gain setting */
37 #define BLUE 0x01 /* AWB - Blue channel gain setting */
38 #define RED 0x02 /* AWB - Red channel gain setting */
39 #define GREEN 0x03 /* AWB - Green channel gain setting */
40 #define COM1 0x04 /* Common control 1 */
41 #define BAVG 0x05 /* U/B Average Level */
42 #define GAVG 0x06 /* Y/Gb Average Level */
43 #define RAVG 0x07 /* V/R Average Level */
44 #define AECH 0x08 /* Exposure Value - AEC MSBs */
45 #define COM2 0x09 /* Common control 2 */
46 #define PID 0x0A /* Product ID Number MSB */
47 #define VER 0x0B /* Product ID Number LSB */
48 #define COM3 0x0C /* Common control 3 */
49 #define COM4 0x0D /* Common control 4 */
50 #define COM5 0x0E /* Common control 5 */
51 #define COM6 0x0F /* Common control 6 */
52 #define AEC 0x10 /* Exposure Value */
53 #define CLKRC 0x11 /* Internal clock */
54 #define COM7 0x12 /* Common control 7 */
55 #define COM8 0x13 /* Common control 8 */
56 #define COM9 0x14 /* Common control 9 */
57 #define COM10 0x15 /* Common control 10 */
58 #define REG16 0x16 /* Register 16 */
59 #define HSTART 0x17 /* Horizontal sensor size */
60 #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
61 #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
62 #define VSIZE 0x1A /* Vertical sensor size */
63 #define PSHFT 0x1B /* Data format - pixel delay select */
64 #define MIDH 0x1C /* Manufacturer ID byte - high */
65 #define MIDL 0x1D /* Manufacturer ID byte - low */
66 #define LAEC 0x1F /* Fine AEC value */
67 #define COM11 0x20 /* Common control 11 */
68 #define BDBASE 0x22 /* Banding filter Minimum AEC value */
69 #define DBSTEP 0x23 /* Banding filter Maximum Setp */
70 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
71 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
72 #define VPT 0x26 /* AGC/AEC Fast mode operating region */
73 #define REG28 0x28 /* Register 28 */
74 #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
75 #define EXHCH 0x2A /* Dummy pixel insert MSB */
76 #define EXHCL 0x2B /* Dummy pixel insert LSB */
77 #define VOUTSIZE 0x2C /* Vertical data output size MSBs */
78 #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
79 #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
80 #define YAVE 0x2F /* Y/G Channel Average value */
81 #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
82 #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
83 #define HREF 0x32 /* Image start and size control */
84 #define DM_LNL 0x33 /* Dummy line low 8 bits */
85 #define DM_LNH 0x34 /* Dummy line high 8 bits */
86 #define ADOFF_B 0x35 /* AD offset compensation value for B channel */
87 #define ADOFF_R 0x36 /* AD offset compensation value for R channel */
88 #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
89 #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
90 #define OFF_B 0x39 /* Analog process B channel offset value */
91 #define OFF_R 0x3A /* Analog process R channel offset value */
92 #define OFF_GB 0x3B /* Analog process Gb channel offset value */
93 #define OFF_GR 0x3C /* Analog process Gr channel offset value */
94 #define COM12 0x3D /* Common control 12 */
95 #define COM13 0x3E /* Common control 13 */
96 #define COM14 0x3F /* Common control 14 */
97 #define COM15 0x40 /* Common control 15*/
98 #define COM16 0x41 /* Common control 16 */
99 #define TGT_B 0x42 /* BLC blue channel target value */
100 #define TGT_R 0x43 /* BLC red channel target value */
101 #define TGT_GB 0x44 /* BLC Gb channel target value */
102 #define TGT_GR 0x45 /* BLC Gr channel target value */
103 /* for ov7720 */
104 #define LCC0 0x46 /* Lens correction control 0 */
105 #define LCC1 0x47 /* Lens correction option 1 - X coordinate */
106 #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
107 #define LCC3 0x49 /* Lens correction option 3 */
108 #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
109 #define LCC5 0x4B /* Lens correction option 5 */
110 #define LCC6 0x4C /* Lens correction option 6 */
111 /* for ov7725 */
112 #define LC_CTR 0x46 /* Lens correction control */
113 #define LC_XC 0x47 /* X coordinate of lens correction center relative */
114 #define LC_YC 0x48 /* Y coordinate of lens correction center relative */
115 #define LC_COEF 0x49 /* Lens correction coefficient */
116 #define LC_RADI 0x4A /* Lens correction radius */
117 #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */
118 #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */
119
120 #define FIXGAIN 0x4D /* Analog fix gain amplifer */
121 #define AREF0 0x4E /* Sensor reference control */
122 #define AREF1 0x4F /* Sensor reference current control */
123 #define AREF2 0x50 /* Analog reference control */
124 #define AREF3 0x51 /* ADC reference control */
125 #define AREF4 0x52 /* ADC reference control */
126 #define AREF5 0x53 /* ADC reference control */
127 #define AREF6 0x54 /* Analog reference control */
128 #define AREF7 0x55 /* Analog reference control */
129 #define UFIX 0x60 /* U channel fixed value output */
130 #define VFIX 0x61 /* V channel fixed value output */
131 #define AWBB_BLK 0x62 /* AWB option for advanced AWB */
132 #define AWB_CTRL0 0x63 /* AWB control byte 0 */
133 #define DSP_CTRL1 0x64 /* DSP control byte 1 */
134 #define DSP_CTRL2 0x65 /* DSP control byte 2 */
135 #define DSP_CTRL3 0x66 /* DSP control byte 3 */
136 #define DSP_CTRL4 0x67 /* DSP control byte 4 */
137 #define AWB_BIAS 0x68 /* AWB BLC level clip */
138 #define AWB_CTRL1 0x69 /* AWB control 1 */
139 #define AWB_CTRL2 0x6A /* AWB control 2 */
140 #define AWB_CTRL3 0x6B /* AWB control 3 */
141 #define AWB_CTRL4 0x6C /* AWB control 4 */
142 #define AWB_CTRL5 0x6D /* AWB control 5 */
143 #define AWB_CTRL6 0x6E /* AWB control 6 */
144 #define AWB_CTRL7 0x6F /* AWB control 7 */
145 #define AWB_CTRL8 0x70 /* AWB control 8 */
146 #define AWB_CTRL9 0x71 /* AWB control 9 */
147 #define AWB_CTRL10 0x72 /* AWB control 10 */
148 #define AWB_CTRL11 0x73 /* AWB control 11 */
149 #define AWB_CTRL12 0x74 /* AWB control 12 */
150 #define AWB_CTRL13 0x75 /* AWB control 13 */
151 #define AWB_CTRL14 0x76 /* AWB control 14 */
152 #define AWB_CTRL15 0x77 /* AWB control 15 */
153 #define AWB_CTRL16 0x78 /* AWB control 16 */
154 #define AWB_CTRL17 0x79 /* AWB control 17 */
155 #define AWB_CTRL18 0x7A /* AWB control 18 */
156 #define AWB_CTRL19 0x7B /* AWB control 19 */
157 #define AWB_CTRL20 0x7C /* AWB control 20 */
158 #define AWB_CTRL21 0x7D /* AWB control 21 */
159 #define GAM1 0x7E /* Gamma Curve 1st segment input end point */
160 #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
161 #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
162 #define GAM4 0x81 /* Gamma Curve 4th segment input end point */
163 #define GAM5 0x82 /* Gamma Curve 5th segment input end point */
164 #define GAM6 0x83 /* Gamma Curve 6th segment input end point */
165 #define GAM7 0x84 /* Gamma Curve 7th segment input end point */
166 #define GAM8 0x85 /* Gamma Curve 8th segment input end point */
167 #define GAM9 0x86 /* Gamma Curve 9th segment input end point */
168 #define GAM10 0x87 /* Gamma Curve 10th segment input end point */
169 #define GAM11 0x88 /* Gamma Curve 11th segment input end point */
170 #define GAM12 0x89 /* Gamma Curve 12th segment input end point */
171 #define GAM13 0x8A /* Gamma Curve 13th segment input end point */
172 #define GAM14 0x8B /* Gamma Curve 14th segment input end point */
173 #define GAM15 0x8C /* Gamma Curve 15th segment input end point */
174 #define SLOP 0x8D /* Gamma curve highest segment slope */
175 #define DNSTH 0x8E /* De-noise threshold */
176 #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
177 #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
178 #define DNSOFF 0x91 /* Auto De-noise threshold control */
179 #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */
180 #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */
181 #define MTX1 0x94 /* Matrix coefficient 1 */
182 #define MTX2 0x95 /* Matrix coefficient 2 */
183 #define MTX3 0x96 /* Matrix coefficient 3 */
184 #define MTX4 0x97 /* Matrix coefficient 4 */
185 #define MTX5 0x98 /* Matrix coefficient 5 */
186 #define MTX6 0x99 /* Matrix coefficient 6 */
187 #define MTX_CTRL 0x9A /* Matrix control */
188 #define BRIGHT 0x9B /* Brightness control */
189 #define CNTRST 0x9C /* Contrast contrast */
190 #define CNTRST_CTRL 0x9D /* Contrast contrast center */
191 #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
192 #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
193 #define SCAL0 0xA0 /* Scaling control 0 */
194 #define SCAL1 0xA1 /* Scaling control 1 */
195 #define SCAL2 0xA2 /* Scaling control 2 */
196 #define FIFODLYM 0xA3 /* FIFO manual mode delay control */
197 #define FIFODLYA 0xA4 /* FIFO auto mode delay control */
198 #define SDE 0xA6 /* Special digital effect control */
199 #define USAT 0xA7 /* U component saturation control */
200 #define VSAT 0xA8 /* V component saturation control */
201 /* for ov7720 */
202 #define HUE0 0xA9 /* Hue control 0 */
203 #define HUE1 0xAA /* Hue control 1 */
204 /* for ov7725 */
205 #define HUECOS 0xA9 /* Cosine value */
206 #define HUESIN 0xAA /* Sine value */
207
208 #define SIGN 0xAB /* Sign bit for Hue and contrast */
209 #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
210
211 /*
212 * register detail
213 */
214
215 /* COM2 */
216 #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
217 /* Output drive capability */
218 #define OCAP_1x 0x00 /* 1x */
219 #define OCAP_2x 0x01 /* 2x */
220 #define OCAP_3x 0x02 /* 3x */
221 #define OCAP_4x 0x03 /* 4x */
222
223 /* COM3 */
224 #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
225 #define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
226
227 #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
228 #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
229 #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
230 #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
231 #define SWAP_ML 0x08 /* Swap output MSB/LSB */
232 /* Tri-state option for output clock */
233 #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
234 /* 1: No tri-state at this period */
235 /* Tri-state option for output data */
236 #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
237 /* 1: No tri-state at this period */
238 #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
239
240 /* COM4 */
241 /* PLL frequency control */
242 #define PLL_BYPASS 0x00 /* 00: Bypass PLL */
243 #define PLL_4x 0x40 /* 01: PLL 4x */
244 #define PLL_6x 0x80 /* 10: PLL 6x */
245 #define PLL_8x 0xc0 /* 11: PLL 8x */
246 /* AEC evaluate window */
247 #define AEC_FULL 0x00 /* 00: Full window */
248 #define AEC_1p2 0x10 /* 01: 1/2 window */
249 #define AEC_1p4 0x20 /* 10: 1/4 window */
250 #define AEC_2p3 0x30 /* 11: Low 2/3 window */
251
252 /* COM5 */
253 #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
254 #define AFR_SPPED 0x40 /* Auto frame rate control speed selection */
255 /* Auto frame rate max rate control */
256 #define AFR_NO_RATE 0x00 /* No reduction of frame rate */
257 #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
258 #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
259 #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
260 /* Auto frame rate active point control */
261 #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
262 #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
263 #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
264 #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
265 /* AEC max step control */
266 #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
267 /* 1 : No limit to AEC increase step */
268
269 /* COM7 */
270 /* SCCB Register Reset */
271 #define SCCB_RESET 0x80 /* 0 : No change */
272 /* 1 : Resets all registers to default */
273 /* Resolution selection */
274 #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
275 #define SLCT_VGA 0x00 /* 0 : VGA */
276 #define SLCT_QVGA 0x40 /* 1 : QVGA */
277 #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
278 #define SENSOR_RAW 0x10 /* Sensor RAW */
279 /* RGB output format control */
280 #define FMT_MASK 0x0c /* Mask of color format */
281 #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
282 #define FMT_RGB565 0x04 /* 01 : RGB 565 */
283 #define FMT_RGB555 0x08 /* 10 : RGB 555 */
284 #define FMT_RGB444 0x0c /* 11 : RGB 444 */
285 /* Output format control */
286 #define OFMT_MASK 0x03 /* Mask of output format */
287 #define OFMT_YUV 0x00 /* 00 : YUV */
288 #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
289 #define OFMT_RGB 0x02 /* 10 : RGB */
290 #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
291
292 /* COM8 */
293 #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
294 /* AEC Setp size limit */
295 #define UNLMT_STEP 0x40 /* 0 : Step size is limited */
296 /* 1 : Unlimited step size */
297 #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
298 #define AEC_BND 0x10 /* Enable AEC below banding value */
299 #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
300 #define AGC_ON 0x04 /* AGC Enable */
301 #define AWB_ON 0x02 /* AWB Enable */
302 #define AEC_ON 0x01 /* AEC Enable */
303
304 /* COM9 */
305 #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
306 /* Automatic gain ceiling - maximum AGC value */
307 #define GAIN_2x 0x00 /* 000 : 2x */
308 #define GAIN_4x 0x10 /* 001 : 4x */
309 #define GAIN_8x 0x20 /* 010 : 8x */
310 #define GAIN_16x 0x30 /* 011 : 16x */
311 #define GAIN_32x 0x40 /* 100 : 32x */
312 #define GAIN_64x 0x50 /* 101 : 64x */
313 #define GAIN_128x 0x60 /* 110 : 128x */
314 #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
315 #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
316
317 /* COM11 */
318 #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
319 #define SGLF_TRIG 0x01 /* Single frame transfer trigger */
320
321 /* HREF */
322 #define HREF_VSTART_SHIFT 6 /* VSTART LSB */
323 #define HREF_HSTART_SHIFT 4 /* HSTART 2 LSBs */
324 #define HREF_VSIZE_SHIFT 2 /* VSIZE LSB */
325 #define HREF_HSIZE_SHIFT 0 /* HSIZE 2 LSBs */
326
327 /* EXHCH */
328 #define EXHCH_VSIZE_SHIFT 2 /* VOUTSIZE LSB */
329 #define EXHCH_HSIZE_SHIFT 0 /* HOUTSIZE 2 LSBs */
330
331 /* DSP_CTRL1 */
332 #define FIFO_ON 0x80 /* FIFO enable/disable selection */
333 #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
334 #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
335 #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
336 #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
337 #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
338 #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
339 #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
340
341 /* DSP_CTRL3 */
342 #define UV_MASK 0x80 /* UV output sequence option */
343 #define UV_ON 0x80 /* ON */
344 #define UV_OFF 0x00 /* OFF */
345 #define CBAR_MASK 0x20 /* DSP Color bar mask */
346 #define CBAR_ON 0x20 /* ON */
347 #define CBAR_OFF 0x00 /* OFF */
348
349 /* DSP_CTRL4 */
350 #define DSP_OFMT_YUV 0x00
351 #define DSP_OFMT_RGB 0x00
352 #define DSP_OFMT_RAW8 0x02
353 #define DSP_OFMT_RAW10 0x03
354
355 /* DSPAUTO (DSP Auto Function ON/OFF Control) */
356 #define AWB_ACTRL 0x80 /* AWB auto threshold control */
357 #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
358 #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
359 #define UV_ACTRL 0x10 /* UV adjust auto slope control */
360 #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
361 #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
362
363 #define VGA_WIDTH 640
364 #define VGA_HEIGHT 480
365 #define QVGA_WIDTH 320
366 #define QVGA_HEIGHT 240
367 #define OV772X_MAX_WIDTH VGA_WIDTH
368 #define OV772X_MAX_HEIGHT VGA_HEIGHT
369
370 /*
371 * ID
372 */
373 #define OV7720 0x7720
374 #define OV7725 0x7721
375 #define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
376
377 /*
378 * struct
379 */
380
381 struct ov772x_color_format {
382 enum v4l2_mbus_pixelcode code;
383 enum v4l2_colorspace colorspace;
384 u8 dsp3;
385 u8 dsp4;
386 u8 com3;
387 u8 com7;
388 };
389
390 struct ov772x_win_size {
391 char *name;
392 unsigned char com7_bit;
393 struct v4l2_rect rect;
394 };
395
396 struct ov772x_priv {
397 struct v4l2_subdev subdev;
398 struct v4l2_ctrl_handler hdl;
399 struct v4l2_clk *clk;
400 struct ov772x_camera_info *info;
401 const struct ov772x_color_format *cfmt;
402 const struct ov772x_win_size *win;
403 unsigned short flag_vflip:1;
404 unsigned short flag_hflip:1;
405 /* band_filter = COM8[5] ? 256 - BDBASE : 0 */
406 unsigned short band_filter;
407 };
408
409 /*
410 * supported color format list
411 */
412 static const struct ov772x_color_format ov772x_cfmts[] = {
413 {
414 .code = V4L2_MBUS_FMT_YUYV8_2X8,
415 .colorspace = V4L2_COLORSPACE_JPEG,
416 .dsp3 = 0x0,
417 .dsp4 = DSP_OFMT_YUV,
418 .com3 = SWAP_YUV,
419 .com7 = OFMT_YUV,
420 },
421 {
422 .code = V4L2_MBUS_FMT_YVYU8_2X8,
423 .colorspace = V4L2_COLORSPACE_JPEG,
424 .dsp3 = UV_ON,
425 .dsp4 = DSP_OFMT_YUV,
426 .com3 = SWAP_YUV,
427 .com7 = OFMT_YUV,
428 },
429 {
430 .code = V4L2_MBUS_FMT_UYVY8_2X8,
431 .colorspace = V4L2_COLORSPACE_JPEG,
432 .dsp3 = 0x0,
433 .dsp4 = DSP_OFMT_YUV,
434 .com3 = 0x0,
435 .com7 = OFMT_YUV,
436 },
437 {
438 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
439 .colorspace = V4L2_COLORSPACE_SRGB,
440 .dsp3 = 0x0,
441 .dsp4 = DSP_OFMT_YUV,
442 .com3 = SWAP_RGB,
443 .com7 = FMT_RGB555 | OFMT_RGB,
444 },
445 {
446 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
447 .colorspace = V4L2_COLORSPACE_SRGB,
448 .dsp3 = 0x0,
449 .dsp4 = DSP_OFMT_YUV,
450 .com3 = 0x0,
451 .com7 = FMT_RGB555 | OFMT_RGB,
452 },
453 {
454 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
455 .colorspace = V4L2_COLORSPACE_SRGB,
456 .dsp3 = 0x0,
457 .dsp4 = DSP_OFMT_YUV,
458 .com3 = SWAP_RGB,
459 .com7 = FMT_RGB565 | OFMT_RGB,
460 },
461 {
462 .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
463 .colorspace = V4L2_COLORSPACE_SRGB,
464 .dsp3 = 0x0,
465 .dsp4 = DSP_OFMT_YUV,
466 .com3 = 0x0,
467 .com7 = FMT_RGB565 | OFMT_RGB,
468 },
469 {
470 /* Setting DSP4 to DSP_OFMT_RAW8 still gives 10-bit output,
471 * regardless of the COM7 value. We can thus only support 10-bit
472 * Bayer until someone figures it out.
473 */
474 .code = V4L2_MBUS_FMT_SBGGR10_1X10,
475 .colorspace = V4L2_COLORSPACE_SRGB,
476 .dsp3 = 0x0,
477 .dsp4 = DSP_OFMT_RAW10,
478 .com3 = 0x0,
479 .com7 = SENSOR_RAW | OFMT_BRAW,
480 },
481 };
482
483
484 /*
485 * window size list
486 */
487
488 static const struct ov772x_win_size ov772x_win_sizes[] = {
489 {
490 .name = "VGA",
491 .com7_bit = SLCT_VGA,
492 .rect = {
493 .left = 140,
494 .top = 14,
495 .width = VGA_WIDTH,
496 .height = VGA_HEIGHT,
497 },
498 }, {
499 .name = "QVGA",
500 .com7_bit = SLCT_QVGA,
501 .rect = {
502 .left = 252,
503 .top = 6,
504 .width = QVGA_WIDTH,
505 .height = QVGA_HEIGHT,
506 },
507 },
508 };
509
510 /*
511 * general function
512 */
513
514 static struct ov772x_priv *to_ov772x(struct v4l2_subdev *sd)
515 {
516 return container_of(sd, struct ov772x_priv, subdev);
517 }
518
519 static inline int ov772x_read(struct i2c_client *client, u8 addr)
520 {
521 return i2c_smbus_read_byte_data(client, addr);
522 }
523
524 static inline int ov772x_write(struct i2c_client *client, u8 addr, u8 value)
525 {
526 return i2c_smbus_write_byte_data(client, addr, value);
527 }
528
529 static int ov772x_mask_set(struct i2c_client *client, u8 command, u8 mask,
530 u8 set)
531 {
532 s32 val = ov772x_read(client, command);
533 if (val < 0)
534 return val;
535
536 val &= ~mask;
537 val |= set & mask;
538
539 return ov772x_write(client, command, val);
540 }
541
542 static int ov772x_reset(struct i2c_client *client)
543 {
544 int ret;
545
546 ret = ov772x_write(client, COM7, SCCB_RESET);
547 if (ret < 0)
548 return ret;
549
550 msleep(1);
551
552 return ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
553 }
554
555 /*
556 * soc_camera_ops function
557 */
558
559 static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
560 {
561 struct i2c_client *client = v4l2_get_subdevdata(sd);
562 struct ov772x_priv *priv = to_ov772x(sd);
563
564 if (!enable) {
565 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
566 return 0;
567 }
568
569 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0);
570
571 dev_dbg(&client->dev, "format %d, win %s\n",
572 priv->cfmt->code, priv->win->name);
573
574 return 0;
575 }
576
577 static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl)
578 {
579 struct ov772x_priv *priv = container_of(ctrl->handler,
580 struct ov772x_priv, hdl);
581 struct v4l2_subdev *sd = &priv->subdev;
582 struct i2c_client *client = v4l2_get_subdevdata(sd);
583 int ret = 0;
584 u8 val;
585
586 switch (ctrl->id) {
587 case V4L2_CID_VFLIP:
588 val = ctrl->val ? VFLIP_IMG : 0x00;
589 priv->flag_vflip = ctrl->val;
590 if (priv->info->flags & OV772X_FLAG_VFLIP)
591 val ^= VFLIP_IMG;
592 return ov772x_mask_set(client, COM3, VFLIP_IMG, val);
593 case V4L2_CID_HFLIP:
594 val = ctrl->val ? HFLIP_IMG : 0x00;
595 priv->flag_hflip = ctrl->val;
596 if (priv->info->flags & OV772X_FLAG_HFLIP)
597 val ^= HFLIP_IMG;
598 return ov772x_mask_set(client, COM3, HFLIP_IMG, val);
599 case V4L2_CID_BAND_STOP_FILTER:
600 if (!ctrl->val) {
601 /* Switch the filter off, it is on now */
602 ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff);
603 if (!ret)
604 ret = ov772x_mask_set(client, COM8,
605 BNDF_ON_OFF, 0);
606 } else {
607 /* Switch the filter on, set AEC low limit */
608 val = 256 - ctrl->val;
609 ret = ov772x_mask_set(client, COM8,
610 BNDF_ON_OFF, BNDF_ON_OFF);
611 if (!ret)
612 ret = ov772x_mask_set(client, BDBASE,
613 0xff, val);
614 }
615 if (!ret)
616 priv->band_filter = ctrl->val;
617 return ret;
618 }
619
620 return -EINVAL;
621 }
622
623 #ifdef CONFIG_VIDEO_ADV_DEBUG
624 static int ov772x_g_register(struct v4l2_subdev *sd,
625 struct v4l2_dbg_register *reg)
626 {
627 struct i2c_client *client = v4l2_get_subdevdata(sd);
628 int ret;
629
630 reg->size = 1;
631 if (reg->reg > 0xff)
632 return -EINVAL;
633
634 ret = ov772x_read(client, reg->reg);
635 if (ret < 0)
636 return ret;
637
638 reg->val = (__u64)ret;
639
640 return 0;
641 }
642
643 static int ov772x_s_register(struct v4l2_subdev *sd,
644 const struct v4l2_dbg_register *reg)
645 {
646 struct i2c_client *client = v4l2_get_subdevdata(sd);
647
648 if (reg->reg > 0xff ||
649 reg->val > 0xff)
650 return -EINVAL;
651
652 return ov772x_write(client, reg->reg, reg->val);
653 }
654 #endif
655
656 static int ov772x_s_power(struct v4l2_subdev *sd, int on)
657 {
658 struct i2c_client *client = v4l2_get_subdevdata(sd);
659 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
660 struct ov772x_priv *priv = to_ov772x(sd);
661
662 return soc_camera_set_power(&client->dev, ssdd, priv->clk, on);
663 }
664
665 static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
666 {
667 const struct ov772x_win_size *win = &ov772x_win_sizes[0];
668 u32 best_diff = UINT_MAX;
669 unsigned int i;
670
671 for (i = 0; i < ARRAY_SIZE(ov772x_win_sizes); ++i) {
672 u32 diff = abs(width - ov772x_win_sizes[i].rect.width)
673 + abs(height - ov772x_win_sizes[i].rect.height);
674 if (diff < best_diff) {
675 best_diff = diff;
676 win = &ov772x_win_sizes[i];
677 }
678 }
679
680 return win;
681 }
682
683 static void ov772x_select_params(const struct v4l2_mbus_framefmt *mf,
684 const struct ov772x_color_format **cfmt,
685 const struct ov772x_win_size **win)
686 {
687 unsigned int i;
688
689 /* Select a format. */
690 *cfmt = &ov772x_cfmts[0];
691
692 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
693 if (mf->code == ov772x_cfmts[i].code) {
694 *cfmt = &ov772x_cfmts[i];
695 break;
696 }
697 }
698
699 /* Select a window size. */
700 *win = ov772x_select_win(mf->width, mf->height);
701 }
702
703 static int ov772x_set_params(struct ov772x_priv *priv,
704 const struct ov772x_color_format *cfmt,
705 const struct ov772x_win_size *win)
706 {
707 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
708 int ret;
709 u8 val;
710
711 /*
712 * reset hardware
713 */
714 ov772x_reset(client);
715
716 /*
717 * Edge Ctrl
718 */
719 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
720
721 /*
722 * Manual Edge Control Mode
723 *
724 * Edge auto strength bit is set by default.
725 * Remove it when manual mode.
726 */
727
728 ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
729 if (ret < 0)
730 goto ov772x_set_fmt_error;
731
732 ret = ov772x_mask_set(client,
733 EDGE_TRSHLD, OV772X_EDGE_THRESHOLD_MASK,
734 priv->info->edgectrl.threshold);
735 if (ret < 0)
736 goto ov772x_set_fmt_error;
737
738 ret = ov772x_mask_set(client,
739 EDGE_STRNGT, OV772X_EDGE_STRENGTH_MASK,
740 priv->info->edgectrl.strength);
741 if (ret < 0)
742 goto ov772x_set_fmt_error;
743
744 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
745 /*
746 * Auto Edge Control Mode
747 *
748 * set upper and lower limit
749 */
750 ret = ov772x_mask_set(client,
751 EDGE_UPPER, OV772X_EDGE_UPPER_MASK,
752 priv->info->edgectrl.upper);
753 if (ret < 0)
754 goto ov772x_set_fmt_error;
755
756 ret = ov772x_mask_set(client,
757 EDGE_LOWER, OV772X_EDGE_LOWER_MASK,
758 priv->info->edgectrl.lower);
759 if (ret < 0)
760 goto ov772x_set_fmt_error;
761 }
762
763 /* Format and window size */
764 ret = ov772x_write(client, HSTART, win->rect.left >> 2);
765 if (ret < 0)
766 goto ov772x_set_fmt_error;
767 ret = ov772x_write(client, HSIZE, win->rect.width >> 2);
768 if (ret < 0)
769 goto ov772x_set_fmt_error;
770 ret = ov772x_write(client, VSTART, win->rect.top >> 1);
771 if (ret < 0)
772 goto ov772x_set_fmt_error;
773 ret = ov772x_write(client, VSIZE, win->rect.height >> 1);
774 if (ret < 0)
775 goto ov772x_set_fmt_error;
776 ret = ov772x_write(client, HOUTSIZE, win->rect.width >> 2);
777 if (ret < 0)
778 goto ov772x_set_fmt_error;
779 ret = ov772x_write(client, VOUTSIZE, win->rect.height >> 1);
780 if (ret < 0)
781 goto ov772x_set_fmt_error;
782 ret = ov772x_write(client, HREF,
783 ((win->rect.top & 1) << HREF_VSTART_SHIFT) |
784 ((win->rect.left & 3) << HREF_HSTART_SHIFT) |
785 ((win->rect.height & 1) << HREF_VSIZE_SHIFT) |
786 ((win->rect.width & 3) << HREF_HSIZE_SHIFT));
787 if (ret < 0)
788 goto ov772x_set_fmt_error;
789 ret = ov772x_write(client, EXHCH,
790 ((win->rect.height & 1) << EXHCH_VSIZE_SHIFT) |
791 ((win->rect.width & 3) << EXHCH_HSIZE_SHIFT));
792 if (ret < 0)
793 goto ov772x_set_fmt_error;
794
795 /*
796 * set DSP_CTRL3
797 */
798 val = cfmt->dsp3;
799 if (val) {
800 ret = ov772x_mask_set(client,
801 DSP_CTRL3, UV_MASK, val);
802 if (ret < 0)
803 goto ov772x_set_fmt_error;
804 }
805
806 /* DSP_CTRL4: AEC reference point and DSP output format. */
807 if (cfmt->dsp4) {
808 ret = ov772x_write(client, DSP_CTRL4, cfmt->dsp4);
809 if (ret < 0)
810 goto ov772x_set_fmt_error;
811 }
812
813 /*
814 * set COM3
815 */
816 val = cfmt->com3;
817 if (priv->info->flags & OV772X_FLAG_VFLIP)
818 val |= VFLIP_IMG;
819 if (priv->info->flags & OV772X_FLAG_HFLIP)
820 val |= HFLIP_IMG;
821 if (priv->flag_vflip)
822 val ^= VFLIP_IMG;
823 if (priv->flag_hflip)
824 val ^= HFLIP_IMG;
825
826 ret = ov772x_mask_set(client,
827 COM3, SWAP_MASK | IMG_MASK, val);
828 if (ret < 0)
829 goto ov772x_set_fmt_error;
830
831 /* COM7: Sensor resolution and output format control. */
832 ret = ov772x_write(client, COM7, win->com7_bit | cfmt->com7);
833 if (ret < 0)
834 goto ov772x_set_fmt_error;
835
836 /*
837 * set COM8
838 */
839 if (priv->band_filter) {
840 ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, 1);
841 if (!ret)
842 ret = ov772x_mask_set(client, BDBASE,
843 0xff, 256 - priv->band_filter);
844 if (ret < 0)
845 goto ov772x_set_fmt_error;
846 }
847
848 return ret;
849
850 ov772x_set_fmt_error:
851
852 ov772x_reset(client);
853
854 return ret;
855 }
856
857 static int ov772x_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
858 {
859 a->c.left = 0;
860 a->c.top = 0;
861 a->c.width = VGA_WIDTH;
862 a->c.height = VGA_HEIGHT;
863 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
864
865 return 0;
866 }
867
868 static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
869 {
870 a->bounds.left = 0;
871 a->bounds.top = 0;
872 a->bounds.width = OV772X_MAX_WIDTH;
873 a->bounds.height = OV772X_MAX_HEIGHT;
874 a->defrect = a->bounds;
875 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
876 a->pixelaspect.numerator = 1;
877 a->pixelaspect.denominator = 1;
878
879 return 0;
880 }
881
882 static int ov772x_g_fmt(struct v4l2_subdev *sd,
883 struct v4l2_mbus_framefmt *mf)
884 {
885 struct ov772x_priv *priv = to_ov772x(sd);
886
887 mf->width = priv->win->rect.width;
888 mf->height = priv->win->rect.height;
889 mf->code = priv->cfmt->code;
890 mf->colorspace = priv->cfmt->colorspace;
891 mf->field = V4L2_FIELD_NONE;
892
893 return 0;
894 }
895
896 static int ov772x_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
897 {
898 struct ov772x_priv *priv = to_ov772x(sd);
899 const struct ov772x_color_format *cfmt;
900 const struct ov772x_win_size *win;
901 int ret;
902
903 ov772x_select_params(mf, &cfmt, &win);
904
905 ret = ov772x_set_params(priv, cfmt, win);
906 if (ret < 0)
907 return ret;
908
909 priv->win = win;
910 priv->cfmt = cfmt;
911
912 mf->code = cfmt->code;
913 mf->width = win->rect.width;
914 mf->height = win->rect.height;
915 mf->field = V4L2_FIELD_NONE;
916 mf->colorspace = cfmt->colorspace;
917
918 return 0;
919 }
920
921 static int ov772x_try_fmt(struct v4l2_subdev *sd,
922 struct v4l2_mbus_framefmt *mf)
923 {
924 const struct ov772x_color_format *cfmt;
925 const struct ov772x_win_size *win;
926
927 ov772x_select_params(mf, &cfmt, &win);
928
929 mf->code = cfmt->code;
930 mf->width = win->rect.width;
931 mf->height = win->rect.height;
932 mf->field = V4L2_FIELD_NONE;
933 mf->colorspace = cfmt->colorspace;
934
935 return 0;
936 }
937
938 static int ov772x_video_probe(struct ov772x_priv *priv)
939 {
940 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
941 u8 pid, ver;
942 const char *devname;
943 int ret;
944
945 ret = ov772x_s_power(&priv->subdev, 1);
946 if (ret < 0)
947 return ret;
948
949 /*
950 * check and show product ID and manufacturer ID
951 */
952 pid = ov772x_read(client, PID);
953 ver = ov772x_read(client, VER);
954
955 switch (VERSION(pid, ver)) {
956 case OV7720:
957 devname = "ov7720";
958 break;
959 case OV7725:
960 devname = "ov7725";
961 break;
962 default:
963 dev_err(&client->dev,
964 "Product ID error %x:%x\n", pid, ver);
965 ret = -ENODEV;
966 goto done;
967 }
968
969 dev_info(&client->dev,
970 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
971 devname,
972 pid,
973 ver,
974 ov772x_read(client, MIDH),
975 ov772x_read(client, MIDL));
976 ret = v4l2_ctrl_handler_setup(&priv->hdl);
977
978 done:
979 ov772x_s_power(&priv->subdev, 0);
980 return ret;
981 }
982
983 static const struct v4l2_ctrl_ops ov772x_ctrl_ops = {
984 .s_ctrl = ov772x_s_ctrl,
985 };
986
987 static struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
988 #ifdef CONFIG_VIDEO_ADV_DEBUG
989 .g_register = ov772x_g_register,
990 .s_register = ov772x_s_register,
991 #endif
992 .s_power = ov772x_s_power,
993 };
994
995 static int ov772x_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
996 enum v4l2_mbus_pixelcode *code)
997 {
998 if (index >= ARRAY_SIZE(ov772x_cfmts))
999 return -EINVAL;
1000
1001 *code = ov772x_cfmts[index].code;
1002 return 0;
1003 }
1004
1005 static int ov772x_g_mbus_config(struct v4l2_subdev *sd,
1006 struct v4l2_mbus_config *cfg)
1007 {
1008 struct i2c_client *client = v4l2_get_subdevdata(sd);
1009 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1010
1011 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1012 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1013 V4L2_MBUS_DATA_ACTIVE_HIGH;
1014 cfg->type = V4L2_MBUS_PARALLEL;
1015 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
1016
1017 return 0;
1018 }
1019
1020 static struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
1021 .s_stream = ov772x_s_stream,
1022 .g_mbus_fmt = ov772x_g_fmt,
1023 .s_mbus_fmt = ov772x_s_fmt,
1024 .try_mbus_fmt = ov772x_try_fmt,
1025 .cropcap = ov772x_cropcap,
1026 .g_crop = ov772x_g_crop,
1027 .enum_mbus_fmt = ov772x_enum_fmt,
1028 .g_mbus_config = ov772x_g_mbus_config,
1029 };
1030
1031 static struct v4l2_subdev_ops ov772x_subdev_ops = {
1032 .core = &ov772x_subdev_core_ops,
1033 .video = &ov772x_subdev_video_ops,
1034 };
1035
1036 /*
1037 * i2c_driver function
1038 */
1039
1040 static int ov772x_probe(struct i2c_client *client,
1041 const struct i2c_device_id *did)
1042 {
1043 struct ov772x_priv *priv;
1044 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1045 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1046 int ret;
1047
1048 if (!ssdd || !ssdd->drv_priv) {
1049 dev_err(&client->dev, "OV772X: missing platform data!\n");
1050 return -EINVAL;
1051 }
1052
1053 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1054 dev_err(&adapter->dev,
1055 "I2C-Adapter doesn't support "
1056 "I2C_FUNC_SMBUS_BYTE_DATA\n");
1057 return -EIO;
1058 }
1059
1060 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1061 if (!priv)
1062 return -ENOMEM;
1063
1064 priv->info = ssdd->drv_priv;
1065
1066 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
1067 v4l2_ctrl_handler_init(&priv->hdl, 3);
1068 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1069 V4L2_CID_VFLIP, 0, 1, 1, 0);
1070 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1071 V4L2_CID_HFLIP, 0, 1, 1, 0);
1072 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1073 V4L2_CID_BAND_STOP_FILTER, 0, 256, 1, 0);
1074 priv->subdev.ctrl_handler = &priv->hdl;
1075 if (priv->hdl.error)
1076 return priv->hdl.error;
1077
1078 priv->clk = v4l2_clk_get(&client->dev, "mclk");
1079 if (IS_ERR(priv->clk)) {
1080 ret = PTR_ERR(priv->clk);
1081 goto eclkget;
1082 }
1083
1084 ret = ov772x_video_probe(priv);
1085 if (ret < 0) {
1086 v4l2_clk_put(priv->clk);
1087 eclkget:
1088 v4l2_ctrl_handler_free(&priv->hdl);
1089 } else {
1090 priv->cfmt = &ov772x_cfmts[0];
1091 priv->win = &ov772x_win_sizes[0];
1092 }
1093
1094 return ret;
1095 }
1096
1097 static int ov772x_remove(struct i2c_client *client)
1098 {
1099 struct ov772x_priv *priv = to_ov772x(i2c_get_clientdata(client));
1100
1101 v4l2_clk_put(priv->clk);
1102 v4l2_device_unregister_subdev(&priv->subdev);
1103 v4l2_ctrl_handler_free(&priv->hdl);
1104 return 0;
1105 }
1106
1107 static const struct i2c_device_id ov772x_id[] = {
1108 { "ov772x", 0 },
1109 { }
1110 };
1111 MODULE_DEVICE_TABLE(i2c, ov772x_id);
1112
1113 static struct i2c_driver ov772x_i2c_driver = {
1114 .driver = {
1115 .name = "ov772x",
1116 },
1117 .probe = ov772x_probe,
1118 .remove = ov772x_remove,
1119 .id_table = ov772x_id,
1120 };
1121
1122 module_i2c_driver(ov772x_i2c_driver);
1123
1124 MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1125 MODULE_AUTHOR("Kuninori Morimoto");
1126 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support