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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / pci / cx23885 / cx23885-cards.c
blob79f20c8c842ed1a1f12b34a0eeab0e133fdd3e7b
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <media/cx25840.h>
27 #include <linux/firmware.h>
28 #include <misc/altera.h>
29
30 #include "cx23885.h"
31 #include "tuner-xc2028.h"
32 #include "netup-eeprom.h"
33 #include "netup-init.h"
34 #include "altera-ci.h"
35 #include "xc4000.h"
36 #include "xc5000.h"
37 #include "cx23888-ir.h"
38
39 static unsigned int netup_card_rev = 4;
40 module_param(netup_card_rev, int, 0644);
41 MODULE_PARM_DESC(netup_card_rev,
42 "NetUP Dual DVB-T/C CI card revision");
43 static unsigned int enable_885_ir;
44 module_param(enable_885_ir, int, 0644);
45 MODULE_PARM_DESC(enable_885_ir,
46 "Enable integrated IR controller for supported\n"
47 "\t\t CX2388[57] boards that are wired for it:\n"
48 "\t\t\tHVR-1250 (reported safe)\n"
49 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
50 "\t\t\tTeVii S470 (reported unsafe)\n"
51 "\t\t This can cause an interrupt storm with some cards.\n"
52 "\t\t Default: 0 [Disabled]");
53
54 /* ------------------------------------------------------------------ */
55 /* board config info */
56
57 struct cx23885_board cx23885_boards[] = {
58 [CX23885_BOARD_UNKNOWN] = {
59 .name = "UNKNOWN/GENERIC",
60 /* Ensure safe default for unknown boards */
61 .clk_freq = 0,
62 .input = {{
63 .type = CX23885_VMUX_COMPOSITE1,
64 .vmux = 0,
65 }, {
66 .type = CX23885_VMUX_COMPOSITE2,
67 .vmux = 1,
68 }, {
69 .type = CX23885_VMUX_COMPOSITE3,
70 .vmux = 2,
71 }, {
72 .type = CX23885_VMUX_COMPOSITE4,
73 .vmux = 3,
74 } },
75 },
76 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
77 .name = "Hauppauge WinTV-HVR1800lp",
78 .portc = CX23885_MPEG_DVB,
79 .input = {{
80 .type = CX23885_VMUX_TELEVISION,
81 .vmux = 0,
82 .gpio0 = 0xff00,
83 }, {
84 .type = CX23885_VMUX_DEBUG,
85 .vmux = 0,
86 .gpio0 = 0xff01,
87 }, {
88 .type = CX23885_VMUX_COMPOSITE1,
89 .vmux = 1,
90 .gpio0 = 0xff02,
91 }, {
92 .type = CX23885_VMUX_SVIDEO,
93 .vmux = 2,
94 .gpio0 = 0xff02,
95 } },
96 },
97 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
98 .name = "Hauppauge WinTV-HVR1800",
99 .porta = CX23885_ANALOG_VIDEO,
100 .portb = CX23885_MPEG_ENCODER,
101 .portc = CX23885_MPEG_DVB,
102 .tuner_type = TUNER_PHILIPS_TDA8290,
103 .tuner_addr = 0x42, /* 0x84 >> 1 */
104 .tuner_bus = 1,
105 .input = {{
106 .type = CX23885_VMUX_TELEVISION,
107 .vmux = CX25840_VIN7_CH3 |
108 CX25840_VIN5_CH2 |
109 CX25840_VIN2_CH1,
110 .amux = CX25840_AUDIO8,
111 .gpio0 = 0,
112 }, {
113 .type = CX23885_VMUX_COMPOSITE1,
114 .vmux = CX25840_VIN7_CH3 |
115 CX25840_VIN4_CH2 |
116 CX25840_VIN6_CH1,
117 .amux = CX25840_AUDIO7,
118 .gpio0 = 0,
119 }, {
120 .type = CX23885_VMUX_SVIDEO,
121 .vmux = CX25840_VIN7_CH3 |
122 CX25840_VIN4_CH2 |
123 CX25840_VIN8_CH1 |
124 CX25840_SVIDEO_ON,
125 .amux = CX25840_AUDIO7,
126 .gpio0 = 0,
127 } },
128 },
129 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
130 .name = "Hauppauge WinTV-HVR1250",
131 .porta = CX23885_ANALOG_VIDEO,
132 .portc = CX23885_MPEG_DVB,
133 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
134 .tuner_type = TUNER_PHILIPS_TDA8290,
135 .tuner_addr = 0x42, /* 0x84 >> 1 */
136 .tuner_bus = 1,
137 #endif
138 .force_bff = 1,
139 .input = {{
140 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
141 .type = CX23885_VMUX_TELEVISION,
142 .vmux = CX25840_VIN7_CH3 |
143 CX25840_VIN5_CH2 |
144 CX25840_VIN2_CH1,
145 .amux = CX25840_AUDIO8,
146 .gpio0 = 0xff00,
147 }, {
148 #endif
149 .type = CX23885_VMUX_COMPOSITE1,
150 .vmux = CX25840_VIN7_CH3 |
151 CX25840_VIN4_CH2 |
152 CX25840_VIN6_CH1,
153 .amux = CX25840_AUDIO7,
154 .gpio0 = 0xff02,
155 }, {
156 .type = CX23885_VMUX_SVIDEO,
157 .vmux = CX25840_VIN7_CH3 |
158 CX25840_VIN4_CH2 |
159 CX25840_VIN8_CH1 |
160 CX25840_SVIDEO_ON,
161 .amux = CX25840_AUDIO7,
162 .gpio0 = 0xff02,
163 } },
164 },
165 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
166 .name = "DViCO FusionHDTV5 Express",
167 .portb = CX23885_MPEG_DVB,
168 },
169 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
170 .name = "Hauppauge WinTV-HVR1500Q",
171 .portc = CX23885_MPEG_DVB,
172 },
173 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
174 .name = "Hauppauge WinTV-HVR1500",
175 .porta = CX23885_ANALOG_VIDEO,
176 .portc = CX23885_MPEG_DVB,
177 .tuner_type = TUNER_XC2028,
178 .tuner_addr = 0x61, /* 0xc2 >> 1 */
179 .input = {{
180 .type = CX23885_VMUX_TELEVISION,
181 .vmux = CX25840_VIN7_CH3 |
182 CX25840_VIN5_CH2 |
183 CX25840_VIN2_CH1,
184 .gpio0 = 0,
185 }, {
186 .type = CX23885_VMUX_COMPOSITE1,
187 .vmux = CX25840_VIN7_CH3 |
188 CX25840_VIN4_CH2 |
189 CX25840_VIN6_CH1,
190 .gpio0 = 0,
191 }, {
192 .type = CX23885_VMUX_SVIDEO,
193 .vmux = CX25840_VIN7_CH3 |
194 CX25840_VIN4_CH2 |
195 CX25840_VIN8_CH1 |
196 CX25840_SVIDEO_ON,
197 .gpio0 = 0,
198 } },
199 },
200 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
201 .name = "Hauppauge WinTV-HVR1200",
202 .portc = CX23885_MPEG_DVB,
203 },
204 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
205 .name = "Hauppauge WinTV-HVR1700",
206 .portc = CX23885_MPEG_DVB,
207 },
208 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
209 .name = "Hauppauge WinTV-HVR1400",
210 .portc = CX23885_MPEG_DVB,
211 },
212 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
213 .name = "DViCO FusionHDTV7 Dual Express",
214 .portb = CX23885_MPEG_DVB,
215 .portc = CX23885_MPEG_DVB,
216 },
217 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
218 .name = "DViCO FusionHDTV DVB-T Dual Express",
219 .portb = CX23885_MPEG_DVB,
220 .portc = CX23885_MPEG_DVB,
221 },
222 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
223 .name = "Leadtek Winfast PxDVR3200 H",
224 .portc = CX23885_MPEG_DVB,
225 },
226 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = {
227 .name = "Leadtek Winfast PxPVR2200",
228 .porta = CX23885_ANALOG_VIDEO,
229 .tuner_type = TUNER_XC2028,
230 .tuner_addr = 0x61,
231 .tuner_bus = 1,
232 .input = {{
233 .type = CX23885_VMUX_TELEVISION,
234 .vmux = CX25840_VIN2_CH1 |
235 CX25840_VIN5_CH2,
236 .amux = CX25840_AUDIO8,
237 .gpio0 = 0x704040,
238 }, {
239 .type = CX23885_VMUX_COMPOSITE1,
240 .vmux = CX25840_COMPOSITE1,
241 .amux = CX25840_AUDIO7,
242 .gpio0 = 0x704040,
243 }, {
244 .type = CX23885_VMUX_SVIDEO,
245 .vmux = CX25840_SVIDEO_LUMA3 |
246 CX25840_SVIDEO_CHROMA4,
247 .amux = CX25840_AUDIO7,
248 .gpio0 = 0x704040,
249 }, {
250 .type = CX23885_VMUX_COMPONENT,
251 .vmux = CX25840_VIN7_CH1 |
252 CX25840_VIN6_CH2 |
253 CX25840_VIN8_CH3 |
254 CX25840_COMPONENT_ON,
255 .amux = CX25840_AUDIO7,
256 .gpio0 = 0x704040,
257 } },
258 },
259 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
260 .name = "Leadtek Winfast PxDVR3200 H XC4000",
261 .porta = CX23885_ANALOG_VIDEO,
262 .portc = CX23885_MPEG_DVB,
263 .tuner_type = TUNER_XC4000,
264 .tuner_addr = 0x61,
265 .radio_type = UNSET,
266 .radio_addr = ADDR_UNSET,
267 .input = {{
268 .type = CX23885_VMUX_TELEVISION,
269 .vmux = CX25840_VIN2_CH1 |
270 CX25840_VIN5_CH2 |
271 CX25840_NONE0_CH3,
272 }, {
273 .type = CX23885_VMUX_COMPOSITE1,
274 .vmux = CX25840_COMPOSITE1,
275 }, {
276 .type = CX23885_VMUX_SVIDEO,
277 .vmux = CX25840_SVIDEO_LUMA3 |
278 CX25840_SVIDEO_CHROMA4,
279 }, {
280 .type = CX23885_VMUX_COMPONENT,
281 .vmux = CX25840_VIN7_CH1 |
282 CX25840_VIN6_CH2 |
283 CX25840_VIN8_CH3 |
284 CX25840_COMPONENT_ON,
285 } },
286 },
287 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
288 .name = "Compro VideoMate E650F",
289 .portc = CX23885_MPEG_DVB,
290 },
291 [CX23885_BOARD_TBS_6920] = {
292 .name = "TurboSight TBS 6920",
293 .portb = CX23885_MPEG_DVB,
294 },
295 [CX23885_BOARD_TBS_6980] = {
296 .name = "TurboSight TBS 6980",
297 .portb = CX23885_MPEG_DVB,
298 .portc = CX23885_MPEG_DVB,
299 },
300 [CX23885_BOARD_TBS_6981] = {
301 .name = "TurboSight TBS 6981",
302 .portb = CX23885_MPEG_DVB,
303 .portc = CX23885_MPEG_DVB,
304 },
305 [CX23885_BOARD_TEVII_S470] = {
306 .name = "TeVii S470",
307 .portb = CX23885_MPEG_DVB,
308 },
309 [CX23885_BOARD_DVBWORLD_2005] = {
310 .name = "DVBWorld DVB-S2 2005",
311 .portb = CX23885_MPEG_DVB,
312 },
313 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
314 .ci_type = 1,
315 .name = "NetUP Dual DVB-S2 CI",
316 .portb = CX23885_MPEG_DVB,
317 .portc = CX23885_MPEG_DVB,
318 },
319 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
320 .name = "Hauppauge WinTV-HVR1270",
321 .portc = CX23885_MPEG_DVB,
322 },
323 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
324 .name = "Hauppauge WinTV-HVR1275",
325 .portc = CX23885_MPEG_DVB,
326 },
327 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
328 .name = "Hauppauge WinTV-HVR1255",
329 .porta = CX23885_ANALOG_VIDEO,
330 .portc = CX23885_MPEG_DVB,
331 .tuner_type = TUNER_ABSENT,
332 .tuner_addr = 0x42, /* 0x84 >> 1 */
333 .force_bff = 1,
334 .input = {{
335 .type = CX23885_VMUX_TELEVISION,
336 .vmux = CX25840_VIN7_CH3 |
337 CX25840_VIN5_CH2 |
338 CX25840_VIN2_CH1 |
339 CX25840_DIF_ON,
340 .amux = CX25840_AUDIO8,
341 }, {
342 .type = CX23885_VMUX_COMPOSITE1,
343 .vmux = CX25840_VIN7_CH3 |
344 CX25840_VIN4_CH2 |
345 CX25840_VIN6_CH1,
346 .amux = CX25840_AUDIO7,
347 }, {
348 .type = CX23885_VMUX_SVIDEO,
349 .vmux = CX25840_VIN7_CH3 |
350 CX25840_VIN4_CH2 |
351 CX25840_VIN8_CH1 |
352 CX25840_SVIDEO_ON,
353 .amux = CX25840_AUDIO7,
354 } },
355 },
356 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
357 .name = "Hauppauge WinTV-HVR1255",
358 .porta = CX23885_ANALOG_VIDEO,
359 .portc = CX23885_MPEG_DVB,
360 .tuner_type = TUNER_ABSENT,
361 .tuner_addr = 0x42, /* 0x84 >> 1 */
362 .force_bff = 1,
363 .input = {{
364 .type = CX23885_VMUX_TELEVISION,
365 .vmux = CX25840_VIN7_CH3 |
366 CX25840_VIN5_CH2 |
367 CX25840_VIN2_CH1 |
368 CX25840_DIF_ON,
369 .amux = CX25840_AUDIO8,
370 }, {
371 .type = CX23885_VMUX_SVIDEO,
372 .vmux = CX25840_VIN7_CH3 |
373 CX25840_VIN4_CH2 |
374 CX25840_VIN8_CH1 |
375 CX25840_SVIDEO_ON,
376 .amux = CX25840_AUDIO7,
377 } },
378 },
379 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
380 .name = "Hauppauge WinTV-HVR1210",
381 .portc = CX23885_MPEG_DVB,
382 },
383 [CX23885_BOARD_MYGICA_X8506] = {
384 .name = "Mygica X8506 DMB-TH",
385 .tuner_type = TUNER_XC5000,
386 .tuner_addr = 0x61,
387 .tuner_bus = 1,
388 .porta = CX23885_ANALOG_VIDEO,
389 .portb = CX23885_MPEG_DVB,
390 .input = {
391 {
392 .type = CX23885_VMUX_TELEVISION,
393 .vmux = CX25840_COMPOSITE2,
394 },
395 {
396 .type = CX23885_VMUX_COMPOSITE1,
397 .vmux = CX25840_COMPOSITE8,
398 },
399 {
400 .type = CX23885_VMUX_SVIDEO,
401 .vmux = CX25840_SVIDEO_LUMA3 |
402 CX25840_SVIDEO_CHROMA4,
403 },
404 {
405 .type = CX23885_VMUX_COMPONENT,
406 .vmux = CX25840_COMPONENT_ON |
407 CX25840_VIN1_CH1 |
408 CX25840_VIN6_CH2 |
409 CX25840_VIN7_CH3,
410 },
411 },
412 },
413 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
414 .name = "Magic-Pro ProHDTV Extreme 2",
415 .tuner_type = TUNER_XC5000,
416 .tuner_addr = 0x61,
417 .tuner_bus = 1,
418 .porta = CX23885_ANALOG_VIDEO,
419 .portb = CX23885_MPEG_DVB,
420 .input = {
421 {
422 .type = CX23885_VMUX_TELEVISION,
423 .vmux = CX25840_COMPOSITE2,
424 },
425 {
426 .type = CX23885_VMUX_COMPOSITE1,
427 .vmux = CX25840_COMPOSITE8,
428 },
429 {
430 .type = CX23885_VMUX_SVIDEO,
431 .vmux = CX25840_SVIDEO_LUMA3 |
432 CX25840_SVIDEO_CHROMA4,
433 },
434 {
435 .type = CX23885_VMUX_COMPONENT,
436 .vmux = CX25840_COMPONENT_ON |
437 CX25840_VIN1_CH1 |
438 CX25840_VIN6_CH2 |
439 CX25840_VIN7_CH3,
440 },
441 },
442 },
443 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
444 .name = "Hauppauge WinTV-HVR1850",
445 .porta = CX23885_ANALOG_VIDEO,
446 .portb = CX23885_MPEG_ENCODER,
447 .portc = CX23885_MPEG_DVB,
448 .tuner_type = TUNER_ABSENT,
449 .tuner_addr = 0x42, /* 0x84 >> 1 */
450 .force_bff = 1,
451 .input = {{
452 .type = CX23885_VMUX_TELEVISION,
453 .vmux = CX25840_VIN7_CH3 |
454 CX25840_VIN5_CH2 |
455 CX25840_VIN2_CH1 |
456 CX25840_DIF_ON,
457 .amux = CX25840_AUDIO8,
458 }, {
459 .type = CX23885_VMUX_COMPOSITE1,
460 .vmux = CX25840_VIN7_CH3 |
461 CX25840_VIN4_CH2 |
462 CX25840_VIN6_CH1,
463 .amux = CX25840_AUDIO7,
464 }, {
465 .type = CX23885_VMUX_SVIDEO,
466 .vmux = CX25840_VIN7_CH3 |
467 CX25840_VIN4_CH2 |
468 CX25840_VIN8_CH1 |
469 CX25840_SVIDEO_ON,
470 .amux = CX25840_AUDIO7,
471 } },
472 },
473 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
474 .name = "Compro VideoMate E800",
475 .portc = CX23885_MPEG_DVB,
476 },
477 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
478 .name = "Hauppauge WinTV-HVR1290",
479 .portc = CX23885_MPEG_DVB,
480 },
481 [CX23885_BOARD_MYGICA_X8558PRO] = {
482 .name = "Mygica X8558 PRO DMB-TH",
483 .portb = CX23885_MPEG_DVB,
484 .portc = CX23885_MPEG_DVB,
485 },
486 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
487 .name = "LEADTEK WinFast PxTV1200",
488 .porta = CX23885_ANALOG_VIDEO,
489 .tuner_type = TUNER_XC2028,
490 .tuner_addr = 0x61,
491 .tuner_bus = 1,
492 .input = {{
493 .type = CX23885_VMUX_TELEVISION,
494 .vmux = CX25840_VIN2_CH1 |
495 CX25840_VIN5_CH2 |
496 CX25840_NONE0_CH3,
497 }, {
498 .type = CX23885_VMUX_COMPOSITE1,
499 .vmux = CX25840_COMPOSITE1,
500 }, {
501 .type = CX23885_VMUX_SVIDEO,
502 .vmux = CX25840_SVIDEO_LUMA3 |
503 CX25840_SVIDEO_CHROMA4,
504 }, {
505 .type = CX23885_VMUX_COMPONENT,
506 .vmux = CX25840_VIN7_CH1 |
507 CX25840_VIN6_CH2 |
508 CX25840_VIN8_CH3 |
509 CX25840_COMPONENT_ON,
510 } },
511 },
512 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
513 .name = "GoTView X5 3D Hybrid",
514 .tuner_type = TUNER_XC5000,
515 .tuner_addr = 0x64,
516 .tuner_bus = 1,
517 .porta = CX23885_ANALOG_VIDEO,
518 .portb = CX23885_MPEG_DVB,
519 .input = {{
520 .type = CX23885_VMUX_TELEVISION,
521 .vmux = CX25840_VIN2_CH1 |
522 CX25840_VIN5_CH2,
523 .gpio0 = 0x02,
524 }, {
525 .type = CX23885_VMUX_COMPOSITE1,
526 .vmux = CX23885_VMUX_COMPOSITE1,
527 }, {
528 .type = CX23885_VMUX_SVIDEO,
529 .vmux = CX25840_SVIDEO_LUMA3 |
530 CX25840_SVIDEO_CHROMA4,
531 } },
532 },
533 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
534 .ci_type = 2,
535 .name = "NetUP Dual DVB-T/C-CI RF",
536 .porta = CX23885_ANALOG_VIDEO,
537 .portb = CX23885_MPEG_DVB,
538 .portc = CX23885_MPEG_DVB,
539 .num_fds_portb = 2,
540 .num_fds_portc = 2,
541 .tuner_type = TUNER_XC5000,
542 .tuner_addr = 0x64,
543 .input = { {
544 .type = CX23885_VMUX_TELEVISION,
545 .vmux = CX25840_COMPOSITE1,
546 } },
547 },
548 [CX23885_BOARD_MPX885] = {
549 .name = "MPX-885",
550 .porta = CX23885_ANALOG_VIDEO,
551 .input = {{
552 .type = CX23885_VMUX_COMPOSITE1,
553 .vmux = CX25840_COMPOSITE1,
554 .amux = CX25840_AUDIO6,
555 .gpio0 = 0,
556 }, {
557 .type = CX23885_VMUX_COMPOSITE2,
558 .vmux = CX25840_COMPOSITE2,
559 .amux = CX25840_AUDIO6,
560 .gpio0 = 0,
561 }, {
562 .type = CX23885_VMUX_COMPOSITE3,
563 .vmux = CX25840_COMPOSITE3,
564 .amux = CX25840_AUDIO7,
565 .gpio0 = 0,
566 }, {
567 .type = CX23885_VMUX_COMPOSITE4,
568 .vmux = CX25840_COMPOSITE4,
569 .amux = CX25840_AUDIO7,
570 .gpio0 = 0,
571 } },
572 },
573 [CX23885_BOARD_MYGICA_X8507] = {
574 .name = "Mygica X8502/X8507 ISDB-T",
575 .tuner_type = TUNER_XC5000,
576 .tuner_addr = 0x61,
577 .tuner_bus = 1,
578 .porta = CX23885_ANALOG_VIDEO,
579 .portb = CX23885_MPEG_DVB,
580 .input = {
581 {
582 .type = CX23885_VMUX_TELEVISION,
583 .vmux = CX25840_COMPOSITE2,
584 .amux = CX25840_AUDIO8,
585 },
586 {
587 .type = CX23885_VMUX_COMPOSITE1,
588 .vmux = CX25840_COMPOSITE8,
589 .amux = CX25840_AUDIO7,
590 },
591 {
592 .type = CX23885_VMUX_SVIDEO,
593 .vmux = CX25840_SVIDEO_LUMA3 |
594 CX25840_SVIDEO_CHROMA4,
595 .amux = CX25840_AUDIO7,
596 },
597 {
598 .type = CX23885_VMUX_COMPONENT,
599 .vmux = CX25840_COMPONENT_ON |
600 CX25840_VIN1_CH1 |
601 CX25840_VIN6_CH2 |
602 CX25840_VIN7_CH3,
603 .amux = CX25840_AUDIO7,
604 },
605 },
606 },
607 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
608 .name = "TerraTec Cinergy T PCIe Dual",
609 .portb = CX23885_MPEG_DVB,
610 .portc = CX23885_MPEG_DVB,
611 },
612 [CX23885_BOARD_TEVII_S471] = {
613 .name = "TeVii S471",
614 .portb = CX23885_MPEG_DVB,
615 },
616 [CX23885_BOARD_PROF_8000] = {
617 .name = "Prof Revolution DVB-S2 8000",
618 .portb = CX23885_MPEG_DVB,
619 },
620 [CX23885_BOARD_HAUPPAUGE_HVR4400] = {
621 .name = "Hauppauge WinTV-HVR4400",
622 .portb = CX23885_MPEG_DVB,
623 },
624 [CX23885_BOARD_AVERMEDIA_HC81R] = {
625 .name = "AVerTV Hybrid Express Slim HC81R",
626 .tuner_type = TUNER_XC2028,
627 .tuner_addr = 0x61, /* 0xc2 >> 1 */
628 .tuner_bus = 1,
629 .porta = CX23885_ANALOG_VIDEO,
630 .input = {{
631 .type = CX23885_VMUX_TELEVISION,
632 .vmux = CX25840_VIN2_CH1 |
633 CX25840_VIN5_CH2 |
634 CX25840_NONE0_CH3 |
635 CX25840_NONE1_CH3,
636 .amux = CX25840_AUDIO8,
637 }, {
638 .type = CX23885_VMUX_SVIDEO,
639 .vmux = CX25840_VIN8_CH1 |
640 CX25840_NONE_CH2 |
641 CX25840_VIN7_CH3 |
642 CX25840_SVIDEO_ON,
643 .amux = CX25840_AUDIO6,
644 }, {
645 .type = CX23885_VMUX_COMPONENT,
646 .vmux = CX25840_VIN1_CH1 |
647 CX25840_NONE_CH2 |
648 CX25840_NONE0_CH3 |
649 CX25840_NONE1_CH3,
650 .amux = CX25840_AUDIO6,
651 } },
652 }
653 };
654 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
655
656 /* ------------------------------------------------------------------ */
657 /* PCI subsystem IDs */
658
659 struct cx23885_subid cx23885_subids[] = {
660 {
661 .subvendor = 0x0070,
662 .subdevice = 0x3400,
663 .card = CX23885_BOARD_UNKNOWN,
664 }, {
665 .subvendor = 0x0070,
666 .subdevice = 0x7600,
667 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
668 }, {
669 .subvendor = 0x0070,
670 .subdevice = 0x7800,
671 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
672 }, {
673 .subvendor = 0x0070,
674 .subdevice = 0x7801,
675 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
676 }, {
677 .subvendor = 0x0070,
678 .subdevice = 0x7809,
679 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
680 }, {
681 .subvendor = 0x0070,
682 .subdevice = 0x7911,
683 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
684 }, {
685 .subvendor = 0x18ac,
686 .subdevice = 0xd500,
687 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
688 }, {
689 .subvendor = 0x0070,
690 .subdevice = 0x7790,
691 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
692 }, {
693 .subvendor = 0x0070,
694 .subdevice = 0x7797,
695 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
696 }, {
697 .subvendor = 0x0070,
698 .subdevice = 0x7710,
699 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
700 }, {
701 .subvendor = 0x0070,
702 .subdevice = 0x7717,
703 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
704 }, {
705 .subvendor = 0x0070,
706 .subdevice = 0x71d1,
707 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
708 }, {
709 .subvendor = 0x0070,
710 .subdevice = 0x71d3,
711 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
712 }, {
713 .subvendor = 0x0070,
714 .subdevice = 0x8101,
715 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
716 }, {
717 .subvendor = 0x0070,
718 .subdevice = 0x8010,
719 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
720 }, {
721 .subvendor = 0x18ac,
722 .subdevice = 0xd618,
723 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
724 }, {
725 .subvendor = 0x18ac,
726 .subdevice = 0xdb78,
727 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
728 }, {
729 .subvendor = 0x107d,
730 .subdevice = 0x6681,
731 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
732 }, {
733 .subvendor = 0x107d,
734 .subdevice = 0x6f21,
735 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200,
736 }, {
737 .subvendor = 0x107d,
738 .subdevice = 0x6f39,
739 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
740 }, {
741 .subvendor = 0x185b,
742 .subdevice = 0xe800,
743 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
744 }, {
745 .subvendor = 0x6920,
746 .subdevice = 0x8888,
747 .card = CX23885_BOARD_TBS_6920,
748 }, {
749 .subvendor = 0x6980,
750 .subdevice = 0x8888,
751 .card = CX23885_BOARD_TBS_6980,
752 }, {
753 .subvendor = 0x6981,
754 .subdevice = 0x8888,
755 .card = CX23885_BOARD_TBS_6981,
756 }, {
757 .subvendor = 0xd470,
758 .subdevice = 0x9022,
759 .card = CX23885_BOARD_TEVII_S470,
760 }, {
761 .subvendor = 0x0001,
762 .subdevice = 0x2005,
763 .card = CX23885_BOARD_DVBWORLD_2005,
764 }, {
765 .subvendor = 0x1b55,
766 .subdevice = 0x2a2c,
767 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
768 }, {
769 .subvendor = 0x0070,
770 .subdevice = 0x2211,
771 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
772 }, {
773 .subvendor = 0x0070,
774 .subdevice = 0x2215,
775 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
776 }, {
777 .subvendor = 0x0070,
778 .subdevice = 0x221d,
779 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
780 }, {
781 .subvendor = 0x0070,
782 .subdevice = 0x2251,
783 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
784 }, {
785 .subvendor = 0x0070,
786 .subdevice = 0x2259,
787 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
788 }, {
789 .subvendor = 0x0070,
790 .subdevice = 0x2291,
791 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
792 }, {
793 .subvendor = 0x0070,
794 .subdevice = 0x2295,
795 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
796 }, {
797 .subvendor = 0x0070,
798 .subdevice = 0x2299,
799 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
800 }, {
801 .subvendor = 0x0070,
802 .subdevice = 0x229d,
803 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
804 }, {
805 .subvendor = 0x0070,
806 .subdevice = 0x22f0,
807 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
808 }, {
809 .subvendor = 0x0070,
810 .subdevice = 0x22f1,
811 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
812 }, {
813 .subvendor = 0x0070,
814 .subdevice = 0x22f2,
815 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
816 }, {
817 .subvendor = 0x0070,
818 .subdevice = 0x22f3,
819 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
820 }, {
821 .subvendor = 0x0070,
822 .subdevice = 0x22f4,
823 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
824 }, {
825 .subvendor = 0x0070,
826 .subdevice = 0x22f5,
827 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
828 }, {
829 .subvendor = 0x14f1,
830 .subdevice = 0x8651,
831 .card = CX23885_BOARD_MYGICA_X8506,
832 }, {
833 .subvendor = 0x14f1,
834 .subdevice = 0x8657,
835 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
836 }, {
837 .subvendor = 0x0070,
838 .subdevice = 0x8541,
839 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
840 }, {
841 .subvendor = 0x1858,
842 .subdevice = 0xe800,
843 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
844 }, {
845 .subvendor = 0x0070,
846 .subdevice = 0x8551,
847 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
848 }, {
849 .subvendor = 0x14f1,
850 .subdevice = 0x8578,
851 .card = CX23885_BOARD_MYGICA_X8558PRO,
852 }, {
853 .subvendor = 0x107d,
854 .subdevice = 0x6f22,
855 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
856 }, {
857 .subvendor = 0x5654,
858 .subdevice = 0x2390,
859 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
860 }, {
861 .subvendor = 0x1b55,
862 .subdevice = 0xe2e4,
863 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
864 }, {
865 .subvendor = 0x14f1,
866 .subdevice = 0x8502,
867 .card = CX23885_BOARD_MYGICA_X8507,
868 }, {
869 .subvendor = 0x153b,
870 .subdevice = 0x117e,
871 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
872 }, {
873 .subvendor = 0xd471,
874 .subdevice = 0x9022,
875 .card = CX23885_BOARD_TEVII_S471,
876 }, {
877 .subvendor = 0x8000,
878 .subdevice = 0x3034,
879 .card = CX23885_BOARD_PROF_8000,
880 }, {
881 .subvendor = 0x0070,
882 .subdevice = 0xc108,
883 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
884 }, {
885 .subvendor = 0x0070,
886 .subdevice = 0xc138,
887 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
888 }, {
889 .subvendor = 0x0070,
890 .subdevice = 0xc12a,
891 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
892 }, {
893 .subvendor = 0x0070,
894 .subdevice = 0xc1f8,
895 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
896 }, {
897 .subvendor = 0x1461,
898 .subdevice = 0xd939,
899 .card = CX23885_BOARD_AVERMEDIA_HC81R,
900 },
901 };
902 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
903
904 void cx23885_card_list(struct cx23885_dev *dev)
905 {
906 int i;
907
908 if (0 == dev->pci->subsystem_vendor &&
909 0 == dev->pci->subsystem_device) {
910 printk(KERN_INFO
911 "%s: Board has no valid PCIe Subsystem ID and can't\n"
912 "%s: be autodetected. Pass card=<n> insmod option\n"
913 "%s: to workaround that. Redirect complaints to the\n"
914 "%s: vendor of the TV card. Best regards,\n"
915 "%s: -- tux\n",
916 dev->name, dev->name, dev->name, dev->name, dev->name);
917 } else {
918 printk(KERN_INFO
919 "%s: Your board isn't known (yet) to the driver.\n"
920 "%s: Try to pick one of the existing card configs via\n"
921 "%s: card=<n> insmod option. Updating to the latest\n"
922 "%s: version might help as well.\n",
923 dev->name, dev->name, dev->name, dev->name);
924 }
925 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
926 dev->name);
927 for (i = 0; i < cx23885_bcount; i++)
928 printk(KERN_INFO "%s: card=%d -> %s\n",
929 dev->name, i, cx23885_boards[i].name);
930 }
931
932 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
933 {
934 struct tveeprom tv;
935
936 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
937 eeprom_data);
938
939 /* Make sure we support the board model */
940 switch (tv.model) {
941 case 22001:
942 /* WinTV-HVR1270 (PCIe, Retail, half height)
943 * ATSC/QAM and basic analog, IR Blast */
944 case 22009:
945 /* WinTV-HVR1210 (PCIe, Retail, half height)
946 * DVB-T and basic analog, IR Blast */
947 case 22011:
948 /* WinTV-HVR1270 (PCIe, Retail, half height)
949 * ATSC/QAM and basic analog, IR Recv */
950 case 22019:
951 /* WinTV-HVR1210 (PCIe, Retail, half height)
952 * DVB-T and basic analog, IR Recv */
953 case 22021:
954 /* WinTV-HVR1275 (PCIe, Retail, half height)
955 * ATSC/QAM and basic analog, IR Recv */
956 case 22029:
957 /* WinTV-HVR1210 (PCIe, Retail, half height)
958 * DVB-T and basic analog, IR Recv */
959 case 22101:
960 /* WinTV-HVR1270 (PCIe, Retail, full height)
961 * ATSC/QAM and basic analog, IR Blast */
962 case 22109:
963 /* WinTV-HVR1210 (PCIe, Retail, full height)
964 * DVB-T and basic analog, IR Blast */
965 case 22111:
966 /* WinTV-HVR1270 (PCIe, Retail, full height)
967 * ATSC/QAM and basic analog, IR Recv */
968 case 22119:
969 /* WinTV-HVR1210 (PCIe, Retail, full height)
970 * DVB-T and basic analog, IR Recv */
971 case 22121:
972 /* WinTV-HVR1275 (PCIe, Retail, full height)
973 * ATSC/QAM and basic analog, IR Recv */
974 case 22129:
975 /* WinTV-HVR1210 (PCIe, Retail, full height)
976 * DVB-T and basic analog, IR Recv */
977 case 71009:
978 /* WinTV-HVR1200 (PCIe, Retail, full height)
979 * DVB-T and basic analog */
980 case 71359:
981 /* WinTV-HVR1200 (PCIe, OEM, half height)
982 * DVB-T and basic analog */
983 case 71439:
984 /* WinTV-HVR1200 (PCIe, OEM, half height)
985 * DVB-T and basic analog */
986 case 71449:
987 /* WinTV-HVR1200 (PCIe, OEM, full height)
988 * DVB-T and basic analog */
989 case 71939:
990 /* WinTV-HVR1200 (PCIe, OEM, half height)
991 * DVB-T and basic analog */
992 case 71949:
993 /* WinTV-HVR1200 (PCIe, OEM, full height)
994 * DVB-T and basic analog */
995 case 71959:
996 /* WinTV-HVR1200 (PCIe, OEM, full height)
997 * DVB-T and basic analog */
998 case 71979:
999 /* WinTV-HVR1200 (PCIe, OEM, half height)
1000 * DVB-T and basic analog */
1001 case 71999:
1002 /* WinTV-HVR1200 (PCIe, OEM, full height)
1003 * DVB-T and basic analog */
1004 case 76601:
1005 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
1006 channel ATSC and MPEG2 HW Encoder */
1007 case 77001:
1008 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
1009 and Basic analog */
1010 case 77011:
1011 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
1012 and Basic analog */
1013 case 77041:
1014 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
1015 and Basic analog */
1016 case 77051:
1017 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
1018 and Basic analog */
1019 case 78011:
1020 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
1021 Dual channel ATSC and MPEG2 HW Encoder */
1022 case 78501:
1023 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1024 Dual channel ATSC and MPEG2 HW Encoder */
1025 case 78521:
1026 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1027 Dual channel ATSC and MPEG2 HW Encoder */
1028 case 78531:
1029 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
1030 Dual channel ATSC and MPEG2 HW Encoder */
1031 case 78631:
1032 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
1033 Dual channel ATSC and MPEG2 HW Encoder */
1034 case 79001:
1035 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
1036 ATSC and Basic analog */
1037 case 79101:
1038 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
1039 ATSC and Basic analog */
1040 case 79501:
1041 /* WinTV-HVR1250 (PCIe, No IR, half height,
1042 ATSC [at least] and Basic analog) */
1043 case 79561:
1044 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1045 ATSC and Basic analog */
1046 case 79571:
1047 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
1048 ATSC and Basic analog */
1049 case 79671:
1050 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1051 ATSC and Basic analog */
1052 case 80019:
1053 /* WinTV-HVR1400 (Express Card, Retail, IR,
1054 * DVB-T and Basic analog */
1055 case 81509:
1056 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
1057 * DVB-T and MPEG2 HW Encoder */
1058 case 81519:
1059 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
1060 * DVB-T and MPEG2 HW Encoder */
1061 break;
1062 case 85021:
1063 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
1064 Dual channel ATSC and MPEG2 HW Encoder */
1065 break;
1066 case 85721:
1067 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
1068 Dual channel ATSC and Basic analog */
1069 break;
1070 default:
1071 printk(KERN_WARNING "%s: warning: "
1072 "unknown hauppauge model #%d\n",
1073 dev->name, tv.model);
1074 break;
1075 }
1076
1077 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
1078 dev->name, tv.model);
1079 }
1080
1081 /* Some TBS cards require initing a chip using a bitbanged SPI attached
1082 to the cx23885 gpio's. If this chip doesn't get init'ed the demod
1083 doesn't respond to any command. */
1084 static void tbs_card_init(struct cx23885_dev *dev)
1085 {
1086 int i;
1087 const u8 buf[] = {
1088 0xe0, 0x06, 0x66, 0x33, 0x65,
1089 0x01, 0x17, 0x06, 0xde};
1090
1091 switch (dev->board) {
1092 case CX23885_BOARD_TBS_6980:
1093 case CX23885_BOARD_TBS_6981:
1094 cx_set(GP0_IO, 0x00070007);
1095 usleep_range(1000, 10000);
1096 cx_clear(GP0_IO, 2);
1097 usleep_range(1000, 10000);
1098 for (i = 0; i < 9 * 8; i++) {
1099 cx_clear(GP0_IO, 7);
1100 usleep_range(1000, 10000);
1101 cx_set(GP0_IO,
1102 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4);
1103 usleep_range(1000, 10000);
1104 }
1105 cx_set(GP0_IO, 7);
1106 break;
1107 }
1108 }
1109
1110 int cx23885_tuner_callback(void *priv, int component, int command, int arg)
1111 {
1112 struct cx23885_tsport *port = priv;
1113 struct cx23885_dev *dev = port->dev;
1114 u32 bitmask = 0;
1115
1116 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
1117 return 0;
1118
1119 if (command != 0) {
1120 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
1121 __func__, command);
1122 return -EINVAL;
1123 }
1124
1125 switch (dev->board) {
1126 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1127 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1128 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1129 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1130 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1131 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1132 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1133 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1134 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1135 /* Tuner Reset Command */
1136 bitmask = 0x04;
1137 break;
1138 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1139 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1140 /* Two identical tuners on two different i2c buses,
1141 * we need to reset the correct gpio. */
1142 if (port->nr == 1)
1143 bitmask = 0x01;
1144 else if (port->nr == 2)
1145 bitmask = 0x04;
1146 break;
1147 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1148 /* Tuner Reset Command */
1149 bitmask = 0x02;
1150 break;
1151 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1152 altera_ci_tuner_reset(dev, port->nr);
1153 break;
1154 case CX23885_BOARD_AVERMEDIA_HC81R:
1155 /* XC3028L Reset Command */
1156 bitmask = 1 << 2;
1157 break;
1158 }
1159
1160 if (bitmask) {
1161 /* Drive the tuner into reset and back out */
1162 cx_clear(GP0_IO, bitmask);
1163 mdelay(200);
1164 cx_set(GP0_IO, bitmask);
1165 }
1166
1167 return 0;
1168 }
1169
1170 void cx23885_gpio_setup(struct cx23885_dev *dev)
1171 {
1172 switch (dev->board) {
1173 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1174 /* GPIO-0 cx24227 demodulator reset */
1175 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1176 break;
1177 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1178 /* GPIO-0 cx24227 demodulator */
1179 /* GPIO-2 xc3028 tuner */
1180
1181 /* Put the parts into reset */
1182 cx_set(GP0_IO, 0x00050000);
1183 cx_clear(GP0_IO, 0x00000005);
1184 msleep(5);
1185
1186 /* Bring the parts out of reset */
1187 cx_set(GP0_IO, 0x00050005);
1188 break;
1189 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1190 /* GPIO-0 cx24227 demodulator reset */
1191 /* GPIO-2 xc5000 tuner reset */
1192 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1193 break;
1194 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1195 /* GPIO-0 656_CLK */
1196 /* GPIO-1 656_D0 */
1197 /* GPIO-2 8295A Reset */
1198 /* GPIO-3-10 cx23417 data0-7 */
1199 /* GPIO-11-14 cx23417 addr0-3 */
1200 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1201 /* GPIO-19 IR_RX */
1202
1203 /* CX23417 GPIO's */
1204 /* EIO15 Zilog Reset */
1205 /* EIO14 S5H1409/CX24227 Reset */
1206 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1207
1208 /* Put the demod into reset and protect the eeprom */
1209 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1210 mdelay(100);
1211
1212 /* Bring the demod and blaster out of reset */
1213 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1214 mdelay(100);
1215
1216 /* Force the TDA8295A into reset and back */
1217 cx23885_gpio_enable(dev, GPIO_2, 1);
1218 cx23885_gpio_set(dev, GPIO_2);
1219 mdelay(20);
1220 cx23885_gpio_clear(dev, GPIO_2);
1221 mdelay(20);
1222 cx23885_gpio_set(dev, GPIO_2);
1223 mdelay(20);
1224 break;
1225 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1226 /* GPIO-0 tda10048 demodulator reset */
1227 /* GPIO-2 tda18271 tuner reset */
1228
1229 /* Put the parts into reset and back */
1230 cx_set(GP0_IO, 0x00050000);
1231 mdelay(20);
1232 cx_clear(GP0_IO, 0x00000005);
1233 mdelay(20);
1234 cx_set(GP0_IO, 0x00050005);
1235 break;
1236 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1237 /* GPIO-0 TDA10048 demodulator reset */
1238 /* GPIO-2 TDA8295A Reset */
1239 /* GPIO-3-10 cx23417 data0-7 */
1240 /* GPIO-11-14 cx23417 addr0-3 */
1241 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1242
1243 /* The following GPIO's are on the interna AVCore (cx25840) */
1244 /* GPIO-19 IR_RX */
1245 /* GPIO-20 IR_TX 416/DVBT Select */
1246 /* GPIO-21 IIS DAT */
1247 /* GPIO-22 IIS WCLK */
1248 /* GPIO-23 IIS BCLK */
1249
1250 /* Put the parts into reset and back */
1251 cx_set(GP0_IO, 0x00050000);
1252 mdelay(20);
1253 cx_clear(GP0_IO, 0x00000005);
1254 mdelay(20);
1255 cx_set(GP0_IO, 0x00050005);
1256 break;
1257 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1258 /* GPIO-0 Dibcom7000p demodulator reset */
1259 /* GPIO-2 xc3028L tuner reset */
1260 /* GPIO-13 LED */
1261
1262 /* Put the parts into reset and back */
1263 cx_set(GP0_IO, 0x00050000);
1264 mdelay(20);
1265 cx_clear(GP0_IO, 0x00000005);
1266 mdelay(20);
1267 cx_set(GP0_IO, 0x00050005);
1268 break;
1269 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1270 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
1271 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
1272 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
1273 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
1274
1275 /* Put the parts into reset and back */
1276 cx_set(GP0_IO, 0x000f0000);
1277 mdelay(20);
1278 cx_clear(GP0_IO, 0x0000000f);
1279 mdelay(20);
1280 cx_set(GP0_IO, 0x000f000f);
1281 break;
1282 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1283 /* GPIO-0 portb xc3028 reset */
1284 /* GPIO-1 portb zl10353 reset */
1285 /* GPIO-2 portc xc3028 reset */
1286 /* GPIO-3 portc zl10353 reset */
1287
1288 /* Put the parts into reset and back */
1289 cx_set(GP0_IO, 0x000f0000);
1290 mdelay(20);
1291 cx_clear(GP0_IO, 0x0000000f);
1292 mdelay(20);
1293 cx_set(GP0_IO, 0x000f000f);
1294 break;
1295 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1296 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1297 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1298 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1299 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1300 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1301 /* GPIO-2 xc3028 tuner reset */
1302
1303 /* The following GPIO's are on the internal AVCore (cx25840) */
1304 /* GPIO-? zl10353 demod reset */
1305
1306 /* Put the parts into reset and back */
1307 cx_set(GP0_IO, 0x00040000);
1308 mdelay(20);
1309 cx_clear(GP0_IO, 0x00000004);
1310 mdelay(20);
1311 cx_set(GP0_IO, 0x00040004);
1312 break;
1313 case CX23885_BOARD_TBS_6920:
1314 case CX23885_BOARD_TBS_6980:
1315 case CX23885_BOARD_TBS_6981:
1316 case CX23885_BOARD_PROF_8000:
1317 cx_write(MC417_CTL, 0x00000036);
1318 cx_write(MC417_OEN, 0x00001000);
1319 cx_set(MC417_RWD, 0x00000002);
1320 mdelay(200);
1321 cx_clear(MC417_RWD, 0x00000800);
1322 mdelay(200);
1323 cx_set(MC417_RWD, 0x00000800);
1324 mdelay(200);
1325 break;
1326 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1327 /* GPIO-0 INTA from CiMax1
1328 GPIO-1 INTB from CiMax2
1329 GPIO-2 reset chips
1330 GPIO-3 to GPIO-10 data/addr for CA
1331 GPIO-11 ~CS0 to CiMax1
1332 GPIO-12 ~CS1 to CiMax2
1333 GPIO-13 ADL0 load LSB addr
1334 GPIO-14 ADL1 load MSB addr
1335 GPIO-15 ~RDY from CiMax
1336 GPIO-17 ~RD to CiMax
1337 GPIO-18 ~WR to CiMax
1338 */
1339 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1340 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1341 cx_clear(GP0_IO, 0x00030004);
1342 mdelay(100);/* reset delay */
1343 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1344 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1345 /* GPIO-15 IN as ~ACK, rest as OUT */
1346 cx_write(MC417_OEN, 0x00001000);
1347 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1348 cx_write(MC417_RWD, 0x0000c300);
1349 /* enable irq */
1350 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1351 break;
1352 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1353 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1354 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1355 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1356 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1357 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
1358 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1359 /* GPIO-9 Demod reset */
1360
1361 /* Put the parts into reset and back */
1362 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1363 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
1364 cx23885_gpio_clear(dev, GPIO_9);
1365 mdelay(20);
1366 cx23885_gpio_set(dev, GPIO_9);
1367 break;
1368 case CX23885_BOARD_MYGICA_X8506:
1369 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1370 case CX23885_BOARD_MYGICA_X8507:
1371 /* GPIO-0 (0)Analog / (1)Digital TV */
1372 /* GPIO-1 reset XC5000 */
1373 /* GPIO-2 demod reset */
1374 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1375 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
1376 mdelay(100);
1377 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
1378 mdelay(100);
1379 break;
1380 case CX23885_BOARD_MYGICA_X8558PRO:
1381 /* GPIO-0 reset first ATBM8830 */
1382 /* GPIO-1 reset second ATBM8830 */
1383 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1384 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1385 mdelay(100);
1386 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1387 mdelay(100);
1388 break;
1389 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1390 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1391 /* GPIO-0 656_CLK */
1392 /* GPIO-1 656_D0 */
1393 /* GPIO-2 Wake# */
1394 /* GPIO-3-10 cx23417 data0-7 */
1395 /* GPIO-11-14 cx23417 addr0-3 */
1396 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1397 /* GPIO-19 IR_RX */
1398 /* GPIO-20 C_IR_TX */
1399 /* GPIO-21 I2S DAT */
1400 /* GPIO-22 I2S WCLK */
1401 /* GPIO-23 I2S BCLK */
1402 /* ALT GPIO: EXP GPIO LATCH */
1403
1404 /* CX23417 GPIO's */
1405 /* GPIO-14 S5H1411/CX24228 Reset */
1406 /* GPIO-13 EEPROM write protect */
1407 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1408
1409 /* Put the demod into reset and protect the eeprom */
1410 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1411 mdelay(100);
1412
1413 /* Bring the demod out of reset */
1414 mc417_gpio_set(dev, GPIO_14);
1415 mdelay(100);
1416
1417 /* CX24228 GPIO */
1418 /* Connected to IF / Mux */
1419 break;
1420 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1421 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1422 break;
1423 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1424 /* GPIO-0 ~INT in
1425 GPIO-1 TMS out
1426 GPIO-2 ~reset chips out
1427 GPIO-3 to GPIO-10 data/addr for CA in/out
1428 GPIO-11 ~CS out
1429 GPIO-12 ADDR out
1430 GPIO-13 ~WR out
1431 GPIO-14 ~RD out
1432 GPIO-15 ~RDY in
1433 GPIO-16 TCK out
1434 GPIO-17 TDO in
1435 GPIO-18 TDI out
1436 */
1437 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1438 /* GPIO-0 as INT, reset & TMS low */
1439 cx_clear(GP0_IO, 0x00010006);
1440 mdelay(100);/* reset delay */
1441 cx_set(GP0_IO, 0x00000004); /* reset high */
1442 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1443 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1444 cx_write(MC417_OEN, 0x00005000);
1445 /* ~RD, ~WR high; ADDR low; ~CS high */
1446 cx_write(MC417_RWD, 0x00000d00);
1447 /* enable irq */
1448 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1449 break;
1450 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1451 /* GPIO-8 tda10071 demod reset */
1452
1453 /* Put the parts into reset and back */
1454 cx23885_gpio_enable(dev, GPIO_8, 1);
1455 cx23885_gpio_clear(dev, GPIO_8);
1456 mdelay(100);
1457 cx23885_gpio_set(dev, GPIO_8);
1458 mdelay(100);
1459 break;
1460 case CX23885_BOARD_AVERMEDIA_HC81R:
1461 cx_clear(MC417_CTL, 1);
1462 /* GPIO-0,1,2 setup direction as output */
1463 cx_set(GP0_IO, 0x00070000);
1464 mdelay(10);
1465 /* AF9013 demod reset */
1466 cx_set(GP0_IO, 0x00010001);
1467 mdelay(10);
1468 cx_clear(GP0_IO, 0x00010001);
1469 mdelay(10);
1470 cx_set(GP0_IO, 0x00010001);
1471 mdelay(10);
1472 /* demod tune? */
1473 cx_clear(GP0_IO, 0x00030003);
1474 mdelay(10);
1475 cx_set(GP0_IO, 0x00020002);
1476 mdelay(10);
1477 cx_set(GP0_IO, 0x00010001);
1478 mdelay(10);
1479 cx_clear(GP0_IO, 0x00020002);
1480 /* XC3028L tuner reset */
1481 cx_set(GP0_IO, 0x00040004);
1482 cx_clear(GP0_IO, 0x00040004);
1483 cx_set(GP0_IO, 0x00040004);
1484 mdelay(60);
1485 break;
1486 }
1487 }
1488
1489 int cx23885_ir_init(struct cx23885_dev *dev)
1490 {
1491 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1492 {
1493 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1494 .pin = CX23885_PIN_IR_RX_GPIO19,
1495 .function = CX23885_PAD_IR_RX,
1496 .value = 0,
1497 .strength = CX25840_PIN_DRIVE_MEDIUM,
1498 }, {
1499 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1500 .pin = CX23885_PIN_IR_TX_GPIO20,
1501 .function = CX23885_PAD_IR_TX,
1502 .value = 0,
1503 .strength = CX25840_PIN_DRIVE_MEDIUM,
1504 }
1505 };
1506 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1507
1508 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1509 {
1510 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1511 .pin = CX23885_PIN_IR_RX_GPIO19,
1512 .function = CX23885_PAD_IR_RX,
1513 .value = 0,
1514 .strength = CX25840_PIN_DRIVE_MEDIUM,
1515 }
1516 };
1517 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1518
1519 struct v4l2_subdev_ir_parameters params;
1520 int ret = 0;
1521 switch (dev->board) {
1522 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1523 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1524 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1525 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1526 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1527 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1528 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1529 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1530 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1531 /* FIXME: Implement me */
1532 break;
1533 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1534 ret = cx23888_ir_probe(dev);
1535 if (ret)
1536 break;
1537 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1538 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1539 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1540 break;
1541 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1542 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1543 ret = cx23888_ir_probe(dev);
1544 if (ret)
1545 break;
1546 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1547 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1548 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1549 /*
1550 * For these boards we need to invert the Tx output via the
1551 * IR controller to have the LED off while idle
1552 */
1553 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1554 params.enable = false;
1555 params.shutdown = false;
1556 params.invert_level = true;
1557 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1558 params.shutdown = true;
1559 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1560 break;
1561 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1562 case CX23885_BOARD_TEVII_S470:
1563 case CX23885_BOARD_MYGICA_X8507:
1564 case CX23885_BOARD_TBS_6980:
1565 case CX23885_BOARD_TBS_6981:
1566 if (!enable_885_ir)
1567 break;
1568 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1569 if (dev->sd_ir == NULL) {
1570 ret = -ENODEV;
1571 break;
1572 }
1573 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1574 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1575 break;
1576 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1577 if (!enable_885_ir)
1578 break;
1579 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1580 if (dev->sd_ir == NULL) {
1581 ret = -ENODEV;
1582 break;
1583 }
1584 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1585 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1586 break;
1587 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1588 request_module("ir-kbd-i2c");
1589 break;
1590 }
1591
1592 return ret;
1593 }
1594
1595 void cx23885_ir_fini(struct cx23885_dev *dev)
1596 {
1597 switch (dev->board) {
1598 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1599 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1600 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1601 cx23885_irq_remove(dev, PCI_MSK_IR);
1602 cx23888_ir_remove(dev);
1603 dev->sd_ir = NULL;
1604 break;
1605 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1606 case CX23885_BOARD_TEVII_S470:
1607 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1608 case CX23885_BOARD_MYGICA_X8507:
1609 case CX23885_BOARD_TBS_6980:
1610 case CX23885_BOARD_TBS_6981:
1611 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1612 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1613 dev->sd_ir = NULL;
1614 break;
1615 }
1616 }
1617
1618 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1619 {
1620 int data;
1621 int tdo = 0;
1622 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1623 /*TMS*/
1624 data = ((cx_read(GP0_IO)) & (~0x00000002));
1625 data |= (tms ? 0x00020002 : 0x00020000);
1626 cx_write(GP0_IO, data);
1627
1628 /*TDI*/
1629 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1630 data |= (tdi ? 0x00008000 : 0);
1631 cx_write(MC417_RWD, data);
1632 if (read_tdo)
1633 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1634
1635 cx_write(MC417_RWD, data | 0x00002000);
1636 udelay(1);
1637 /*TCK*/
1638 cx_write(MC417_RWD, data);
1639
1640 return tdo;
1641 }
1642
1643 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1644 {
1645 switch (dev->board) {
1646 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1647 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1648 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1649 if (dev->sd_ir)
1650 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1651 break;
1652 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1653 case CX23885_BOARD_TEVII_S470:
1654 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1655 case CX23885_BOARD_MYGICA_X8507:
1656 case CX23885_BOARD_TBS_6980:
1657 case CX23885_BOARD_TBS_6981:
1658 if (dev->sd_ir)
1659 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
1660 break;
1661 }
1662 }
1663
1664 void cx23885_card_setup(struct cx23885_dev *dev)
1665 {
1666 struct cx23885_tsport *ts1 = &dev->ts1;
1667 struct cx23885_tsport *ts2 = &dev->ts2;
1668
1669 static u8 eeprom[256];
1670
1671 if (dev->i2c_bus[0].i2c_rc == 0) {
1672 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1673 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1674 eeprom, sizeof(eeprom));
1675 }
1676
1677 switch (dev->board) {
1678 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1679 if (dev->i2c_bus[0].i2c_rc == 0) {
1680 if (eeprom[0x80] != 0x84)
1681 hauppauge_eeprom(dev, eeprom+0xc0);
1682 else
1683 hauppauge_eeprom(dev, eeprom+0x80);
1684 }
1685 break;
1686 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1687 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1688 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1689 if (dev->i2c_bus[0].i2c_rc == 0)
1690 hauppauge_eeprom(dev, eeprom+0x80);
1691 break;
1692 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1693 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1694 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1695 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1696 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1697 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1698 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1699 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1700 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1701 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1702 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1703 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1704 if (dev->i2c_bus[0].i2c_rc == 0)
1705 hauppauge_eeprom(dev, eeprom+0xc0);
1706 break;
1707 }
1708
1709 switch (dev->board) {
1710 case CX23885_BOARD_AVERMEDIA_HC81R:
1711 /* Defaults for VID B */
1712 ts1->gen_ctrl_val = 0x4; /* Parallel */
1713 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1714 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1715 /* Defaults for VID C */
1716 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1717 ts2->gen_ctrl_val = 0x10e;
1718 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1719 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1720 break;
1721 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1722 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1723 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1724 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1725 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1726 /* break omitted intentionally */
1727 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1728 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1729 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1730 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1731 break;
1732 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1733 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1734 /* Defaults for VID B - Analog encoder */
1735 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1736 ts1->gen_ctrl_val = 0x10e;
1737 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1738 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1739
1740 /* APB_TSVALERR_POL (active low)*/
1741 ts1->vld_misc_val = 0x2000;
1742 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1743 cx_write(0x130184, 0xc);
1744
1745 /* Defaults for VID C */
1746 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1747 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1748 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1749 break;
1750 case CX23885_BOARD_TBS_6920:
1751 ts1->gen_ctrl_val = 0x4; /* Parallel */
1752 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1753 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1754 break;
1755 case CX23885_BOARD_TEVII_S470:
1756 case CX23885_BOARD_TEVII_S471:
1757 case CX23885_BOARD_DVBWORLD_2005:
1758 case CX23885_BOARD_PROF_8000:
1759 ts1->gen_ctrl_val = 0x5; /* Parallel */
1760 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1761 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1762 break;
1763 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1764 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1765 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1766 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1767 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1768 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1769 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1770 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1771 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1772 break;
1773 case CX23885_BOARD_TBS_6980:
1774 case CX23885_BOARD_TBS_6981:
1775 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1776 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1777 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1778 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1779 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1780 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1781 tbs_card_init(dev);
1782 break;
1783 case CX23885_BOARD_MYGICA_X8506:
1784 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1785 case CX23885_BOARD_MYGICA_X8507:
1786 ts1->gen_ctrl_val = 0x5; /* Parallel */
1787 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1788 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1789 break;
1790 case CX23885_BOARD_MYGICA_X8558PRO:
1791 ts1->gen_ctrl_val = 0x5; /* Parallel */
1792 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1793 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1794 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1795 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1796 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1797 break;
1798 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1799 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1800 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1801 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1802 break;
1803 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1804 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1805 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1806 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1807 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1808 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1809 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1810 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1811 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1812 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1813 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1814 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1815 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1816 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1817 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1818 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1819 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1820 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1821 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1822 default:
1823 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1824 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1825 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1826 }
1827
1828 /* Certain boards support analog, or require the avcore to be
1829 * loaded, ensure this happens.
1830 */
1831 switch (dev->board) {
1832 case CX23885_BOARD_TEVII_S470:
1833 /* Currently only enabled for the integrated IR controller */
1834 if (!enable_885_ir)
1835 break;
1836 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1837 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1838 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1839 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1840 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1841 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1842 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1843 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1844 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1845 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1846 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1847 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1848 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1849 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1850 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1851 case CX23885_BOARD_MYGICA_X8506:
1852 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1853 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1854 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1855 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1856 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1857 case CX23885_BOARD_MPX885:
1858 case CX23885_BOARD_MYGICA_X8507:
1859 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1860 case CX23885_BOARD_AVERMEDIA_HC81R:
1861 case CX23885_BOARD_TBS_6980:
1862 case CX23885_BOARD_TBS_6981:
1863 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1864 &dev->i2c_bus[2].i2c_adap,
1865 "cx25840", 0x88 >> 1, NULL);
1866 if (dev->sd_cx25840) {
1867 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1868 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1869 }
1870 break;
1871 }
1872
1873 /* AUX-PLL 27MHz CLK */
1874 switch (dev->board) {
1875 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1876 netup_initialize(dev);
1877 break;
1878 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1879 int ret;
1880 const struct firmware *fw;
1881 const char *filename = "dvb-netup-altera-01.fw";
1882 char *action = "configure";
1883 static struct netup_card_info cinfo;
1884 struct altera_config netup_config = {
1885 .dev = dev,
1886 .action = action,
1887 .jtag_io = netup_jtag_io,
1888 };
1889
1890 netup_initialize(dev);
1891
1892 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1893 if (netup_card_rev)
1894 cinfo.rev = netup_card_rev;
1895
1896 switch (cinfo.rev) {
1897 case 0x4:
1898 filename = "dvb-netup-altera-04.fw";
1899 break;
1900 default:
1901 filename = "dvb-netup-altera-01.fw";
1902 break;
1903 }
1904 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
1905 cinfo.rev, filename);
1906
1907 ret = request_firmware(&fw, filename, &dev->pci->dev);
1908 if (ret != 0)
1909 printk(KERN_ERR "did not find the firmware file. (%s) "
1910 "Please see linux/Documentation/dvb/ for more details "
1911 "on firmware-problems.", filename);
1912 else
1913 altera_init(&netup_config, fw);
1914
1915 release_firmware(fw);
1916 break;
1917 }
1918 }
1919 }
1920
1921 /* ------------------------------------------------------------------ */
Linux with added FPC-III support