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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
blob05492053b473033da6da030fb1f64d7dcf2ea0ef
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/device.h>
25 #include <linux/fs.h>
26 #include <linux/kthread.h>
27 #include <linux/file.h>
28 #include <linux/suspend.h>
29
30 #include "cx23885.h"
31 #include <media/v4l2-common.h>
32
33 #include "dvb_ca_en50221.h"
34 #include "s5h1409.h"
35 #include "s5h1411.h"
36 #include "mt2131.h"
37 #include "tda8290.h"
38 #include "tda18271.h"
39 #include "lgdt330x.h"
40 #include "xc4000.h"
41 #include "xc5000.h"
42 #include "max2165.h"
43 #include "tda10048.h"
44 #include "tuner-xc2028.h"
45 #include "tuner-simple.h"
46 #include "dib7000p.h"
47 #include "dibx000_common.h"
48 #include "zl10353.h"
49 #include "stv0900.h"
50 #include "stv0900_reg.h"
51 #include "stv6110.h"
52 #include "lnbh24.h"
53 #include "cx24116.h"
54 #include "cx24117.h"
55 #include "cimax2.h"
56 #include "lgs8gxx.h"
57 #include "netup-eeprom.h"
58 #include "netup-init.h"
59 #include "lgdt3305.h"
60 #include "atbm8830.h"
61 #include "ts2020.h"
62 #include "ds3000.h"
63 #include "cx23885-f300.h"
64 #include "altera-ci.h"
65 #include "stv0367.h"
66 #include "drxk.h"
67 #include "mt2063.h"
68 #include "stv090x.h"
69 #include "stb6100.h"
70 #include "stb6100_cfg.h"
71 #include "tda10071.h"
72 #include "a8293.h"
73 #include "mb86a20s.h"
74
75 static unsigned int debug;
76
77 #define dprintk(level, fmt, arg...)\
78 do { if (debug >= level)\
79 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
80 } while (0)
81
82 /* ------------------------------------------------------------------ */
83
84 static unsigned int alt_tuner;
85 module_param(alt_tuner, int, 0644);
86 MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
87
88 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
89
90 /* ------------------------------------------------------------------ */
91
92 static int dvb_buf_setup(struct videobuf_queue *q,
93 unsigned int *count, unsigned int *size)
94 {
95 struct cx23885_tsport *port = q->priv_data;
96
97 port->ts_packet_size = 188 * 4;
98 port->ts_packet_count = 32;
99
100 *size = port->ts_packet_size * port->ts_packet_count;
101 *count = 32;
102 return 0;
103 }
104
105 static int dvb_buf_prepare(struct videobuf_queue *q,
106 struct videobuf_buffer *vb, enum v4l2_field field)
107 {
108 struct cx23885_tsport *port = q->priv_data;
109 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
110 }
111
112 static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
113 {
114 struct cx23885_tsport *port = q->priv_data;
115 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
116 }
117
118 static void dvb_buf_release(struct videobuf_queue *q,
119 struct videobuf_buffer *vb)
120 {
121 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
122 }
123
124 static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
125 {
126 struct videobuf_dvb_frontends *f;
127 struct videobuf_dvb_frontend *fe;
128
129 f = &port->frontends;
130
131 if (f->gate <= 1) /* undefined or fe0 */
132 fe = videobuf_dvb_get_frontend(f, 1);
133 else
134 fe = videobuf_dvb_get_frontend(f, f->gate);
135
136 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
137 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
138 }
139
140 static struct videobuf_queue_ops dvb_qops = {
141 .buf_setup = dvb_buf_setup,
142 .buf_prepare = dvb_buf_prepare,
143 .buf_queue = dvb_buf_queue,
144 .buf_release = dvb_buf_release,
145 };
146
147 static struct s5h1409_config hauppauge_generic_config = {
148 .demod_address = 0x32 >> 1,
149 .output_mode = S5H1409_SERIAL_OUTPUT,
150 .gpio = S5H1409_GPIO_ON,
151 .qam_if = 44000,
152 .inversion = S5H1409_INVERSION_OFF,
153 .status_mode = S5H1409_DEMODLOCKING,
154 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
155 };
156
157 static struct tda10048_config hauppauge_hvr1200_config = {
158 .demod_address = 0x10 >> 1,
159 .output_mode = TDA10048_SERIAL_OUTPUT,
160 .fwbulkwritelen = TDA10048_BULKWRITE_200,
161 .inversion = TDA10048_INVERSION_ON,
162 .dtv6_if_freq_khz = TDA10048_IF_3300,
163 .dtv7_if_freq_khz = TDA10048_IF_3800,
164 .dtv8_if_freq_khz = TDA10048_IF_4300,
165 .clk_freq_khz = TDA10048_CLK_16000,
166 };
167
168 static struct tda10048_config hauppauge_hvr1210_config = {
169 .demod_address = 0x10 >> 1,
170 .output_mode = TDA10048_SERIAL_OUTPUT,
171 .fwbulkwritelen = TDA10048_BULKWRITE_200,
172 .inversion = TDA10048_INVERSION_ON,
173 .dtv6_if_freq_khz = TDA10048_IF_3300,
174 .dtv7_if_freq_khz = TDA10048_IF_3500,
175 .dtv8_if_freq_khz = TDA10048_IF_4000,
176 .clk_freq_khz = TDA10048_CLK_16000,
177 };
178
179 static struct s5h1409_config hauppauge_ezqam_config = {
180 .demod_address = 0x32 >> 1,
181 .output_mode = S5H1409_SERIAL_OUTPUT,
182 .gpio = S5H1409_GPIO_OFF,
183 .qam_if = 4000,
184 .inversion = S5H1409_INVERSION_ON,
185 .status_mode = S5H1409_DEMODLOCKING,
186 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
187 };
188
189 static struct s5h1409_config hauppauge_hvr1800lp_config = {
190 .demod_address = 0x32 >> 1,
191 .output_mode = S5H1409_SERIAL_OUTPUT,
192 .gpio = S5H1409_GPIO_OFF,
193 .qam_if = 44000,
194 .inversion = S5H1409_INVERSION_OFF,
195 .status_mode = S5H1409_DEMODLOCKING,
196 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
197 };
198
199 static struct s5h1409_config hauppauge_hvr1500_config = {
200 .demod_address = 0x32 >> 1,
201 .output_mode = S5H1409_SERIAL_OUTPUT,
202 .gpio = S5H1409_GPIO_OFF,
203 .inversion = S5H1409_INVERSION_OFF,
204 .status_mode = S5H1409_DEMODLOCKING,
205 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
206 };
207
208 static struct mt2131_config hauppauge_generic_tunerconfig = {
209 0x61
210 };
211
212 static struct lgdt330x_config fusionhdtv_5_express = {
213 .demod_address = 0x0e,
214 .demod_chip = LGDT3303,
215 .serial_mpeg = 0x40,
216 };
217
218 static struct s5h1409_config hauppauge_hvr1500q_config = {
219 .demod_address = 0x32 >> 1,
220 .output_mode = S5H1409_SERIAL_OUTPUT,
221 .gpio = S5H1409_GPIO_ON,
222 .qam_if = 44000,
223 .inversion = S5H1409_INVERSION_OFF,
224 .status_mode = S5H1409_DEMODLOCKING,
225 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
226 };
227
228 static struct s5h1409_config dvico_s5h1409_config = {
229 .demod_address = 0x32 >> 1,
230 .output_mode = S5H1409_SERIAL_OUTPUT,
231 .gpio = S5H1409_GPIO_ON,
232 .qam_if = 44000,
233 .inversion = S5H1409_INVERSION_OFF,
234 .status_mode = S5H1409_DEMODLOCKING,
235 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
236 };
237
238 static struct s5h1411_config dvico_s5h1411_config = {
239 .output_mode = S5H1411_SERIAL_OUTPUT,
240 .gpio = S5H1411_GPIO_ON,
241 .qam_if = S5H1411_IF_44000,
242 .vsb_if = S5H1411_IF_44000,
243 .inversion = S5H1411_INVERSION_OFF,
244 .status_mode = S5H1411_DEMODLOCKING,
245 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
246 };
247
248 static struct s5h1411_config hcw_s5h1411_config = {
249 .output_mode = S5H1411_SERIAL_OUTPUT,
250 .gpio = S5H1411_GPIO_OFF,
251 .vsb_if = S5H1411_IF_44000,
252 .qam_if = S5H1411_IF_4000,
253 .inversion = S5H1411_INVERSION_ON,
254 .status_mode = S5H1411_DEMODLOCKING,
255 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
256 };
257
258 static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
259 .i2c_address = 0x61,
260 .if_khz = 5380,
261 };
262
263 static struct xc5000_config dvico_xc5000_tunerconfig = {
264 .i2c_address = 0x64,
265 .if_khz = 5380,
266 };
267
268 static struct tda829x_config tda829x_no_probe = {
269 .probe_tuner = TDA829X_DONT_PROBE,
270 };
271
272 static struct tda18271_std_map hauppauge_tda18271_std_map = {
273 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
274 .if_lvl = 6, .rfagc_top = 0x37 },
275 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
276 .if_lvl = 6, .rfagc_top = 0x37 },
277 };
278
279 static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
280 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
281 .if_lvl = 1, .rfagc_top = 0x37, },
282 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
283 .if_lvl = 1, .rfagc_top = 0x37, },
284 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
285 .if_lvl = 1, .rfagc_top = 0x37, },
286 };
287
288 static struct tda18271_config hauppauge_tda18271_config = {
289 .std_map = &hauppauge_tda18271_std_map,
290 .gate = TDA18271_GATE_ANALOG,
291 .output_opt = TDA18271_OUTPUT_LT_OFF,
292 };
293
294 static struct tda18271_config hauppauge_hvr1200_tuner_config = {
295 .std_map = &hauppauge_hvr1200_tda18271_std_map,
296 .gate = TDA18271_GATE_ANALOG,
297 .output_opt = TDA18271_OUTPUT_LT_OFF,
298 };
299
300 static struct tda18271_config hauppauge_hvr1210_tuner_config = {
301 .gate = TDA18271_GATE_DIGITAL,
302 .output_opt = TDA18271_OUTPUT_LT_OFF,
303 };
304
305 static struct tda18271_std_map hauppauge_hvr127x_std_map = {
306 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
307 .if_lvl = 1, .rfagc_top = 0x58 },
308 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
309 .if_lvl = 1, .rfagc_top = 0x58 },
310 };
311
312 static struct tda18271_config hauppauge_hvr127x_config = {
313 .std_map = &hauppauge_hvr127x_std_map,
314 .output_opt = TDA18271_OUTPUT_LT_OFF,
315 };
316
317 static struct lgdt3305_config hauppauge_lgdt3305_config = {
318 .i2c_addr = 0x0e,
319 .mpeg_mode = LGDT3305_MPEG_SERIAL,
320 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
321 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
322 .deny_i2c_rptr = 1,
323 .spectral_inversion = 1,
324 .qam_if_khz = 4000,
325 .vsb_if_khz = 3250,
326 };
327
328 static struct dibx000_agc_config xc3028_agc_config = {
329 BAND_VHF | BAND_UHF, /* band_caps */
330
331 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
332 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
333 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
334 * P_agc_nb_est=2, P_agc_write=0
335 */
336 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
337 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
338
339 712, /* inv_gain */
340 21, /* time_stabiliz */
341
342 0, /* alpha_level */
343 118, /* thlock */
344
345 0, /* wbd_inv */
346 2867, /* wbd_ref */
347 0, /* wbd_sel */
348 2, /* wbd_alpha */
349
350 0, /* agc1_max */
351 0, /* agc1_min */
352 39718, /* agc2_max */
353 9930, /* agc2_min */
354 0, /* agc1_pt1 */
355 0, /* agc1_pt2 */
356 0, /* agc1_pt3 */
357 0, /* agc1_slope1 */
358 0, /* agc1_slope2 */
359 0, /* agc2_pt1 */
360 128, /* agc2_pt2 */
361 29, /* agc2_slope1 */
362 29, /* agc2_slope2 */
363
364 17, /* alpha_mant */
365 27, /* alpha_exp */
366 23, /* beta_mant */
367 51, /* beta_exp */
368
369 1, /* perform_agc_softsplit */
370 };
371
372 /* PLL Configuration for COFDM BW_MHz = 8.000000
373 * With external clock = 30.000000 */
374 static struct dibx000_bandwidth_config xc3028_bw_config = {
375 60000, /* internal */
376 30000, /* sampling */
377 1, /* pll_cfg: prediv */
378 8, /* pll_cfg: ratio */
379 3, /* pll_cfg: range */
380 1, /* pll_cfg: reset */
381 0, /* pll_cfg: bypass */
382 0, /* misc: refdiv */
383 0, /* misc: bypclk_div */
384 1, /* misc: IO_CLK_en_core */
385 1, /* misc: ADClkSrc */
386 0, /* misc: modulo */
387 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
388 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
389 20452225, /* timf */
390 30000000 /* xtal_hz */
391 };
392
393 static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
394 .output_mpeg2_in_188_bytes = 1,
395 .hostbus_diversity = 1,
396 .tuner_is_baseband = 0,
397 .update_lna = NULL,
398
399 .agc_config_count = 1,
400 .agc = &xc3028_agc_config,
401 .bw = &xc3028_bw_config,
402
403 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
404 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
405 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
406
407 .pwm_freq_div = 0,
408 .agc_control = NULL,
409 .spur_protect = 0,
410
411 .output_mode = OUTMODE_MPEG2_SERIAL,
412 };
413
414 static struct zl10353_config dvico_fusionhdtv_xc3028 = {
415 .demod_address = 0x0f,
416 .if2 = 45600,
417 .no_tuner = 1,
418 .disable_i2c_gate_ctrl = 1,
419 };
420
421 static struct stv0900_reg stv0900_ts_regs[] = {
422 { R0900_TSGENERAL, 0x00 },
423 { R0900_P1_TSSPEED, 0x40 },
424 { R0900_P2_TSSPEED, 0x40 },
425 { R0900_P1_TSCFGM, 0xc0 },
426 { R0900_P2_TSCFGM, 0xc0 },
427 { R0900_P1_TSCFGH, 0xe0 },
428 { R0900_P2_TSCFGH, 0xe0 },
429 { R0900_P1_TSCFGL, 0x20 },
430 { R0900_P2_TSCFGL, 0x20 },
431 { 0xffff, 0xff }, /* terminate */
432 };
433
434 static struct stv0900_config netup_stv0900_config = {
435 .demod_address = 0x68,
436 .demod_mode = 1, /* dual */
437 .xtal = 8000000,
438 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
439 .diseqc_mode = 2,/* 2/3 PWM */
440 .ts_config_regs = stv0900_ts_regs,
441 .tun1_maddress = 0,/* 0x60 */
442 .tun2_maddress = 3,/* 0x63 */
443 .tun1_adc = 1,/* 1 Vpp */
444 .tun2_adc = 1,/* 1 Vpp */
445 };
446
447 static struct stv6110_config netup_stv6110_tunerconfig_a = {
448 .i2c_address = 0x60,
449 .mclk = 16000000,
450 .clk_div = 1,
451 .gain = 8, /* +16 dB - maximum gain */
452 };
453
454 static struct stv6110_config netup_stv6110_tunerconfig_b = {
455 .i2c_address = 0x63,
456 .mclk = 16000000,
457 .clk_div = 1,
458 .gain = 8, /* +16 dB - maximum gain */
459 };
460
461 static struct cx24116_config tbs_cx24116_config = {
462 .demod_address = 0x55,
463 };
464
465 static struct cx24117_config tbs_cx24117_config = {
466 .demod_address = 0x55,
467 };
468
469 static struct ds3000_config tevii_ds3000_config = {
470 .demod_address = 0x68,
471 };
472
473 static struct ts2020_config tevii_ts2020_config = {
474 .tuner_address = 0x60,
475 .clk_out_div = 1,
476 };
477
478 static struct cx24116_config dvbworld_cx24116_config = {
479 .demod_address = 0x05,
480 };
481
482 static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
483 .prod = LGS8GXX_PROD_LGS8GL5,
484 .demod_address = 0x19,
485 .serial_ts = 0,
486 .ts_clk_pol = 1,
487 .ts_clk_gated = 1,
488 .if_clk_freq = 30400, /* 30.4 MHz */
489 .if_freq = 5380, /* 5.38 MHz */
490 .if_neg_center = 1,
491 .ext_adc = 0,
492 .adc_signed = 0,
493 .if_neg_edge = 0,
494 };
495
496 static struct xc5000_config mygica_x8506_xc5000_config = {
497 .i2c_address = 0x61,
498 .if_khz = 5380,
499 };
500
501 static struct mb86a20s_config mygica_x8507_mb86a20s_config = {
502 .demod_address = 0x10,
503 };
504
505 static struct xc5000_config mygica_x8507_xc5000_config = {
506 .i2c_address = 0x61,
507 .if_khz = 4000,
508 };
509
510 static struct stv090x_config prof_8000_stv090x_config = {
511 .device = STV0903,
512 .demod_mode = STV090x_SINGLE,
513 .clk_mode = STV090x_CLK_EXT,
514 .xtal = 27000000,
515 .address = 0x6A,
516 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
517 .repeater_level = STV090x_RPTLEVEL_64,
518 .adc1_range = STV090x_ADC_2Vpp,
519 .diseqc_envelope_mode = false,
520
521 .tuner_get_frequency = stb6100_get_frequency,
522 .tuner_set_frequency = stb6100_set_frequency,
523 .tuner_set_bandwidth = stb6100_set_bandwidth,
524 .tuner_get_bandwidth = stb6100_get_bandwidth,
525 };
526
527 static struct stb6100_config prof_8000_stb6100_config = {
528 .tuner_address = 0x60,
529 .refclock = 27000000,
530 };
531
532 static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
533 {
534 struct cx23885_tsport *port = fe->dvb->priv;
535 struct cx23885_dev *dev = port->dev;
536
537 if (voltage == SEC_VOLTAGE_18)
538 cx_write(MC417_RWD, 0x00001e00);
539 else if (voltage == SEC_VOLTAGE_13)
540 cx_write(MC417_RWD, 0x00001a00);
541 else
542 cx_write(MC417_RWD, 0x00001800);
543 return 0;
544 }
545
546 static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
547 {
548 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
549 struct cx23885_tsport *port = fe->dvb->priv;
550 struct cx23885_dev *dev = port->dev;
551
552 switch (dev->board) {
553 case CX23885_BOARD_HAUPPAUGE_HVR1275:
554 switch (p->modulation) {
555 case VSB_8:
556 cx23885_gpio_clear(dev, GPIO_5);
557 break;
558 case QAM_64:
559 case QAM_256:
560 default:
561 cx23885_gpio_set(dev, GPIO_5);
562 break;
563 }
564 break;
565 case CX23885_BOARD_MYGICA_X8506:
566 case CX23885_BOARD_MYGICA_X8507:
567 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
568 /* Select Digital TV */
569 cx23885_gpio_set(dev, GPIO_0);
570 break;
571 }
572
573 /* Call the real set_frontend */
574 if (port->set_frontend)
575 return port->set_frontend(fe);
576
577 return 0;
578 }
579
580 static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
581 struct dvb_frontend *fe)
582 {
583 port->set_frontend = fe->ops.set_frontend;
584 fe->ops.set_frontend = cx23885_dvb_set_frontend;
585 }
586
587 static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
588 .prod = LGS8GXX_PROD_LGS8G75,
589 .demod_address = 0x19,
590 .serial_ts = 0,
591 .ts_clk_pol = 1,
592 .ts_clk_gated = 1,
593 .if_clk_freq = 30400, /* 30.4 MHz */
594 .if_freq = 6500, /* 6.50 MHz */
595 .if_neg_center = 1,
596 .ext_adc = 0,
597 .adc_signed = 1,
598 .adc_vpp = 2, /* 1.6 Vpp */
599 .if_neg_edge = 1,
600 };
601
602 static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
603 .i2c_address = 0x61,
604 .if_khz = 6500,
605 };
606
607 static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
608 .prod = ATBM8830_PROD_8830,
609 .demod_address = 0x44,
610 .serial_ts = 0,
611 .ts_sampling_edge = 1,
612 .ts_clk_gated = 0,
613 .osc_clk_freq = 30400, /* in kHz */
614 .if_freq = 0, /* zero IF */
615 .zif_swap_iq = 1,
616 .agc_min = 0x2E,
617 .agc_max = 0xFF,
618 .agc_hold_loop = 0,
619 };
620
621 static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
622 .i2c_address = 0x60,
623 .osc_clk = 20
624 };
625
626 static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
627 .prod = ATBM8830_PROD_8830,
628 .demod_address = 0x44,
629 .serial_ts = 1,
630 .ts_sampling_edge = 1,
631 .ts_clk_gated = 0,
632 .osc_clk_freq = 30400, /* in kHz */
633 .if_freq = 0, /* zero IF */
634 .zif_swap_iq = 1,
635 .agc_min = 0x2E,
636 .agc_max = 0xFF,
637 .agc_hold_loop = 0,
638 };
639
640 static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
641 .i2c_address = 0x60,
642 .osc_clk = 20
643 };
644 static struct stv0367_config netup_stv0367_config[] = {
645 {
646 .demod_address = 0x1c,
647 .xtal = 27000000,
648 .if_khz = 4500,
649 .if_iq_mode = 0,
650 .ts_mode = 1,
651 .clk_pol = 0,
652 }, {
653 .demod_address = 0x1d,
654 .xtal = 27000000,
655 .if_khz = 4500,
656 .if_iq_mode = 0,
657 .ts_mode = 1,
658 .clk_pol = 0,
659 },
660 };
661
662 static struct xc5000_config netup_xc5000_config[] = {
663 {
664 .i2c_address = 0x61,
665 .if_khz = 4500,
666 }, {
667 .i2c_address = 0x64,
668 .if_khz = 4500,
669 },
670 };
671
672 static struct drxk_config terratec_drxk_config[] = {
673 {
674 .adr = 0x29,
675 .no_i2c_bridge = 1,
676 }, {
677 .adr = 0x2a,
678 .no_i2c_bridge = 1,
679 },
680 };
681
682 static struct mt2063_config terratec_mt2063_config[] = {
683 {
684 .tuner_address = 0x60,
685 }, {
686 .tuner_address = 0x67,
687 },
688 };
689
690 static const struct tda10071_config hauppauge_tda10071_config = {
691 .demod_i2c_addr = 0x05,
692 .tuner_i2c_addr = 0x54,
693 .i2c_wr_max = 64,
694 .ts_mode = TDA10071_TS_SERIAL,
695 .spec_inv = 0,
696 .xtal = 40444000, /* 40.444 MHz */
697 .pll_multiplier = 20,
698 };
699
700 static const struct a8293_config hauppauge_a8293_config = {
701 .i2c_addr = 0x0b,
702 };
703
704 static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
705 {
706 struct cx23885_dev *dev = (struct cx23885_dev *)device;
707 unsigned long timeout = jiffies + msecs_to_jiffies(1);
708 uint32_t mem = 0;
709
710 mem = cx_read(MC417_RWD);
711 if (read)
712 cx_set(MC417_OEN, ALT_DATA);
713 else {
714 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
715 mem &= ~ALT_DATA;
716 mem |= (data & ALT_DATA);
717 }
718
719 if (flag)
720 mem |= ALT_AD_RG;
721 else
722 mem &= ~ALT_AD_RG;
723
724 mem &= ~ALT_CS;
725 if (read)
726 mem = (mem & ~ALT_RD) | ALT_WR;
727 else
728 mem = (mem & ~ALT_WR) | ALT_RD;
729
730 cx_write(MC417_RWD, mem); /* start RW cycle */
731
732 for (;;) {
733 mem = cx_read(MC417_RWD);
734 if ((mem & ALT_RDY) == 0)
735 break;
736 if (time_after(jiffies, timeout))
737 break;
738 udelay(1);
739 }
740
741 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
742 if (read)
743 return mem & ALT_DATA;
744
745 return 0;
746 };
747
748 static int dvb_register(struct cx23885_tsport *port)
749 {
750 struct cx23885_dev *dev = port->dev;
751 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
752 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
753 int mfe_shared = 0; /* bus not shared by default */
754 int ret;
755
756 /* Get the first frontend */
757 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
758 if (!fe0)
759 return -EINVAL;
760
761 /* init struct videobuf_dvb */
762 fe0->dvb.name = dev->name;
763
764 /* multi-frontend gate control is undefined or defaults to fe0 */
765 port->frontends.gate = 0;
766
767 /* Sets the gate control callback to be used by i2c command calls */
768 port->gate_ctrl = cx23885_dvb_gate_ctrl;
769
770 /* init frontend */
771 switch (dev->board) {
772 case CX23885_BOARD_HAUPPAUGE_HVR1250:
773 i2c_bus = &dev->i2c_bus[0];
774 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
775 &hauppauge_generic_config,
776 &i2c_bus->i2c_adap);
777 if (fe0->dvb.frontend != NULL) {
778 dvb_attach(mt2131_attach, fe0->dvb.frontend,
779 &i2c_bus->i2c_adap,
780 &hauppauge_generic_tunerconfig, 0);
781 }
782 break;
783 case CX23885_BOARD_HAUPPAUGE_HVR1270:
784 case CX23885_BOARD_HAUPPAUGE_HVR1275:
785 i2c_bus = &dev->i2c_bus[0];
786 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
787 &hauppauge_lgdt3305_config,
788 &i2c_bus->i2c_adap);
789 if (fe0->dvb.frontend != NULL) {
790 dvb_attach(tda18271_attach, fe0->dvb.frontend,
791 0x60, &dev->i2c_bus[1].i2c_adap,
792 &hauppauge_hvr127x_config);
793 }
794 if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
795 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
796 break;
797 case CX23885_BOARD_HAUPPAUGE_HVR1255:
798 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
799 i2c_bus = &dev->i2c_bus[0];
800 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
801 &hcw_s5h1411_config,
802 &i2c_bus->i2c_adap);
803 if (fe0->dvb.frontend != NULL) {
804 dvb_attach(tda18271_attach, fe0->dvb.frontend,
805 0x60, &dev->i2c_bus[1].i2c_adap,
806 &hauppauge_tda18271_config);
807 }
808
809 tda18271_attach(&dev->ts1.analog_fe,
810 0x60, &dev->i2c_bus[1].i2c_adap,
811 &hauppauge_tda18271_config);
812
813 break;
814 case CX23885_BOARD_HAUPPAUGE_HVR1800:
815 i2c_bus = &dev->i2c_bus[0];
816 switch (alt_tuner) {
817 case 1:
818 fe0->dvb.frontend =
819 dvb_attach(s5h1409_attach,
820 &hauppauge_ezqam_config,
821 &i2c_bus->i2c_adap);
822 if (fe0->dvb.frontend != NULL) {
823 dvb_attach(tda829x_attach, fe0->dvb.frontend,
824 &dev->i2c_bus[1].i2c_adap, 0x42,
825 &tda829x_no_probe);
826 dvb_attach(tda18271_attach, fe0->dvb.frontend,
827 0x60, &dev->i2c_bus[1].i2c_adap,
828 &hauppauge_tda18271_config);
829 }
830 break;
831 case 0:
832 default:
833 fe0->dvb.frontend =
834 dvb_attach(s5h1409_attach,
835 &hauppauge_generic_config,
836 &i2c_bus->i2c_adap);
837 if (fe0->dvb.frontend != NULL)
838 dvb_attach(mt2131_attach, fe0->dvb.frontend,
839 &i2c_bus->i2c_adap,
840 &hauppauge_generic_tunerconfig, 0);
841 break;
842 }
843 break;
844 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
845 i2c_bus = &dev->i2c_bus[0];
846 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
847 &hauppauge_hvr1800lp_config,
848 &i2c_bus->i2c_adap);
849 if (fe0->dvb.frontend != NULL) {
850 dvb_attach(mt2131_attach, fe0->dvb.frontend,
851 &i2c_bus->i2c_adap,
852 &hauppauge_generic_tunerconfig, 0);
853 }
854 break;
855 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
856 i2c_bus = &dev->i2c_bus[0];
857 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
858 &fusionhdtv_5_express,
859 &i2c_bus->i2c_adap);
860 if (fe0->dvb.frontend != NULL) {
861 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
862 &i2c_bus->i2c_adap, 0x61,
863 TUNER_LG_TDVS_H06XF);
864 }
865 break;
866 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
867 i2c_bus = &dev->i2c_bus[1];
868 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
869 &hauppauge_hvr1500q_config,
870 &dev->i2c_bus[0].i2c_adap);
871 if (fe0->dvb.frontend != NULL)
872 dvb_attach(xc5000_attach, fe0->dvb.frontend,
873 &i2c_bus->i2c_adap,
874 &hauppauge_hvr1500q_tunerconfig);
875 break;
876 case CX23885_BOARD_HAUPPAUGE_HVR1500:
877 i2c_bus = &dev->i2c_bus[1];
878 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
879 &hauppauge_hvr1500_config,
880 &dev->i2c_bus[0].i2c_adap);
881 if (fe0->dvb.frontend != NULL) {
882 struct dvb_frontend *fe;
883 struct xc2028_config cfg = {
884 .i2c_adap = &i2c_bus->i2c_adap,
885 .i2c_addr = 0x61,
886 };
887 static struct xc2028_ctrl ctl = {
888 .fname = XC2028_DEFAULT_FIRMWARE,
889 .max_len = 64,
890 .demod = XC3028_FE_OREN538,
891 };
892
893 fe = dvb_attach(xc2028_attach,
894 fe0->dvb.frontend, &cfg);
895 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
896 fe->ops.tuner_ops.set_config(fe, &ctl);
897 }
898 break;
899 case CX23885_BOARD_HAUPPAUGE_HVR1200:
900 case CX23885_BOARD_HAUPPAUGE_HVR1700:
901 i2c_bus = &dev->i2c_bus[0];
902 fe0->dvb.frontend = dvb_attach(tda10048_attach,
903 &hauppauge_hvr1200_config,
904 &i2c_bus->i2c_adap);
905 if (fe0->dvb.frontend != NULL) {
906 dvb_attach(tda829x_attach, fe0->dvb.frontend,
907 &dev->i2c_bus[1].i2c_adap, 0x42,
908 &tda829x_no_probe);
909 dvb_attach(tda18271_attach, fe0->dvb.frontend,
910 0x60, &dev->i2c_bus[1].i2c_adap,
911 &hauppauge_hvr1200_tuner_config);
912 }
913 break;
914 case CX23885_BOARD_HAUPPAUGE_HVR1210:
915 i2c_bus = &dev->i2c_bus[0];
916 fe0->dvb.frontend = dvb_attach(tda10048_attach,
917 &hauppauge_hvr1210_config,
918 &i2c_bus->i2c_adap);
919 if (fe0->dvb.frontend != NULL) {
920 dvb_attach(tda18271_attach, fe0->dvb.frontend,
921 0x60, &dev->i2c_bus[1].i2c_adap,
922 &hauppauge_hvr1210_tuner_config);
923 }
924 break;
925 case CX23885_BOARD_HAUPPAUGE_HVR1400:
926 i2c_bus = &dev->i2c_bus[0];
927 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
928 &i2c_bus->i2c_adap,
929 0x12, &hauppauge_hvr1400_dib7000_config);
930 if (fe0->dvb.frontend != NULL) {
931 struct dvb_frontend *fe;
932 struct xc2028_config cfg = {
933 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
934 .i2c_addr = 0x64,
935 };
936 static struct xc2028_ctrl ctl = {
937 .fname = XC3028L_DEFAULT_FIRMWARE,
938 .max_len = 64,
939 .demod = XC3028_FE_DIBCOM52,
940 /* This is true for all demods with
941 v36 firmware? */
942 .type = XC2028_D2633,
943 };
944
945 fe = dvb_attach(xc2028_attach,
946 fe0->dvb.frontend, &cfg);
947 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
948 fe->ops.tuner_ops.set_config(fe, &ctl);
949 }
950 break;
951 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
952 i2c_bus = &dev->i2c_bus[port->nr - 1];
953
954 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
955 &dvico_s5h1409_config,
956 &i2c_bus->i2c_adap);
957 if (fe0->dvb.frontend == NULL)
958 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
959 &dvico_s5h1411_config,
960 &i2c_bus->i2c_adap);
961 if (fe0->dvb.frontend != NULL)
962 dvb_attach(xc5000_attach, fe0->dvb.frontend,
963 &i2c_bus->i2c_adap,
964 &dvico_xc5000_tunerconfig);
965 break;
966 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
967 i2c_bus = &dev->i2c_bus[port->nr - 1];
968
969 fe0->dvb.frontend = dvb_attach(zl10353_attach,
970 &dvico_fusionhdtv_xc3028,
971 &i2c_bus->i2c_adap);
972 if (fe0->dvb.frontend != NULL) {
973 struct dvb_frontend *fe;
974 struct xc2028_config cfg = {
975 .i2c_adap = &i2c_bus->i2c_adap,
976 .i2c_addr = 0x61,
977 };
978 static struct xc2028_ctrl ctl = {
979 .fname = XC2028_DEFAULT_FIRMWARE,
980 .max_len = 64,
981 .demod = XC3028_FE_ZARLINK456,
982 };
983
984 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
985 &cfg);
986 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
987 fe->ops.tuner_ops.set_config(fe, &ctl);
988 }
989 break;
990 }
991 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
992 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
993 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
994 i2c_bus = &dev->i2c_bus[0];
995
996 fe0->dvb.frontend = dvb_attach(zl10353_attach,
997 &dvico_fusionhdtv_xc3028,
998 &i2c_bus->i2c_adap);
999 if (fe0->dvb.frontend != NULL) {
1000 struct dvb_frontend *fe;
1001 struct xc2028_config cfg = {
1002 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
1003 .i2c_addr = 0x61,
1004 };
1005 static struct xc2028_ctrl ctl = {
1006 .fname = XC2028_DEFAULT_FIRMWARE,
1007 .max_len = 64,
1008 .demod = XC3028_FE_ZARLINK456,
1009 };
1010
1011 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
1012 &cfg);
1013 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1014 fe->ops.tuner_ops.set_config(fe, &ctl);
1015 }
1016 break;
1017 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1018 i2c_bus = &dev->i2c_bus[0];
1019
1020 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1021 &dvico_fusionhdtv_xc3028,
1022 &i2c_bus->i2c_adap);
1023 if (fe0->dvb.frontend != NULL) {
1024 struct dvb_frontend *fe;
1025 struct xc4000_config cfg = {
1026 .i2c_address = 0x61,
1027 .default_pm = 0,
1028 .dvb_amplitude = 134,
1029 .set_smoothedcvbs = 1,
1030 .if_khz = 4560
1031 };
1032
1033 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
1034 &dev->i2c_bus[1].i2c_adap, &cfg);
1035 if (!fe) {
1036 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
1037 dev->name);
1038 goto frontend_detach;
1039 }
1040 }
1041 break;
1042 case CX23885_BOARD_TBS_6920:
1043 i2c_bus = &dev->i2c_bus[1];
1044
1045 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1046 &tbs_cx24116_config,
1047 &i2c_bus->i2c_adap);
1048 if (fe0->dvb.frontend != NULL)
1049 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
1050
1051 break;
1052 case CX23885_BOARD_TBS_6980:
1053 case CX23885_BOARD_TBS_6981:
1054 i2c_bus = &dev->i2c_bus[1];
1055
1056 switch (port->nr) {
1057 /* PORT B */
1058 case 1:
1059 fe0->dvb.frontend = dvb_attach(cx24117_attach,
1060 &tbs_cx24117_config,
1061 &i2c_bus->i2c_adap);
1062 break;
1063 /* PORT C */
1064 case 2:
1065 fe0->dvb.frontend = dvb_attach(cx24117_attach,
1066 &tbs_cx24117_config,
1067 &i2c_bus->i2c_adap);
1068 break;
1069 }
1070 break;
1071 case CX23885_BOARD_TEVII_S470:
1072 i2c_bus = &dev->i2c_bus[1];
1073
1074 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1075 &tevii_ds3000_config,
1076 &i2c_bus->i2c_adap);
1077 if (fe0->dvb.frontend != NULL) {
1078 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1079 &tevii_ts2020_config, &i2c_bus->i2c_adap);
1080 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
1081 }
1082
1083 break;
1084 case CX23885_BOARD_DVBWORLD_2005:
1085 i2c_bus = &dev->i2c_bus[1];
1086
1087 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1088 &dvbworld_cx24116_config,
1089 &i2c_bus->i2c_adap);
1090 break;
1091 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1092 i2c_bus = &dev->i2c_bus[0];
1093 switch (port->nr) {
1094 /* port B */
1095 case 1:
1096 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1097 &netup_stv0900_config,
1098 &i2c_bus->i2c_adap, 0);
1099 if (fe0->dvb.frontend != NULL) {
1100 if (dvb_attach(stv6110_attach,
1101 fe0->dvb.frontend,
1102 &netup_stv6110_tunerconfig_a,
1103 &i2c_bus->i2c_adap)) {
1104 if (!dvb_attach(lnbh24_attach,
1105 fe0->dvb.frontend,
1106 &i2c_bus->i2c_adap,
1107 LNBH24_PCL | LNBH24_TTX,
1108 LNBH24_TEN, 0x09))
1109 printk(KERN_ERR
1110 "No LNBH24 found!\n");
1111
1112 }
1113 }
1114 break;
1115 /* port C */
1116 case 2:
1117 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1118 &netup_stv0900_config,
1119 &i2c_bus->i2c_adap, 1);
1120 if (fe0->dvb.frontend != NULL) {
1121 if (dvb_attach(stv6110_attach,
1122 fe0->dvb.frontend,
1123 &netup_stv6110_tunerconfig_b,
1124 &i2c_bus->i2c_adap)) {
1125 if (!dvb_attach(lnbh24_attach,
1126 fe0->dvb.frontend,
1127 &i2c_bus->i2c_adap,
1128 LNBH24_PCL | LNBH24_TTX,
1129 LNBH24_TEN, 0x0a))
1130 printk(KERN_ERR
1131 "No LNBH24 found!\n");
1132
1133 }
1134 }
1135 break;
1136 }
1137 break;
1138 case CX23885_BOARD_MYGICA_X8506:
1139 i2c_bus = &dev->i2c_bus[0];
1140 i2c_bus2 = &dev->i2c_bus[1];
1141 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1142 &mygica_x8506_lgs8gl5_config,
1143 &i2c_bus->i2c_adap);
1144 if (fe0->dvb.frontend != NULL) {
1145 dvb_attach(xc5000_attach,
1146 fe0->dvb.frontend,
1147 &i2c_bus2->i2c_adap,
1148 &mygica_x8506_xc5000_config);
1149 }
1150 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
1151 break;
1152 case CX23885_BOARD_MYGICA_X8507:
1153 i2c_bus = &dev->i2c_bus[0];
1154 i2c_bus2 = &dev->i2c_bus[1];
1155 fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
1156 &mygica_x8507_mb86a20s_config,
1157 &i2c_bus->i2c_adap);
1158 if (fe0->dvb.frontend != NULL) {
1159 dvb_attach(xc5000_attach,
1160 fe0->dvb.frontend,
1161 &i2c_bus2->i2c_adap,
1162 &mygica_x8507_xc5000_config);
1163 }
1164 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
1165 break;
1166 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1167 i2c_bus = &dev->i2c_bus[0];
1168 i2c_bus2 = &dev->i2c_bus[1];
1169 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1170 &magicpro_prohdtve2_lgs8g75_config,
1171 &i2c_bus->i2c_adap);
1172 if (fe0->dvb.frontend != NULL) {
1173 dvb_attach(xc5000_attach,
1174 fe0->dvb.frontend,
1175 &i2c_bus2->i2c_adap,
1176 &magicpro_prohdtve2_xc5000_config);
1177 }
1178 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
1179 break;
1180 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1181 i2c_bus = &dev->i2c_bus[0];
1182 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1183 &hcw_s5h1411_config,
1184 &i2c_bus->i2c_adap);
1185 if (fe0->dvb.frontend != NULL)
1186 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1187 0x60, &dev->i2c_bus[0].i2c_adap,
1188 &hauppauge_tda18271_config);
1189
1190 tda18271_attach(&dev->ts1.analog_fe,
1191 0x60, &dev->i2c_bus[1].i2c_adap,
1192 &hauppauge_tda18271_config);
1193
1194 break;
1195 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1196 i2c_bus = &dev->i2c_bus[0];
1197 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1198 &hcw_s5h1411_config,
1199 &i2c_bus->i2c_adap);
1200 if (fe0->dvb.frontend != NULL)
1201 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1202 0x60, &dev->i2c_bus[0].i2c_adap,
1203 &hauppauge_tda18271_config);
1204 break;
1205 case CX23885_BOARD_MYGICA_X8558PRO:
1206 switch (port->nr) {
1207 /* port B */
1208 case 1:
1209 i2c_bus = &dev->i2c_bus[0];
1210 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1211 &mygica_x8558pro_atbm8830_cfg1,
1212 &i2c_bus->i2c_adap);
1213 if (fe0->dvb.frontend != NULL) {
1214 dvb_attach(max2165_attach,
1215 fe0->dvb.frontend,
1216 &i2c_bus->i2c_adap,
1217 &mygic_x8558pro_max2165_cfg1);
1218 }
1219 break;
1220 /* port C */
1221 case 2:
1222 i2c_bus = &dev->i2c_bus[1];
1223 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1224 &mygica_x8558pro_atbm8830_cfg2,
1225 &i2c_bus->i2c_adap);
1226 if (fe0->dvb.frontend != NULL) {
1227 dvb_attach(max2165_attach,
1228 fe0->dvb.frontend,
1229 &i2c_bus->i2c_adap,
1230 &mygic_x8558pro_max2165_cfg2);
1231 }
1232 break;
1233 }
1234 break;
1235 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1236 i2c_bus = &dev->i2c_bus[0];
1237 mfe_shared = 1;/* MFE */
1238 port->frontends.gate = 0;/* not clear for me yet */
1239 /* ports B, C */
1240 /* MFE frontend 1 DVB-T */
1241 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1242 &netup_stv0367_config[port->nr - 1],
1243 &i2c_bus->i2c_adap);
1244 if (fe0->dvb.frontend != NULL) {
1245 if (NULL == dvb_attach(xc5000_attach,
1246 fe0->dvb.frontend,
1247 &i2c_bus->i2c_adap,
1248 &netup_xc5000_config[port->nr - 1]))
1249 goto frontend_detach;
1250 /* load xc5000 firmware */
1251 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1252 }
1253 /* MFE frontend 2 */
1254 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1255 if (fe1 == NULL)
1256 goto frontend_detach;
1257 /* DVB-C init */
1258 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1259 &netup_stv0367_config[port->nr - 1],
1260 &i2c_bus->i2c_adap);
1261 if (fe1->dvb.frontend != NULL) {
1262 fe1->dvb.frontend->id = 1;
1263 if (NULL == dvb_attach(xc5000_attach,
1264 fe1->dvb.frontend,
1265 &i2c_bus->i2c_adap,
1266 &netup_xc5000_config[port->nr - 1]))
1267 goto frontend_detach;
1268 }
1269 break;
1270 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1271 i2c_bus = &dev->i2c_bus[0];
1272 i2c_bus2 = &dev->i2c_bus[1];
1273
1274 switch (port->nr) {
1275 /* port b */
1276 case 1:
1277 fe0->dvb.frontend = dvb_attach(drxk_attach,
1278 &terratec_drxk_config[0],
1279 &i2c_bus->i2c_adap);
1280 if (fe0->dvb.frontend != NULL) {
1281 if (!dvb_attach(mt2063_attach,
1282 fe0->dvb.frontend,
1283 &terratec_mt2063_config[0],
1284 &i2c_bus2->i2c_adap))
1285 goto frontend_detach;
1286 }
1287 break;
1288 /* port c */
1289 case 2:
1290 fe0->dvb.frontend = dvb_attach(drxk_attach,
1291 &terratec_drxk_config[1],
1292 &i2c_bus->i2c_adap);
1293 if (fe0->dvb.frontend != NULL) {
1294 if (!dvb_attach(mt2063_attach,
1295 fe0->dvb.frontend,
1296 &terratec_mt2063_config[1],
1297 &i2c_bus2->i2c_adap))
1298 goto frontend_detach;
1299 }
1300 break;
1301 }
1302 break;
1303 case CX23885_BOARD_TEVII_S471:
1304 i2c_bus = &dev->i2c_bus[1];
1305
1306 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1307 &tevii_ds3000_config,
1308 &i2c_bus->i2c_adap);
1309 if (fe0->dvb.frontend != NULL) {
1310 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1311 &tevii_ts2020_config, &i2c_bus->i2c_adap);
1312 }
1313 break;
1314 case CX23885_BOARD_PROF_8000:
1315 i2c_bus = &dev->i2c_bus[0];
1316
1317 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1318 &prof_8000_stv090x_config,
1319 &i2c_bus->i2c_adap,
1320 STV090x_DEMODULATOR_0);
1321 if (fe0->dvb.frontend != NULL) {
1322 if (!dvb_attach(stb6100_attach,
1323 fe0->dvb.frontend,
1324 &prof_8000_stb6100_config,
1325 &i2c_bus->i2c_adap))
1326 goto frontend_detach;
1327
1328 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1329 }
1330 break;
1331 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1332 i2c_bus = &dev->i2c_bus[0];
1333 fe0->dvb.frontend = dvb_attach(tda10071_attach,
1334 &hauppauge_tda10071_config,
1335 &i2c_bus->i2c_adap);
1336 if (fe0->dvb.frontend != NULL) {
1337 dvb_attach(a8293_attach, fe0->dvb.frontend,
1338 &i2c_bus->i2c_adap,
1339 &hauppauge_a8293_config);
1340 }
1341 break;
1342 default:
1343 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1344 " isn't supported yet\n",
1345 dev->name);
1346 break;
1347 }
1348
1349 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
1350 printk(KERN_ERR "%s: frontend initialization failed\n",
1351 dev->name);
1352 goto frontend_detach;
1353 }
1354
1355 /* define general-purpose callback pointer */
1356 fe0->dvb.frontend->callback = cx23885_tuner_callback;
1357 if (fe1)
1358 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1359 #if 0
1360 /* Ensure all frontends negotiate bus access */
1361 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1362 if (fe1)
1363 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1364 #endif
1365
1366 /* Put the analog decoder in standby to keep it quiet */
1367 call_all(dev, core, s_power, 0);
1368
1369 if (fe0->dvb.frontend->ops.analog_ops.standby)
1370 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
1371
1372 /* register everything */
1373 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
1374 &dev->pci->dev, adapter_nr, mfe_shared);
1375 if (ret)
1376 goto frontend_detach;
1377
1378 /* init CI & MAC */
1379 switch (dev->board) {
1380 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1381 static struct netup_card_info cinfo;
1382
1383 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1384 memcpy(port->frontends.adapter.proposed_mac,
1385 cinfo.port[port->nr - 1].mac, 6);
1386 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1387 port->nr, port->frontends.adapter.proposed_mac);
1388
1389 netup_ci_init(port);
1390 break;
1391 }
1392 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1393 struct altera_ci_config netup_ci_cfg = {
1394 .dev = dev,/* magic number to identify*/
1395 .adapter = &port->frontends.adapter,/* for CI */
1396 .demux = &fe0->dvb.demux,/* for hw pid filter */
1397 .fpga_rw = netup_altera_fpga_rw,
1398 };
1399
1400 altera_ci_init(&netup_ci_cfg, port->nr);
1401 break;
1402 }
1403 case CX23885_BOARD_TEVII_S470: {
1404 u8 eeprom[256]; /* 24C02 i2c eeprom */
1405
1406 if (port->nr != 1)
1407 break;
1408
1409 /* Read entire EEPROM */
1410 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1411 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
1412 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
1413 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1414 break;
1415 }
1416 }
1417
1418 return ret;
1419
1420 frontend_detach:
1421 port->gate_ctrl = NULL;
1422 videobuf_dvb_dealloc_frontends(&port->frontends);
1423 return -EINVAL;
1424 }
1425
1426 int cx23885_dvb_register(struct cx23885_tsport *port)
1427 {
1428
1429 struct videobuf_dvb_frontend *fe0;
1430 struct cx23885_dev *dev = port->dev;
1431 int err, i;
1432
1433 /* Here we need to allocate the correct number of frontends,
1434 * as reflected in the cards struct. The reality is that currently
1435 * no cx23885 boards support this - yet. But, if we don't modify this
1436 * code then the second frontend would never be allocated (later)
1437 * and fail with error before the attach in dvb_register().
1438 * Without these changes we risk an OOPS later. The changes here
1439 * are for safety, and should provide a good foundation for the
1440 * future addition of any multi-frontend cx23885 based boards.
1441 */
1442 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1443 port->num_frontends);
1444
1445 for (i = 1; i <= port->num_frontends; i++) {
1446 if (videobuf_dvb_alloc_frontend(
1447 &port->frontends, i) == NULL) {
1448 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1449 return -ENOMEM;
1450 }
1451
1452 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1453 if (!fe0)
1454 err = -EINVAL;
1455
1456 dprintk(1, "%s\n", __func__);
1457 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
1458 dev->board,
1459 dev->name,
1460 dev->pci_bus,
1461 dev->pci_slot);
1462
1463 err = -ENODEV;
1464
1465 /* dvb stuff */
1466 /* We have to init the queue for each frontend on a port. */
1467 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1468 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1469 &dev->pci->dev, &port->slock,
1470 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
1471 sizeof(struct cx23885_buffer), port, NULL);
1472 }
1473 err = dvb_register(port);
1474 if (err != 0)
1475 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1476 __func__, err);
1477
1478 return err;
1479 }
1480
1481 int cx23885_dvb_unregister(struct cx23885_tsport *port)
1482 {
1483 struct videobuf_dvb_frontend *fe0;
1484
1485 /* FIXME: in an error condition where the we have
1486 * an expected number of frontends (attach problem)
1487 * then this might not clean up correctly, if 1
1488 * is invalid.
1489 * This comment only applies to future boards IF they
1490 * implement MFE support.
1491 */
1492 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
1493 if (fe0 && fe0->dvb.frontend)
1494 videobuf_dvb_unregister_bus(&port->frontends);
1495
1496 switch (port->dev->board) {
1497 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1498 netup_ci_exit(port);
1499 break;
1500 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1501 altera_ci_release(port->dev, port->nr);
1502 break;
1503 }
1504
1505 port->gate_ctrl = NULL;
1506
1507 return 0;
1508 }
1509
Linux with added FPC-III support