3 * device driver for Conexant 2388x based TV cards
6 * (c) 2003 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
10 * - video_ioctl2 conversion
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <linux/init.h>
29 #include <linux/list.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/kmod.h>
34 #include <linux/sound.h>
35 #include <linux/interrupt.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <linux/videodev2.h>
39 #include <linux/mutex.h>
42 #include <media/v4l2-common.h>
43 #include <media/v4l2-ioctl.h>
45 MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
46 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
47 MODULE_LICENSE("GPL");
49 /* ------------------------------------------------------------------ */
51 unsigned int cx88_core_debug
;
52 module_param_named(core_debug
, cx88_core_debug
, int, 0644);
53 MODULE_PARM_DESC(core_debug
, "enable debug messages [core]");
55 static unsigned int nicam
;
56 module_param(nicam
,int,0644);
57 MODULE_PARM_DESC(nicam
,"tv audio is nicam");
59 static unsigned int nocomb
;
60 module_param(nocomb
,int,0644);
61 MODULE_PARM_DESC(nocomb
,"disable comb filter");
63 #define dprintk(level,fmt, arg...) do { \
64 if (cx88_core_debug >= level) \
65 printk(KERN_DEBUG "%s: " fmt, core->name , ## arg); \
68 static unsigned int cx88_devcount
;
69 static LIST_HEAD(cx88_devlist
);
70 static DEFINE_MUTEX(devlist
);
72 #define NO_SYNC_LINE (-1U)
74 /* @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be
75 generated _after_ lpi lines are transferred. */
76 static __le32
* cx88_risc_field(__le32
*rp
, struct scatterlist
*sglist
,
77 unsigned int offset
, u32 sync_line
,
78 unsigned int bpl
, unsigned int padding
,
79 unsigned int lines
, unsigned int lpi
)
81 struct scatterlist
*sg
;
82 unsigned int line
,todo
,sol
;
84 /* sync instruction */
85 if (sync_line
!= NO_SYNC_LINE
)
86 *(rp
++) = cpu_to_le32(RISC_RESYNC
| sync_line
);
90 for (line
= 0; line
< lines
; line
++) {
91 while (offset
&& offset
>= sg_dma_len(sg
)) {
92 offset
-= sg_dma_len(sg
);
95 if (lpi
&& line
>0 && !(line
% lpi
))
96 sol
= RISC_SOL
| RISC_IRQ1
| RISC_CNT_INC
;
99 if (bpl
<= sg_dma_len(sg
)-offset
) {
100 /* fits into current chunk */
101 *(rp
++)=cpu_to_le32(RISC_WRITE
|sol
|RISC_EOL
|bpl
);
102 *(rp
++)=cpu_to_le32(sg_dma_address(sg
)+offset
);
105 /* scanline needs to be split */
107 *(rp
++)=cpu_to_le32(RISC_WRITE
|sol
|
108 (sg_dma_len(sg
)-offset
));
109 *(rp
++)=cpu_to_le32(sg_dma_address(sg
)+offset
);
110 todo
-= (sg_dma_len(sg
)-offset
);
113 while (todo
> sg_dma_len(sg
)) {
114 *(rp
++)=cpu_to_le32(RISC_WRITE
|
116 *(rp
++)=cpu_to_le32(sg_dma_address(sg
));
117 todo
-= sg_dma_len(sg
);
120 *(rp
++)=cpu_to_le32(RISC_WRITE
|RISC_EOL
|todo
);
121 *(rp
++)=cpu_to_le32(sg_dma_address(sg
));
130 int cx88_risc_buffer(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
131 struct scatterlist
*sglist
,
132 unsigned int top_offset
, unsigned int bottom_offset
,
133 unsigned int bpl
, unsigned int padding
, unsigned int lines
)
135 u32 instructions
,fields
;
140 if (UNSET
!= top_offset
)
142 if (UNSET
!= bottom_offset
)
145 /* estimate risc mem: worst case is one write per page border +
146 one write per scan line + syncs + jump (all 2 dwords). Padding
147 can cause next bpl to start close to a page border. First DMA
148 region may be smaller than PAGE_SIZE */
149 instructions
= fields
* (1 + ((bpl
+ padding
) * lines
) / PAGE_SIZE
+ lines
);
151 if ((rc
= btcx_riscmem_alloc(pci
,risc
,instructions
*8)) < 0)
154 /* write risc instructions */
156 if (UNSET
!= top_offset
)
157 rp
= cx88_risc_field(rp
, sglist
, top_offset
, 0,
158 bpl
, padding
, lines
, 0);
159 if (UNSET
!= bottom_offset
)
160 rp
= cx88_risc_field(rp
, sglist
, bottom_offset
, 0x200,
161 bpl
, padding
, lines
, 0);
163 /* save pointer to jmp instruction address */
165 BUG_ON((risc
->jmp
- risc
->cpu
+ 2) * sizeof (*risc
->cpu
) > risc
->size
);
169 int cx88_risc_databuffer(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
170 struct scatterlist
*sglist
, unsigned int bpl
,
171 unsigned int lines
, unsigned int lpi
)
177 /* estimate risc mem: worst case is one write per page border +
178 one write per scan line + syncs + jump (all 2 dwords). Here
179 there is no padding and no sync. First DMA region may be smaller
181 instructions
= 1 + (bpl
* lines
) / PAGE_SIZE
+ lines
;
183 if ((rc
= btcx_riscmem_alloc(pci
,risc
,instructions
*8)) < 0)
186 /* write risc instructions */
188 rp
= cx88_risc_field(rp
, sglist
, 0, NO_SYNC_LINE
, bpl
, 0, lines
, lpi
);
190 /* save pointer to jmp instruction address */
192 BUG_ON((risc
->jmp
- risc
->cpu
+ 2) * sizeof (*risc
->cpu
) > risc
->size
);
196 int cx88_risc_stopper(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
197 u32 reg
, u32 mask
, u32 value
)
202 if ((rc
= btcx_riscmem_alloc(pci
, risc
, 4*16)) < 0)
205 /* write risc instructions */
207 *(rp
++) = cpu_to_le32(RISC_WRITECR
| RISC_IRQ2
| RISC_IMM
);
208 *(rp
++) = cpu_to_le32(reg
);
209 *(rp
++) = cpu_to_le32(value
);
210 *(rp
++) = cpu_to_le32(mask
);
211 *(rp
++) = cpu_to_le32(RISC_JUMP
);
212 *(rp
++) = cpu_to_le32(risc
->dma
);
217 cx88_free_buffer(struct videobuf_queue
*q
, struct cx88_buffer
*buf
)
219 struct videobuf_dmabuf
*dma
=videobuf_to_dma(&buf
->vb
);
221 BUG_ON(in_interrupt());
222 videobuf_waiton(q
, &buf
->vb
, 0, 0);
223 videobuf_dma_unmap(q
->dev
, dma
);
224 videobuf_dma_free(dma
);
225 btcx_riscmem_free(to_pci_dev(q
->dev
), &buf
->risc
);
226 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
229 /* ------------------------------------------------------------------ */
230 /* our SRAM memory layout */
232 /* we are going to put all thr risc programs into host memory, so we
233 * can use the whole SDRAM for the DMA fifos. To simplify things, we
234 * use a static memory layout. That surely will waste memory in case
235 * we don't use all DMA channels at the same time (which will be the
236 * case most of the time). But that still gives us enough FIFO space
237 * to be able to deal with insane long pci latencies ...
239 * FIFO space allocations:
240 * channel 21 (y video) - 10.0k
241 * channel 22 (u video) - 2.0k
242 * channel 23 (v video) - 2.0k
243 * channel 24 (vbi) - 4.0k
244 * channels 25+26 (audio) - 4.0k
245 * channel 28 (mpeg) - 4.0k
246 * channel 27 (audio rds)- 3.0k
249 * Every channel has 160 bytes control data (64 bytes instruction
250 * queue and 6 CDT entries), which is close to 2k total.
253 * 0x0000 - 0x03ff CMDs / reserved
254 * 0x0400 - 0x0bff instruction queues + CDs
258 const struct sram_channel cx88_sram_channels
[] = {
260 .name
= "video y / packed",
261 .cmds_start
= 0x180040,
262 .ctrl_start
= 0x180400,
263 .cdt
= 0x180400 + 64,
264 .fifo_start
= 0x180c00,
265 .fifo_size
= 0x002800,
266 .ptr1_reg
= MO_DMA21_PTR1
,
267 .ptr2_reg
= MO_DMA21_PTR2
,
268 .cnt1_reg
= MO_DMA21_CNT1
,
269 .cnt2_reg
= MO_DMA21_CNT2
,
273 .cmds_start
= 0x180080,
274 .ctrl_start
= 0x1804a0,
275 .cdt
= 0x1804a0 + 64,
276 .fifo_start
= 0x183400,
277 .fifo_size
= 0x000800,
278 .ptr1_reg
= MO_DMA22_PTR1
,
279 .ptr2_reg
= MO_DMA22_PTR2
,
280 .cnt1_reg
= MO_DMA22_CNT1
,
281 .cnt2_reg
= MO_DMA22_CNT2
,
285 .cmds_start
= 0x1800c0,
286 .ctrl_start
= 0x180540,
287 .cdt
= 0x180540 + 64,
288 .fifo_start
= 0x183c00,
289 .fifo_size
= 0x000800,
290 .ptr1_reg
= MO_DMA23_PTR1
,
291 .ptr2_reg
= MO_DMA23_PTR2
,
292 .cnt1_reg
= MO_DMA23_CNT1
,
293 .cnt2_reg
= MO_DMA23_CNT2
,
297 .cmds_start
= 0x180100,
298 .ctrl_start
= 0x1805e0,
299 .cdt
= 0x1805e0 + 64,
300 .fifo_start
= 0x184400,
301 .fifo_size
= 0x001000,
302 .ptr1_reg
= MO_DMA24_PTR1
,
303 .ptr2_reg
= MO_DMA24_PTR2
,
304 .cnt1_reg
= MO_DMA24_CNT1
,
305 .cnt2_reg
= MO_DMA24_CNT2
,
308 .name
= "audio from",
309 .cmds_start
= 0x180140,
310 .ctrl_start
= 0x180680,
311 .cdt
= 0x180680 + 64,
312 .fifo_start
= 0x185400,
313 .fifo_size
= 0x001000,
314 .ptr1_reg
= MO_DMA25_PTR1
,
315 .ptr2_reg
= MO_DMA25_PTR2
,
316 .cnt1_reg
= MO_DMA25_CNT1
,
317 .cnt2_reg
= MO_DMA25_CNT2
,
321 .cmds_start
= 0x180180,
322 .ctrl_start
= 0x180720,
323 .cdt
= 0x180680 + 64, /* same as audio IN */
324 .fifo_start
= 0x185400, /* same as audio IN */
325 .fifo_size
= 0x001000, /* same as audio IN */
326 .ptr1_reg
= MO_DMA26_PTR1
,
327 .ptr2_reg
= MO_DMA26_PTR2
,
328 .cnt1_reg
= MO_DMA26_CNT1
,
329 .cnt2_reg
= MO_DMA26_CNT2
,
333 .cmds_start
= 0x180200,
334 .ctrl_start
= 0x1807C0,
335 .cdt
= 0x1807C0 + 64,
336 .fifo_start
= 0x186400,
337 .fifo_size
= 0x001000,
338 .ptr1_reg
= MO_DMA28_PTR1
,
339 .ptr2_reg
= MO_DMA28_PTR2
,
340 .cnt1_reg
= MO_DMA28_CNT1
,
341 .cnt2_reg
= MO_DMA28_CNT2
,
345 .cmds_start
= 0x1801C0,
346 .ctrl_start
= 0x180860,
347 .cdt
= 0x180860 + 64,
348 .fifo_start
= 0x187400,
349 .fifo_size
= 0x000C00,
350 .ptr1_reg
= MO_DMA27_PTR1
,
351 .ptr2_reg
= MO_DMA27_PTR2
,
352 .cnt1_reg
= MO_DMA27_CNT1
,
353 .cnt2_reg
= MO_DMA27_CNT2
,
357 int cx88_sram_channel_setup(struct cx88_core
*core
,
358 const struct sram_channel
*ch
,
359 unsigned int bpl
, u32 risc
)
361 unsigned int i
,lines
;
364 bpl
= (bpl
+ 7) & ~7; /* alignment */
366 lines
= ch
->fifo_size
/ bpl
;
372 for (i
= 0; i
< lines
; i
++)
373 cx_write(cdt
+ 16*i
, ch
->fifo_start
+ bpl
*i
);
376 cx_write(ch
->cmds_start
+ 0, risc
);
377 cx_write(ch
->cmds_start
+ 4, cdt
);
378 cx_write(ch
->cmds_start
+ 8, (lines
*16) >> 3);
379 cx_write(ch
->cmds_start
+ 12, ch
->ctrl_start
);
380 cx_write(ch
->cmds_start
+ 16, 64 >> 2);
381 for (i
= 20; i
< 64; i
+= 4)
382 cx_write(ch
->cmds_start
+ i
, 0);
385 cx_write(ch
->ptr1_reg
, ch
->fifo_start
);
386 cx_write(ch
->ptr2_reg
, cdt
);
387 cx_write(ch
->cnt1_reg
, (bpl
>> 3) -1);
388 cx_write(ch
->cnt2_reg
, (lines
*16) >> 3);
390 dprintk(2,"sram setup %s: bpl=%d lines=%d\n", ch
->name
, bpl
, lines
);
394 /* ------------------------------------------------------------------ */
395 /* debug helper code */
397 static int cx88_risc_decode(u32 risc
)
399 static const char * const instr
[16] = {
400 [ RISC_SYNC
>> 28 ] = "sync",
401 [ RISC_WRITE
>> 28 ] = "write",
402 [ RISC_WRITEC
>> 28 ] = "writec",
403 [ RISC_READ
>> 28 ] = "read",
404 [ RISC_READC
>> 28 ] = "readc",
405 [ RISC_JUMP
>> 28 ] = "jump",
406 [ RISC_SKIP
>> 28 ] = "skip",
407 [ RISC_WRITERM
>> 28 ] = "writerm",
408 [ RISC_WRITECM
>> 28 ] = "writecm",
409 [ RISC_WRITECR
>> 28 ] = "writecr",
411 static int const incr
[16] = {
412 [ RISC_WRITE
>> 28 ] = 2,
413 [ RISC_JUMP
>> 28 ] = 2,
414 [ RISC_WRITERM
>> 28 ] = 3,
415 [ RISC_WRITECM
>> 28 ] = 3,
416 [ RISC_WRITECR
>> 28 ] = 4,
418 static const char * const bits
[] = {
419 "12", "13", "14", "resync",
420 "cnt0", "cnt1", "18", "19",
421 "20", "21", "22", "23",
422 "irq1", "irq2", "eol", "sol",
426 printk("0x%08x [ %s", risc
,
427 instr
[risc
>> 28] ? instr
[risc
>> 28] : "INVALID");
428 for (i
= ARRAY_SIZE(bits
)-1; i
>= 0; i
--)
429 if (risc
& (1 << (i
+ 12)))
430 printk(" %s",bits
[i
]);
431 printk(" count=%d ]\n", risc
& 0xfff);
432 return incr
[risc
>> 28] ? incr
[risc
>> 28] : 1;
436 void cx88_sram_channel_dump(struct cx88_core
*core
,
437 const struct sram_channel
*ch
)
439 static const char * const name
[] = {
455 printk("%s: %s - dma channel status dump\n",
456 core
->name
,ch
->name
);
457 for (i
= 0; i
< ARRAY_SIZE(name
); i
++)
458 printk("%s: cmds: %-12s: 0x%08x\n",
460 cx_read(ch
->cmds_start
+ 4*i
));
461 for (n
= 1, i
= 0; i
< 4; i
++) {
462 risc
= cx_read(ch
->cmds_start
+ 4 * (i
+11));
463 printk("%s: risc%d: ", core
->name
, i
);
465 printk("0x%08x [ arg #%d ]\n", risc
, n
);
467 n
= cx88_risc_decode(risc
);
469 for (i
= 0; i
< 16; i
+= n
) {
470 risc
= cx_read(ch
->ctrl_start
+ 4 * i
);
471 printk("%s: iq %x: ", core
->name
, i
);
472 n
= cx88_risc_decode(risc
);
473 for (j
= 1; j
< n
; j
++) {
474 risc
= cx_read(ch
->ctrl_start
+ 4 * (i
+j
));
475 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
476 core
->name
, i
+j
, risc
, j
);
480 printk("%s: fifo: 0x%08x -> 0x%x\n",
481 core
->name
, ch
->fifo_start
, ch
->fifo_start
+ch
->fifo_size
);
482 printk("%s: ctrl: 0x%08x -> 0x%x\n",
483 core
->name
, ch
->ctrl_start
, ch
->ctrl_start
+6*16);
484 printk("%s: ptr1_reg: 0x%08x\n",
485 core
->name
,cx_read(ch
->ptr1_reg
));
486 printk("%s: ptr2_reg: 0x%08x\n",
487 core
->name
,cx_read(ch
->ptr2_reg
));
488 printk("%s: cnt1_reg: 0x%08x\n",
489 core
->name
,cx_read(ch
->cnt1_reg
));
490 printk("%s: cnt2_reg: 0x%08x\n",
491 core
->name
,cx_read(ch
->cnt2_reg
));
494 static const char *cx88_pci_irqs
[32] = {
495 "vid", "aud", "ts", "vip", "hst", "5", "6", "tm1",
496 "src_dma", "dst_dma", "risc_rd_err", "risc_wr_err",
497 "brdg_err", "src_dma_err", "dst_dma_err", "ipb_dma_err",
498 "i2c", "i2c_rack", "ir_smp", "gpio0", "gpio1"
501 void cx88_print_irqbits(const char *name
, const char *tag
, const char *strings
[],
502 int len
, u32 bits
, u32 mask
)
506 printk(KERN_DEBUG
"%s: %s [0x%x]", name
, tag
, bits
);
507 for (i
= 0; i
< len
; i
++) {
508 if (!(bits
& (1 << i
)))
511 printk(" %s", strings
[i
]);
514 if (!(mask
& (1 << i
)))
521 /* ------------------------------------------------------------------ */
523 int cx88_core_irq(struct cx88_core
*core
, u32 status
)
527 if (status
& PCI_INT_IR_SMPINT
) {
532 cx88_print_irqbits(core
->name
, "irq pci",
533 cx88_pci_irqs
, ARRAY_SIZE(cx88_pci_irqs
),
534 status
, core
->pci_irqmask
);
538 void cx88_wakeup(struct cx88_core
*core
,
539 struct cx88_dmaqueue
*q
, u32 count
)
541 struct cx88_buffer
*buf
;
544 for (bc
= 0;; bc
++) {
545 if (list_empty(&q
->active
))
547 buf
= list_entry(q
->active
.next
,
548 struct cx88_buffer
, vb
.queue
);
549 /* count comes from the hw and is is 16bit wide --
550 * this trick handles wrap-arounds correctly for
551 * up to 32767 buffers in flight... */
552 if ((s16
) (count
- buf
->count
) < 0)
554 v4l2_get_timestamp(&buf
->vb
.ts
);
555 dprintk(2,"[%p/%d] wakeup reg=%d buf=%d\n",buf
,buf
->vb
.i
,
557 buf
->vb
.state
= VIDEOBUF_DONE
;
558 list_del(&buf
->vb
.queue
);
559 wake_up(&buf
->vb
.done
);
561 if (list_empty(&q
->active
)) {
562 del_timer(&q
->timeout
);
564 mod_timer(&q
->timeout
, jiffies
+BUFFER_TIMEOUT
);
567 dprintk(2, "%s: %d buffers handled (should be 1)\n",
571 void cx88_shutdown(struct cx88_core
*core
)
573 /* disable RISC controller + IRQs */
574 cx_write(MO_DEV_CNTRL2
, 0);
576 /* stop dma transfers */
577 cx_write(MO_VID_DMACNTRL
, 0x0);
578 cx_write(MO_AUD_DMACNTRL
, 0x0);
579 cx_write(MO_TS_DMACNTRL
, 0x0);
580 cx_write(MO_VIP_DMACNTRL
, 0x0);
581 cx_write(MO_GPHST_DMACNTRL
, 0x0);
583 /* stop interrupts */
584 cx_write(MO_PCI_INTMSK
, 0x0);
585 cx_write(MO_VID_INTMSK
, 0x0);
586 cx_write(MO_AUD_INTMSK
, 0x0);
587 cx_write(MO_TS_INTMSK
, 0x0);
588 cx_write(MO_VIP_INTMSK
, 0x0);
589 cx_write(MO_GPHST_INTMSK
, 0x0);
592 cx_write(VID_CAPTURE_CONTROL
, 0);
595 int cx88_reset(struct cx88_core
*core
)
597 dprintk(1,"%s\n",__func__
);
600 /* clear irq status */
601 cx_write(MO_VID_INTSTAT
, 0xFFFFFFFF); // Clear PIV int
602 cx_write(MO_PCI_INTSTAT
, 0xFFFFFFFF); // Clear PCI int
603 cx_write(MO_INT1_STAT
, 0xFFFFFFFF); // Clear RISC int
609 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH21
], 720*4, 0);
610 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH22
], 128, 0);
611 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH23
], 128, 0);
612 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH24
], 128, 0);
613 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH25
], 128, 0);
614 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH26
], 128, 0);
615 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH28
], 188*4, 0);
616 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH27
], 128, 0);
619 cx_write(MO_INPUT_FORMAT
, ((1 << 13) | // agc enable
620 (1 << 12) | // agc gain
621 (1 << 11) | // adaptibe agc
622 (0 << 10) | // chroma agc
623 (0 << 9) | // ckillen
626 /* setup image format */
627 cx_andor(MO_COLOR_CTRL
, 0x4000, 0x4000);
629 /* setup FIFO Thresholds */
630 cx_write(MO_PDMA_STHRSH
, 0x0807);
631 cx_write(MO_PDMA_DTHRSH
, 0x0807);
633 /* fixes flashing of image */
634 cx_write(MO_AGC_SYNC_TIP1
, 0x0380000F);
635 cx_write(MO_AGC_BACK_VBI
, 0x00E00555);
637 cx_write(MO_VID_INTSTAT
, 0xFFFFFFFF); // Clear PIV int
638 cx_write(MO_PCI_INTSTAT
, 0xFFFFFFFF); // Clear PCI int
639 cx_write(MO_INT1_STAT
, 0xFFFFFFFF); // Clear RISC int
641 /* Reset on-board parts */
642 cx_write(MO_SRST_IO
, 0);
644 cx_write(MO_SRST_IO
, 1);
649 /* ------------------------------------------------------------------ */
651 static inline unsigned int norm_swidth(v4l2_std_id norm
)
653 return (norm
& (V4L2_STD_MN
& ~V4L2_STD_PAL_Nc
)) ? 754 : 922;
656 static inline unsigned int norm_hdelay(v4l2_std_id norm
)
658 return (norm
& (V4L2_STD_MN
& ~V4L2_STD_PAL_Nc
)) ? 135 : 186;
661 static inline unsigned int norm_vdelay(v4l2_std_id norm
)
663 return (norm
& V4L2_STD_625_50
) ? 0x24 : 0x18;
666 static inline unsigned int norm_fsc8(v4l2_std_id norm
)
668 if (norm
& V4L2_STD_PAL_M
)
669 return 28604892; // 3.575611 MHz
671 if (norm
& (V4L2_STD_PAL_Nc
))
672 return 28656448; // 3.582056 MHz
674 if (norm
& V4L2_STD_NTSC
) // All NTSC/M and variants
675 return 28636360; // 3.57954545 MHz +/- 10 Hz
677 /* SECAM have also different sub carrier for chroma,
678 but step_db and step_dr, at cx88_set_tvnorm already handles that.
680 The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N
683 return 35468950; // 4.43361875 MHz +/- 5 Hz
686 static inline unsigned int norm_htotal(v4l2_std_id norm
)
689 unsigned int fsc4
=norm_fsc8(norm
)/2;
691 /* returns 4*FSC / vtotal / frames per seconds */
692 return (norm
& V4L2_STD_625_50
) ?
693 ((fsc4
+312)/625+12)/25 :
694 ((fsc4
+262)/525*1001+15000)/30000;
697 static inline unsigned int norm_vbipack(v4l2_std_id norm
)
699 return (norm
& V4L2_STD_625_50
) ? 511 : 400;
702 int cx88_set_scale(struct cx88_core
*core
, unsigned int width
, unsigned int height
,
703 enum v4l2_field field
)
705 unsigned int swidth
= norm_swidth(core
->tvnorm
);
706 unsigned int sheight
= norm_maxh(core
->tvnorm
);
709 dprintk(1,"set_scale: %dx%d [%s%s,%s]\n", width
, height
,
710 V4L2_FIELD_HAS_TOP(field
) ? "T" : "",
711 V4L2_FIELD_HAS_BOTTOM(field
) ? "B" : "",
712 v4l2_norm_to_name(core
->tvnorm
));
713 if (!V4L2_FIELD_HAS_BOTH(field
))
716 // recalc H delay and scale registers
717 value
= (width
* norm_hdelay(core
->tvnorm
)) / swidth
;
719 cx_write(MO_HDELAY_EVEN
, value
);
720 cx_write(MO_HDELAY_ODD
, value
);
721 dprintk(1,"set_scale: hdelay 0x%04x (width %d)\n", value
,swidth
);
723 value
= (swidth
* 4096 / width
) - 4096;
724 cx_write(MO_HSCALE_EVEN
, value
);
725 cx_write(MO_HSCALE_ODD
, value
);
726 dprintk(1,"set_scale: hscale 0x%04x\n", value
);
728 cx_write(MO_HACTIVE_EVEN
, width
);
729 cx_write(MO_HACTIVE_ODD
, width
);
730 dprintk(1,"set_scale: hactive 0x%04x\n", width
);
732 // recalc V scale Register (delay is constant)
733 cx_write(MO_VDELAY_EVEN
, norm_vdelay(core
->tvnorm
));
734 cx_write(MO_VDELAY_ODD
, norm_vdelay(core
->tvnorm
));
735 dprintk(1,"set_scale: vdelay 0x%04x\n", norm_vdelay(core
->tvnorm
));
737 value
= (0x10000 - (sheight
* 512 / height
- 512)) & 0x1fff;
738 cx_write(MO_VSCALE_EVEN
, value
);
739 cx_write(MO_VSCALE_ODD
, value
);
740 dprintk(1,"set_scale: vscale 0x%04x\n", value
);
742 cx_write(MO_VACTIVE_EVEN
, sheight
);
743 cx_write(MO_VACTIVE_ODD
, sheight
);
744 dprintk(1,"set_scale: vactive 0x%04x\n", sheight
);
748 value
|= (1 << 19); // CFILT (default)
749 if (core
->tvnorm
& V4L2_STD_SECAM
) {
753 if (INPUT(core
->input
).type
== CX88_VMUX_SVIDEO
)
754 value
|= (1 << 13) | (1 << 5);
755 if (V4L2_FIELD_INTERLACED
== field
)
756 value
|= (1 << 3); // VINT (interlaced vertical scaling)
758 value
|= (1 << 0); // 3-tap interpolation
760 value
|= (1 << 1); // 5-tap interpolation
762 value
|= (3 << 5); // disable comb filter
764 cx_andor(MO_FILTER_EVEN
, 0x7ffc7f, value
); /* preserve PEAKEN, PSEL */
765 cx_andor(MO_FILTER_ODD
, 0x7ffc7f, value
);
766 dprintk(1,"set_scale: filter 0x%04x\n", value
);
771 static const u32 xtal
= 28636363;
773 static int set_pll(struct cx88_core
*core
, int prescale
, u32 ofreq
)
775 static const u32 pre
[] = { 0, 0, 0, 3, 2, 1 };
785 pll
= ofreq
* 8 * prescale
* (u64
)(1 << 20);
787 reg
= (pll
& 0x3ffffff) | (pre
[prescale
] << 26);
788 if (((reg
>> 20) & 0x3f) < 14) {
789 printk("%s/0: pll out of range\n",core
->name
);
793 dprintk(1,"set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n",
794 reg
, cx_read(MO_PLL_REG
), ofreq
);
795 cx_write(MO_PLL_REG
, reg
);
796 for (i
= 0; i
< 100; i
++) {
797 reg
= cx_read(MO_DEVICE_STATUS
);
799 dprintk(1,"pll locked [pre=%d,ofreq=%d]\n",
803 dprintk(1,"pll not locked yet, waiting ...\n");
806 dprintk(1,"pll NOT locked [pre=%d,ofreq=%d]\n",prescale
,ofreq
);
810 int cx88_start_audio_dma(struct cx88_core
*core
)
812 /* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */
813 int bpl
= cx88_sram_channels
[SRAM_CH25
].fifo_size
/4;
815 int rds_bpl
= cx88_sram_channels
[SRAM_CH27
].fifo_size
/AUD_RDS_LINES
;
817 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */
818 if (cx_read(MO_AUD_DMACNTRL
) & 0x10)
821 /* setup fifo + format */
822 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH25
], bpl
, 0);
823 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH26
], bpl
, 0);
824 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH27
],
827 cx_write(MO_AUDD_LNGTH
, bpl
); /* fifo bpl size */
828 cx_write(MO_AUDR_LNGTH
, rds_bpl
); /* fifo bpl size */
830 /* enable Up, Down and Audio RDS fifo */
831 cx_write(MO_AUD_DMACNTRL
, 0x0007);
836 int cx88_stop_audio_dma(struct cx88_core
*core
)
838 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */
839 if (cx_read(MO_AUD_DMACNTRL
) & 0x10)
843 cx_write(MO_AUD_DMACNTRL
, 0x0000);
848 static int set_tvaudio(struct cx88_core
*core
)
850 v4l2_std_id norm
= core
->tvnorm
;
852 if (CX88_VMUX_TELEVISION
!= INPUT(core
->input
).type
&&
853 CX88_VMUX_CABLE
!= INPUT(core
->input
).type
)
856 if (V4L2_STD_PAL_BG
& norm
) {
857 core
->tvaudio
= WW_BG
;
859 } else if (V4L2_STD_PAL_DK
& norm
) {
860 core
->tvaudio
= WW_DK
;
862 } else if (V4L2_STD_PAL_I
& norm
) {
863 core
->tvaudio
= WW_I
;
865 } else if (V4L2_STD_SECAM_L
& norm
) {
866 core
->tvaudio
= WW_L
;
868 } else if ((V4L2_STD_SECAM_B
| V4L2_STD_SECAM_G
| V4L2_STD_SECAM_H
) & norm
) {
869 core
->tvaudio
= WW_BG
;
871 } else if (V4L2_STD_SECAM_DK
& norm
) {
872 core
->tvaudio
= WW_DK
;
874 } else if ((V4L2_STD_NTSC_M
& norm
) ||
875 (V4L2_STD_PAL_M
& norm
)) {
876 core
->tvaudio
= WW_BTSC
;
878 } else if (V4L2_STD_NTSC_M_JP
& norm
) {
879 core
->tvaudio
= WW_EIAJ
;
882 printk("%s/0: tvaudio support needs work for this tv norm [%s], sorry\n",
883 core
->name
, v4l2_norm_to_name(core
->tvnorm
));
884 core
->tvaudio
= WW_NONE
;
888 cx_andor(MO_AFECFG_IO
, 0x1f, 0x0);
889 cx88_set_tvaudio(core
);
890 /* cx88_set_stereo(dev,V4L2_TUNER_MODE_STEREO); */
893 This should be needed only on cx88-alsa. It seems that some cx88 chips have
894 bugs and does require DMA enabled for it to work.
896 cx88_start_audio_dma(core
);
902 int cx88_set_tvnorm(struct cx88_core
*core
, v4l2_std_id norm
)
909 u32 bdelay
,agcdelay
,htotal
;
910 u32 cxiformat
, cxoformat
;
913 fsc8
= norm_fsc8(norm
);
919 if (norm
& V4L2_STD_NTSC_M_JP
) {
920 cxiformat
= VideoFormatNTSCJapan
;
921 cxoformat
= 0x181f0008;
922 } else if (norm
& V4L2_STD_NTSC_443
) {
923 cxiformat
= VideoFormatNTSC443
;
924 cxoformat
= 0x181f0008;
925 } else if (norm
& V4L2_STD_PAL_M
) {
926 cxiformat
= VideoFormatPALM
;
927 cxoformat
= 0x1c1f0008;
928 } else if (norm
& V4L2_STD_PAL_N
) {
929 cxiformat
= VideoFormatPALN
;
930 cxoformat
= 0x1c1f0008;
931 } else if (norm
& V4L2_STD_PAL_Nc
) {
932 cxiformat
= VideoFormatPALNC
;
933 cxoformat
= 0x1c1f0008;
934 } else if (norm
& V4L2_STD_PAL_60
) {
935 cxiformat
= VideoFormatPAL60
;
936 cxoformat
= 0x181f0008;
937 } else if (norm
& V4L2_STD_NTSC
) {
938 cxiformat
= VideoFormatNTSC
;
939 cxoformat
= 0x181f0008;
940 } else if (norm
& V4L2_STD_SECAM
) {
941 step_db
= 4250000 * 8;
942 step_dr
= 4406250 * 8;
944 cxiformat
= VideoFormatSECAM
;
945 cxoformat
= 0x181f0008;
947 cxiformat
= VideoFormatPAL
;
948 cxoformat
= 0x181f0008;
951 dprintk(1,"set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n",
952 v4l2_norm_to_name(core
->tvnorm
), fsc8
, adc_clock
, vdec_clock
,
954 set_pll(core
,2,vdec_clock
);
956 dprintk(1,"set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n",
957 cxiformat
, cx_read(MO_INPUT_FORMAT
) & 0x0f);
958 /* Chroma AGC must be disabled if SECAM is used, we enable it
959 by default on PAL and NTSC */
960 cx_andor(MO_INPUT_FORMAT
, 0x40f,
961 norm
& V4L2_STD_SECAM
? cxiformat
: cxiformat
| 0x400);
963 // FIXME: as-is from DScaler
964 dprintk(1,"set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n",
965 cxoformat
, cx_read(MO_OUTPUT_FORMAT
));
966 cx_write(MO_OUTPUT_FORMAT
, cxoformat
);
968 // MO_SCONV_REG = adc clock / video dec clock * 2^17
969 tmp64
= adc_clock
* (u64
)(1 << 17);
970 do_div(tmp64
, vdec_clock
);
971 dprintk(1,"set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n",
972 (u32
)tmp64
, cx_read(MO_SCONV_REG
));
973 cx_write(MO_SCONV_REG
, (u32
)tmp64
);
975 // MO_SUB_STEP = 8 * fsc / video dec clock * 2^22
976 tmp64
= step_db
* (u64
)(1 << 22);
977 do_div(tmp64
, vdec_clock
);
978 dprintk(1,"set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n",
979 (u32
)tmp64
, cx_read(MO_SUB_STEP
));
980 cx_write(MO_SUB_STEP
, (u32
)tmp64
);
982 // MO_SUB_STEP_DR = 8 * 4406250 / video dec clock * 2^22
983 tmp64
= step_dr
* (u64
)(1 << 22);
984 do_div(tmp64
, vdec_clock
);
985 dprintk(1,"set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n",
986 (u32
)tmp64
, cx_read(MO_SUB_STEP_DR
));
987 cx_write(MO_SUB_STEP_DR
, (u32
)tmp64
);
990 bdelay
= vdec_clock
* 65 / 20000000 + 21;
991 agcdelay
= vdec_clock
* 68 / 20000000 + 15;
992 dprintk(1,"set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n",
993 (bdelay
<< 8) | agcdelay
, cx_read(MO_AGC_BURST
), bdelay
, agcdelay
);
994 cx_write(MO_AGC_BURST
, (bdelay
<< 8) | agcdelay
);
997 tmp64
= norm_htotal(norm
) * (u64
)vdec_clock
;
1000 dprintk(1,"set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n",
1001 htotal
, cx_read(MO_HTOTAL
), (u32
)tmp64
);
1002 cx_andor(MO_HTOTAL
, 0x07ff, htotal
);
1004 // vbi stuff, set vbi offset to 10 (for 20 Clk*2 pixels), this makes
1005 // the effective vbi offset ~244 samples, the same as the Bt8x8
1006 cx_write(MO_VBI_PACKET
, (10<<11) | norm_vbipack(norm
));
1008 // this is needed as well to set all tvnorm parameter
1009 cx88_set_scale(core
, 320, 240, V4L2_FIELD_INTERLACED
);
1015 call_all(core
, core
, s_std
, norm
);
1017 /* The chroma_agc control should be inaccessible if the video format is SECAM */
1018 v4l2_ctrl_grab(core
->chroma_agc
, cxiformat
== VideoFormatSECAM
);
1024 /* ------------------------------------------------------------------ */
1026 struct video_device
*cx88_vdev_init(struct cx88_core
*core
,
1027 struct pci_dev
*pci
,
1028 const struct video_device
*template_
,
1031 struct video_device
*vfd
;
1033 vfd
= video_device_alloc();
1038 * The dev pointer of v4l2_device is NULL, instead we set the
1039 * video_device dev_parent pointer to the correct PCI bus device.
1040 * This driver is a rare example where there is one v4l2_device,
1041 * but the video nodes have different parent (PCI) devices.
1043 vfd
->v4l2_dev
= &core
->v4l2_dev
;
1044 vfd
->dev_parent
= &pci
->dev
;
1045 vfd
->release
= video_device_release
;
1046 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s %s (%s)",
1047 core
->name
, type
, core
->board
.name
);
1048 set_bit(V4L2_FL_USE_FH_PRIO
, &vfd
->flags
);
1052 struct cx88_core
* cx88_core_get(struct pci_dev
*pci
)
1054 struct cx88_core
*core
;
1056 mutex_lock(&devlist
);
1057 list_for_each_entry(core
, &cx88_devlist
, devlist
) {
1058 if (pci
->bus
->number
!= core
->pci_bus
)
1060 if (PCI_SLOT(pci
->devfn
) != core
->pci_slot
)
1063 if (0 != cx88_get_resources(core
, pci
)) {
1064 mutex_unlock(&devlist
);
1067 atomic_inc(&core
->refcount
);
1068 mutex_unlock(&devlist
);
1072 core
= cx88_core_create(pci
, cx88_devcount
);
1075 list_add_tail(&core
->devlist
, &cx88_devlist
);
1078 mutex_unlock(&devlist
);
1082 void cx88_core_put(struct cx88_core
*core
, struct pci_dev
*pci
)
1084 release_mem_region(pci_resource_start(pci
,0),
1085 pci_resource_len(pci
,0));
1087 if (!atomic_dec_and_test(&core
->refcount
))
1090 mutex_lock(&devlist
);
1092 if (0 == core
->i2c_rc
) {
1094 i2c_unregister_device(core
->i2c_rtc
);
1095 i2c_del_adapter(&core
->i2c_adap
);
1097 list_del(&core
->devlist
);
1098 iounmap(core
->lmmio
);
1100 mutex_unlock(&devlist
);
1101 v4l2_ctrl_handler_free(&core
->video_hdl
);
1102 v4l2_ctrl_handler_free(&core
->audio_hdl
);
1103 v4l2_device_unregister(&core
->v4l2_dev
);
1107 /* ------------------------------------------------------------------ */
1109 EXPORT_SYMBOL(cx88_print_irqbits
);
1111 EXPORT_SYMBOL(cx88_core_irq
);
1112 EXPORT_SYMBOL(cx88_wakeup
);
1113 EXPORT_SYMBOL(cx88_reset
);
1114 EXPORT_SYMBOL(cx88_shutdown
);
1116 EXPORT_SYMBOL(cx88_risc_buffer
);
1117 EXPORT_SYMBOL(cx88_risc_databuffer
);
1118 EXPORT_SYMBOL(cx88_risc_stopper
);
1119 EXPORT_SYMBOL(cx88_free_buffer
);
1121 EXPORT_SYMBOL(cx88_sram_channels
);
1122 EXPORT_SYMBOL(cx88_sram_channel_setup
);
1123 EXPORT_SYMBOL(cx88_sram_channel_dump
);
1125 EXPORT_SYMBOL(cx88_set_tvnorm
);
1126 EXPORT_SYMBOL(cx88_set_scale
);
1128 EXPORT_SYMBOL(cx88_vdev_init
);
1129 EXPORT_SYMBOL(cx88_core_get
);
1130 EXPORT_SYMBOL(cx88_core_put
);
1132 EXPORT_SYMBOL(cx88_ir_start
);
1133 EXPORT_SYMBOL(cx88_ir_stop
);
1139 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off