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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / platform / exynos4-is / fimc-is.c
blob13a4228952e32809fdcb8903e40db6f51d187316
1 /*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 * Younghwan Joo <yhwan.joo@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
14
15 #include <linux/device.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/dma-contiguous.h>
19 #include <linux/errno.h>
20 #include <linux/firmware.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_address.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/slab.h>
31 #include <linux/types.h>
32 #include <linux/videodev2.h>
33 #include <media/v4l2-of.h>
34 #include <media/videobuf2-dma-contig.h>
35
36 #include "media-dev.h"
37 #include "fimc-is.h"
38 #include "fimc-is-command.h"
39 #include "fimc-is-errno.h"
40 #include "fimc-is-i2c.h"
41 #include "fimc-is-param.h"
42 #include "fimc-is-regs.h"
43
44
45 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
46 [ISS_CLK_PPMUISPX] = "ppmuispx",
47 [ISS_CLK_PPMUISPMX] = "ppmuispmx",
48 [ISS_CLK_LITE0] = "lite0",
49 [ISS_CLK_LITE1] = "lite1",
50 [ISS_CLK_MPLL] = "mpll",
51 [ISS_CLK_ISP] = "isp",
52 [ISS_CLK_DRC] = "drc",
53 [ISS_CLK_FD] = "fd",
54 [ISS_CLK_MCUISP] = "mcuisp",
55 [ISS_CLK_UART] = "uart",
56 [ISS_CLK_ISP_DIV0] = "ispdiv0",
57 [ISS_CLK_ISP_DIV1] = "ispdiv1",
58 [ISS_CLK_MCUISP_DIV0] = "mcuispdiv0",
59 [ISS_CLK_MCUISP_DIV1] = "mcuispdiv1",
60 [ISS_CLK_ACLK200] = "aclk200",
61 [ISS_CLK_ACLK200_DIV] = "div_aclk200",
62 [ISS_CLK_ACLK400MCUISP] = "aclk400mcuisp",
63 [ISS_CLK_ACLK400MCUISP_DIV] = "div_aclk400mcuisp",
64 };
65
66 static void fimc_is_put_clocks(struct fimc_is *is)
67 {
68 int i;
69
70 for (i = 0; i < ISS_CLKS_MAX; i++) {
71 if (IS_ERR(is->clocks[i]))
72 continue;
73 clk_put(is->clocks[i]);
74 is->clocks[i] = ERR_PTR(-EINVAL);
75 }
76 }
77
78 static int fimc_is_get_clocks(struct fimc_is *is)
79 {
80 int i, ret;
81
82 for (i = 0; i < ISS_CLKS_MAX; i++)
83 is->clocks[i] = ERR_PTR(-EINVAL);
84
85 for (i = 0; i < ISS_CLKS_MAX; i++) {
86 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
87 if (IS_ERR(is->clocks[i])) {
88 ret = PTR_ERR(is->clocks[i]);
89 goto err;
90 }
91 }
92
93 return 0;
94 err:
95 fimc_is_put_clocks(is);
96 dev_err(&is->pdev->dev, "failed to get clock: %s\n",
97 fimc_is_clocks[i]);
98 return ret;
99 }
100
101 static int fimc_is_setup_clocks(struct fimc_is *is)
102 {
103 int ret;
104
105 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
106 is->clocks[ISS_CLK_ACLK200_DIV]);
107 if (ret < 0)
108 return ret;
109
110 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
111 is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
112 if (ret < 0)
113 return ret;
114
115 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
116 if (ret < 0)
117 return ret;
118
119 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
120 if (ret < 0)
121 return ret;
122
123 ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
124 ATCLK_MCUISP_FREQUENCY);
125 if (ret < 0)
126 return ret;
127
128 return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
129 ATCLK_MCUISP_FREQUENCY);
130 }
131
132 static int fimc_is_enable_clocks(struct fimc_is *is)
133 {
134 int i, ret;
135
136 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
137 if (IS_ERR(is->clocks[i]))
138 continue;
139 ret = clk_prepare_enable(is->clocks[i]);
140 if (ret < 0) {
141 dev_err(&is->pdev->dev, "clock %s enable failed\n",
142 fimc_is_clocks[i]);
143 for (--i; i >= 0; i--)
144 clk_disable(is->clocks[i]);
145 return ret;
146 }
147 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
148 }
149 return 0;
150 }
151
152 static void fimc_is_disable_clocks(struct fimc_is *is)
153 {
154 int i;
155
156 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
157 if (!IS_ERR(is->clocks[i])) {
158 clk_disable_unprepare(is->clocks[i]);
159 pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
160 }
161 }
162 }
163
164 static int fimc_is_parse_sensor_config(struct fimc_is_sensor *sensor,
165 struct device_node *np)
166 {
167 u32 tmp = 0;
168 int ret;
169
170 np = v4l2_of_get_next_endpoint(np, NULL);
171 if (!np)
172 return -ENXIO;
173 np = v4l2_of_get_remote_port(np);
174 if (!np)
175 return -ENXIO;
176
177 /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
178 ret = of_property_read_u32(np, "reg", &tmp);
179 sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
180
181 return ret;
182 }
183
184 static int fimc_is_register_subdevs(struct fimc_is *is)
185 {
186 struct device_node *adapter, *child;
187 int ret;
188
189 ret = fimc_isp_subdev_create(&is->isp);
190 if (ret < 0)
191 return ret;
192
193 for_each_compatible_node(adapter, NULL, FIMC_IS_I2C_COMPATIBLE) {
194 if (!of_find_device_by_node(adapter)) {
195 of_node_put(adapter);
196 return -EPROBE_DEFER;
197 }
198
199 for_each_available_child_of_node(adapter, child) {
200 struct i2c_client *client;
201 struct v4l2_subdev *sd;
202
203 client = of_find_i2c_device_by_node(child);
204 if (!client)
205 goto e_retry;
206
207 sd = i2c_get_clientdata(client);
208 if (!sd)
209 goto e_retry;
210
211 /* FIXME: Add support for multiple sensors. */
212 if (WARN_ON(is->sensor))
213 continue;
214
215 is->sensor = sd_to_fimc_is_sensor(sd);
216
217 if (fimc_is_parse_sensor_config(is->sensor, child)) {
218 dev_warn(&is->pdev->dev, "DT parse error: %s\n",
219 child->full_name);
220 }
221 pr_debug("%s(): registered subdev: %p\n",
222 __func__, sd->name);
223 }
224 }
225 return 0;
226
227 e_retry:
228 of_node_put(child);
229 return -EPROBE_DEFER;
230 }
231
232 static int fimc_is_unregister_subdevs(struct fimc_is *is)
233 {
234 fimc_isp_subdev_destroy(&is->isp);
235 is->sensor = NULL;
236 return 0;
237 }
238
239 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
240 {
241 const struct firmware *fw;
242 void *buf;
243 int ret;
244
245 ret = request_firmware(&fw, file_name, &is->pdev->dev);
246 if (ret < 0) {
247 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
248 return ret;
249 }
250 buf = is->memory.vaddr + is->setfile.base;
251 memcpy(buf, fw->data, fw->size);
252 fimc_is_mem_barrier();
253 is->setfile.size = fw->size;
254
255 pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
256
257 memcpy(is->fw.setfile_info,
258 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
259 FIMC_IS_SETFILE_INFO_LEN - 1);
260
261 is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
262 is->setfile.state = 1;
263
264 pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
265 is->setfile.base, fw->size);
266
267 release_firmware(fw);
268 return ret;
269 }
270
271 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
272 {
273 unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
274
275 if (on) {
276 /* Disable watchdog */
277 mcuctl_write(0, is, REG_WDT_ISP);
278
279 /* Cortex-A5 start address setting */
280 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
281
282 /* Enable and start Cortex-A5 */
283 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
284 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
285 } else {
286 /* A5 power off */
287 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
288 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
289
290 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
291 if (timeout == 0)
292 return -ETIME;
293 timeout--;
294 udelay(1);
295 }
296 }
297
298 return 0;
299 }
300
301 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
302 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
303 unsigned int state, unsigned int timeout)
304 {
305
306 int ret = wait_event_timeout(is->irq_queue,
307 !state ^ test_bit(bit, &is->state),
308 timeout);
309 if (ret == 0) {
310 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
311 return -ETIME;
312 }
313 return 0;
314 }
315
316 int fimc_is_start_firmware(struct fimc_is *is)
317 {
318 struct device *dev = &is->pdev->dev;
319 int ret;
320
321 if (is->fw.f_w == NULL) {
322 dev_err(dev, "firmware is not loaded\n");
323 return -EINVAL;
324 }
325
326 memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
327 wmb();
328
329 ret = fimc_is_cpu_set_power(is, 1);
330 if (ret < 0)
331 return ret;
332
333 ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
334 msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
335 if (ret < 0)
336 dev_err(dev, "FIMC-IS CPU power on failed\n");
337
338 return ret;
339 }
340
341 /* Allocate working memory for the FIMC-IS CPU. */
342 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
343 {
344 struct device *dev = &is->pdev->dev;
345
346 is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
347 &is->memory.paddr, GFP_KERNEL);
348 if (is->memory.vaddr == NULL)
349 return -ENOMEM;
350
351 is->memory.size = FIMC_IS_CPU_MEM_SIZE;
352 memset(is->memory.vaddr, 0, is->memory.size);
353
354 dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
355
356 if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
357 dev_err(dev, "invalid firmware memory alignment: %#x\n",
358 (u32)is->memory.paddr);
359 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
360 is->memory.paddr);
361 return -EIO;
362 }
363
364 is->is_p_region = (struct is_region *)(is->memory.vaddr +
365 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
366
367 is->is_dma_p_region = is->memory.paddr +
368 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
369
370 is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
371 FIMC_IS_SHARED_REGION_OFFSET);
372 return 0;
373 }
374
375 static void fimc_is_free_cpu_memory(struct fimc_is *is)
376 {
377 struct device *dev = &is->pdev->dev;
378
379 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
380 is->memory.paddr);
381 }
382
383 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
384 {
385 struct fimc_is *is = context;
386 struct device *dev = &is->pdev->dev;
387 void *buf;
388 int ret;
389
390 if (fw == NULL) {
391 dev_err(dev, "firmware request failed\n");
392 return;
393 }
394 mutex_lock(&is->lock);
395
396 if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
397 dev_err(dev, "wrong firmware size: %d\n", fw->size);
398 goto done;
399 }
400
401 is->fw.size = fw->size;
402
403 ret = fimc_is_alloc_cpu_memory(is);
404 if (ret < 0) {
405 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
406 goto done;
407 }
408
409 memcpy(is->memory.vaddr, fw->data, fw->size);
410 wmb();
411
412 /* Read firmware description. */
413 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
414 memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
415 is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
416
417 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
418 memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
419 is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
420
421 is->fw.state = 1;
422
423 dev_info(dev, "loaded firmware: %s, rev. %s\n",
424 is->fw.info, is->fw.version);
425 dev_dbg(dev, "FW size: %d, paddr: %#x\n", fw->size, is->memory.paddr);
426
427 is->is_shared_region->chip_id = 0xe4412;
428 is->is_shared_region->chip_rev_no = 1;
429
430 fimc_is_mem_barrier();
431
432 /*
433 * FIXME: The firmware is not being released for now, as it is
434 * needed around for copying to the IS working memory every
435 * time before the Cortex-A5 is restarted.
436 */
437 if (is->fw.f_w)
438 release_firmware(is->fw.f_w);
439 is->fw.f_w = fw;
440 done:
441 mutex_unlock(&is->lock);
442 }
443
444 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
445 {
446 return request_firmware_nowait(THIS_MODULE,
447 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
448 GFP_KERNEL, is, fimc_is_load_firmware);
449 }
450
451 /* General IS interrupt handler */
452 static void fimc_is_general_irq_handler(struct fimc_is *is)
453 {
454 is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
455
456 switch (is->i2h_cmd.cmd) {
457 case IHC_GET_SENSOR_NUM:
458 fimc_is_hw_get_params(is, 1);
459 fimc_is_hw_wait_intmsr0_intmsd0(is);
460 fimc_is_hw_set_sensor_num(is);
461 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
462 break;
463 case IHC_SET_FACE_MARK:
464 case IHC_FRAME_DONE:
465 fimc_is_hw_get_params(is, 2);
466 break;
467 case IHC_SET_SHOT_MARK:
468 case IHC_AA_DONE:
469 case IH_REPLY_DONE:
470 fimc_is_hw_get_params(is, 3);
471 break;
472 case IH_REPLY_NOT_DONE:
473 fimc_is_hw_get_params(is, 4);
474 break;
475 case IHC_NOT_READY:
476 break;
477 default:
478 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
479 }
480
481 fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
482
483 switch (is->i2h_cmd.cmd) {
484 case IHC_GET_SENSOR_NUM:
485 fimc_is_hw_set_intgr0_gd0(is);
486 set_bit(IS_ST_A5_PWR_ON, &is->state);
487 break;
488
489 case IHC_SET_SHOT_MARK:
490 break;
491
492 case IHC_SET_FACE_MARK:
493 is->fd_header.count = is->i2h_cmd.args[0];
494 is->fd_header.index = is->i2h_cmd.args[1];
495 is->fd_header.offset = 0;
496 break;
497
498 case IHC_FRAME_DONE:
499 break;
500
501 case IHC_AA_DONE:
502 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
503 is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
504 break;
505
506 case IH_REPLY_DONE:
507 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
508
509 switch (is->i2h_cmd.args[0]) {
510 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
511 /* Get CAC margin */
512 set_bit(IS_ST_CHANGE_MODE, &is->state);
513 is->isp.cac_margin_x = is->i2h_cmd.args[1];
514 is->isp.cac_margin_y = is->i2h_cmd.args[2];
515 pr_debug("CAC margin (x,y): (%d,%d)\n",
516 is->isp.cac_margin_x, is->isp.cac_margin_y);
517 break;
518
519 case HIC_STREAM_ON:
520 clear_bit(IS_ST_STREAM_OFF, &is->state);
521 set_bit(IS_ST_STREAM_ON, &is->state);
522 break;
523
524 case HIC_STREAM_OFF:
525 clear_bit(IS_ST_STREAM_ON, &is->state);
526 set_bit(IS_ST_STREAM_OFF, &is->state);
527 break;
528
529 case HIC_SET_PARAMETER:
530 is->config[is->config_index].p_region_index[0] = 0;
531 is->config[is->config_index].p_region_index[1] = 0;
532 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
533 pr_debug("HIC_SET_PARAMETER\n");
534 break;
535
536 case HIC_GET_PARAMETER:
537 break;
538
539 case HIC_SET_TUNE:
540 break;
541
542 case HIC_GET_STATUS:
543 break;
544
545 case HIC_OPEN_SENSOR:
546 set_bit(IS_ST_OPEN_SENSOR, &is->state);
547 pr_debug("data lanes: %d, settle line: %d\n",
548 is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
549 break;
550
551 case HIC_CLOSE_SENSOR:
552 clear_bit(IS_ST_OPEN_SENSOR, &is->state);
553 is->sensor_index = 0;
554 break;
555
556 case HIC_MSG_TEST:
557 pr_debug("config MSG level completed\n");
558 break;
559
560 case HIC_POWER_DOWN:
561 clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
562 break;
563
564 case HIC_GET_SET_FILE_ADDR:
565 is->setfile.base = is->i2h_cmd.args[1];
566 set_bit(IS_ST_SETFILE_LOADED, &is->state);
567 break;
568
569 case HIC_LOAD_SET_FILE:
570 set_bit(IS_ST_SETFILE_LOADED, &is->state);
571 break;
572 }
573 break;
574
575 case IH_REPLY_NOT_DONE:
576 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
577 is->i2h_cmd.args[1],
578 fimc_is_strerr(is->i2h_cmd.args[1]));
579
580 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
581 pr_err("IS_ERROR_TIME_OUT\n");
582
583 switch (is->i2h_cmd.args[1]) {
584 case IS_ERROR_SET_PARAMETER:
585 fimc_is_mem_barrier();
586 }
587
588 switch (is->i2h_cmd.args[0]) {
589 case HIC_SET_PARAMETER:
590 is->config[is->config_index].p_region_index[0] = 0;
591 is->config[is->config_index].p_region_index[1] = 0;
592 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
593 break;
594 }
595 break;
596
597 case IHC_NOT_READY:
598 pr_err("IS control sequence error: Not Ready\n");
599 break;
600 }
601
602 wake_up(&is->irq_queue);
603 }
604
605 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
606 {
607 struct fimc_is *is = priv;
608 unsigned long flags;
609 u32 status;
610
611 spin_lock_irqsave(&is->slock, flags);
612 status = mcuctl_read(is, MCUCTL_REG_INTSR1);
613
614 if (status & (1UL << FIMC_IS_INT_GENERAL))
615 fimc_is_general_irq_handler(is);
616
617 if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
618 fimc_isp_irq_handler(is);
619
620 spin_unlock_irqrestore(&is->slock, flags);
621 return IRQ_HANDLED;
622 }
623
624 static int fimc_is_hw_open_sensor(struct fimc_is *is,
625 struct fimc_is_sensor *sensor)
626 {
627 struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
628
629 fimc_is_hw_wait_intmsr0_intmsd0(is);
630
631 soe->self_calibration_mode = 1;
632 soe->actuator_type = 0;
633 soe->mipi_lane_num = 0;
634 soe->mclk = 0;
635 soe->mipi_speed = 0;
636 soe->fast_open_sensor = 0;
637 soe->i2c_sclk = 88000000;
638
639 fimc_is_mem_barrier();
640
641 mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
642 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
643 mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
644 mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
645 mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
646
647 fimc_is_hw_set_intgr0_gd0(is);
648
649 return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
650 FIMC_IS_SENSOR_OPEN_TIMEOUT);
651 }
652
653
654 int fimc_is_hw_initialize(struct fimc_is *is)
655 {
656 const int config_ids[] = {
657 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
658 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
659 };
660 struct device *dev = &is->pdev->dev;
661 u32 prev_id;
662 int i, ret;
663
664 /* Sensor initialization. */
665 ret = fimc_is_hw_open_sensor(is, is->sensor);
666 if (ret < 0)
667 return ret;
668
669 /* Get the setfile address. */
670 fimc_is_hw_get_setfile_addr(is);
671
672 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
673 FIMC_IS_CONFIG_TIMEOUT);
674 if (ret < 0) {
675 dev_err(dev, "get setfile address timed out\n");
676 return ret;
677 }
678 pr_debug("setfile.base: %#x\n", is->setfile.base);
679
680 /* Load the setfile. */
681 fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
682 clear_bit(IS_ST_SETFILE_LOADED, &is->state);
683 fimc_is_hw_load_setfile(is);
684 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
685 FIMC_IS_CONFIG_TIMEOUT);
686 if (ret < 0) {
687 dev_err(dev, "loading setfile timed out\n");
688 return ret;
689 }
690
691 pr_debug("setfile: base: %#x, size: %d\n",
692 is->setfile.base, is->setfile.size);
693 pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
694
695 /* Check magic number. */
696 if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
697 FIMC_IS_MAGIC_NUMBER) {
698 dev_err(dev, "magic number error!\n");
699 return -EIO;
700 }
701
702 pr_debug("shared region: %#x, parameter region: %#x\n",
703 is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
704 is->is_dma_p_region);
705
706 is->setfile.sub_index = 0;
707
708 /* Stream off. */
709 fimc_is_hw_stream_off(is);
710 ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
711 FIMC_IS_CONFIG_TIMEOUT);
712 if (ret < 0) {
713 dev_err(dev, "stream off timeout\n");
714 return ret;
715 }
716
717 /* Preserve previous mode. */
718 prev_id = is->config_index;
719
720 /* Set initial parameter values. */
721 for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
722 is->config_index = config_ids[i];
723 fimc_is_set_initial_params(is);
724 ret = fimc_is_itf_s_param(is, true);
725 if (ret < 0) {
726 is->config_index = prev_id;
727 return ret;
728 }
729 }
730 is->config_index = prev_id;
731
732 set_bit(IS_ST_INIT_DONE, &is->state);
733 dev_info(dev, "initialization sequence completed (%d)\n",
734 is->config_index);
735 return 0;
736 }
737
738 static int fimc_is_log_show(struct seq_file *s, void *data)
739 {
740 struct fimc_is *is = s->private;
741 const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
742
743 if (is->memory.vaddr == NULL) {
744 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
745 return -EIO;
746 }
747
748 seq_printf(s, "%s\n", buf);
749 return 0;
750 }
751
752 static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
753 {
754 return single_open(file, fimc_is_log_show, inode->i_private);
755 }
756
757 static const struct file_operations fimc_is_debugfs_fops = {
758 .open = fimc_is_debugfs_open,
759 .read = seq_read,
760 .llseek = seq_lseek,
761 .release = single_release,
762 };
763
764 static void fimc_is_debugfs_remove(struct fimc_is *is)
765 {
766 debugfs_remove_recursive(is->debugfs_entry);
767 is->debugfs_entry = NULL;
768 }
769
770 static int fimc_is_debugfs_create(struct fimc_is *is)
771 {
772 struct dentry *dentry;
773
774 is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
775
776 dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
777 is, &fimc_is_debugfs_fops);
778 if (!dentry)
779 fimc_is_debugfs_remove(is);
780
781 return is->debugfs_entry == NULL ? -EIO : 0;
782 }
783
784 static int fimc_is_runtime_resume(struct device *dev);
785 static int fimc_is_runtime_suspend(struct device *dev);
786
787 static int fimc_is_probe(struct platform_device *pdev)
788 {
789 struct device *dev = &pdev->dev;
790 struct fimc_is *is;
791 struct resource res;
792 struct device_node *node;
793 int ret;
794
795 is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
796 if (!is)
797 return -ENOMEM;
798
799 is->pdev = pdev;
800 is->isp.pdev = pdev;
801
802 init_waitqueue_head(&is->irq_queue);
803 spin_lock_init(&is->slock);
804 mutex_init(&is->lock);
805
806 ret = of_address_to_resource(dev->of_node, 0, &res);
807 if (ret < 0)
808 return ret;
809
810 is->regs = devm_ioremap_resource(dev, &res);
811 if (IS_ERR(is->regs))
812 return PTR_ERR(is->regs);
813
814 node = of_get_child_by_name(dev->of_node, "pmu");
815 if (!node)
816 return -ENODEV;
817
818 is->pmu_regs = of_iomap(node, 0);
819 if (!is->pmu_regs)
820 return -ENOMEM;
821
822 is->irq = irq_of_parse_and_map(dev->of_node, 0);
823 if (is->irq < 0) {
824 dev_err(dev, "no irq found\n");
825 return is->irq;
826 }
827
828 ret = fimc_is_get_clocks(is);
829 if (ret < 0)
830 return ret;
831
832 platform_set_drvdata(pdev, is);
833
834 ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
835 if (ret < 0) {
836 dev_err(dev, "irq request failed\n");
837 goto err_clk;
838 }
839 pm_runtime_enable(dev);
840
841 if (!pm_runtime_enabled(dev)) {
842 ret = fimc_is_runtime_resume(dev);
843 if (ret < 0)
844 goto err_irq;
845 }
846
847 ret = pm_runtime_get_sync(dev);
848 if (ret < 0)
849 goto err_pm;
850
851 is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
852 if (IS_ERR(is->alloc_ctx)) {
853 ret = PTR_ERR(is->alloc_ctx);
854 goto err_pm;
855 }
856 /*
857 * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
858 * will be created within the subdev's registered() callback.
859 */
860 ret = fimc_is_register_subdevs(is);
861 if (ret < 0)
862 goto err_vb;
863
864 ret = fimc_is_debugfs_create(is);
865 if (ret < 0)
866 goto err_sd;
867
868 ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
869 if (ret < 0)
870 goto err_dfs;
871
872 pm_runtime_put_sync(dev);
873
874 dev_dbg(dev, "FIMC-IS registered successfully\n");
875 return 0;
876
877 err_dfs:
878 fimc_is_debugfs_remove(is);
879 err_sd:
880 fimc_is_unregister_subdevs(is);
881 err_vb:
882 vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
883 err_pm:
884 if (!pm_runtime_enabled(dev))
885 fimc_is_runtime_suspend(dev);
886 err_irq:
887 free_irq(is->irq, is);
888 err_clk:
889 fimc_is_put_clocks(is);
890 return ret;
891 }
892
893 static int fimc_is_runtime_resume(struct device *dev)
894 {
895 struct fimc_is *is = dev_get_drvdata(dev);
896 int ret;
897
898 ret = fimc_is_setup_clocks(is);
899 if (ret)
900 return ret;
901
902 return fimc_is_enable_clocks(is);
903 }
904
905 static int fimc_is_runtime_suspend(struct device *dev)
906 {
907 struct fimc_is *is = dev_get_drvdata(dev);
908
909 fimc_is_disable_clocks(is);
910 return 0;
911 }
912
913 #ifdef CONFIG_PM_SLEEP
914 static int fimc_is_resume(struct device *dev)
915 {
916 /* TODO: */
917 return 0;
918 }
919
920 static int fimc_is_suspend(struct device *dev)
921 {
922 struct fimc_is *is = dev_get_drvdata(dev);
923
924 /* TODO: */
925 if (test_bit(IS_ST_A5_PWR_ON, &is->state))
926 return -EBUSY;
927
928 return 0;
929 }
930 #endif /* CONFIG_PM_SLEEP */
931
932 static int fimc_is_remove(struct platform_device *pdev)
933 {
934 struct device *dev = &pdev->dev;
935 struct fimc_is *is = dev_get_drvdata(dev);
936
937 pm_runtime_disable(dev);
938 pm_runtime_set_suspended(dev);
939 if (!pm_runtime_status_suspended(dev))
940 fimc_is_runtime_suspend(dev);
941 free_irq(is->irq, is);
942 fimc_is_unregister_subdevs(is);
943 vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
944 fimc_is_put_clocks(is);
945 fimc_is_debugfs_remove(is);
946 if (is->fw.f_w)
947 release_firmware(is->fw.f_w);
948 fimc_is_free_cpu_memory(is);
949
950 return 0;
951 }
952
953 static const struct of_device_id fimc_is_of_match[] = {
954 { .compatible = "samsung,exynos4212-fimc-is" },
955 { /* sentinel */ },
956 };
957 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
958
959 static const struct dev_pm_ops fimc_is_pm_ops = {
960 SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
961 SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
962 NULL)
963 };
964
965 static struct platform_driver fimc_is_driver = {
966 .probe = fimc_is_probe,
967 .remove = fimc_is_remove,
968 .driver = {
969 .of_match_table = fimc_is_of_match,
970 .name = FIMC_IS_DRV_NAME,
971 .owner = THIS_MODULE,
972 .pm = &fimc_is_pm_ops,
973 }
974 };
975
976 static int fimc_is_module_init(void)
977 {
978 int ret;
979
980 ret = fimc_is_register_sensor_driver();
981 if (ret < 0)
982 return ret;
983
984 ret = fimc_is_register_i2c_driver();
985 if (ret < 0)
986 goto err_sens;
987
988 ret = platform_driver_register(&fimc_is_driver);
989 if (!ret)
990 return ret;
991
992 fimc_is_unregister_i2c_driver();
993 err_sens:
994 fimc_is_unregister_sensor_driver();
995 return ret;
996 }
997
998 static void fimc_is_module_exit(void)
999 {
1000 fimc_is_unregister_sensor_driver();
1001 fimc_is_unregister_i2c_driver();
1002 platform_driver_unregister(&fimc_is_driver);
1003 }
1004
1005 module_init(fimc_is_module_init);
1006 module_exit(fimc_is_module_exit);
1007
1008 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
1009 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
1010 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1011 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support