drivers/media/platform/omap3isp/isp.h

   1 /*
   2  * isp.h
   3  *
   4  * TI OMAP3 ISP - Core
   5  *
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  * Copyright (C) 2009 Texas Instruments, Inc.
   8  *
   9  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  *           Sakari Ailus <sakari.ailus@iki.fi>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  24  * 02110-1301 USA
  25  */
  26
  27 #ifndef OMAP3_ISP_CORE_H
  28 #define OMAP3_ISP_CORE_H
  29
  30 #include <media/omap3isp.h>
  31 #include <media/v4l2-device.h>
  32 #include <linux/clk-provider.h>
  33 #include <linux/device.h>
  34 #include <linux/io.h>
  35 #include <linux/iommu.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/wait.h>
  38
  39 #include "ispstat.h"
  40 #include "ispccdc.h"
  41 #include "ispreg.h"
  42 #include "ispresizer.h"
  43 #include "isppreview.h"
  44 #include "ispcsiphy.h"
  45 #include "ispcsi2.h"
  46 #include "ispccp2.h"
  47
  48 #define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)
  49
  50 #define ISP_TOK_TERM            0xFFFFFFFF      /*
  51                                                  * terminating token for ISP
  52                                                  * modules reg list
  53                                                  */
  54 #define to_isp_device(ptr_module)                               \
  55         container_of(ptr_module, struct isp_device, isp_##ptr_module)
  56 #define to_device(ptr_module)                                           \
  57         (to_isp_device(ptr_module)->dev)
  58
  59 enum isp_mem_resources {
  60         OMAP3_ISP_IOMEM_MAIN,
  61         OMAP3_ISP_IOMEM_CCP2,
  62         OMAP3_ISP_IOMEM_CCDC,
  63         OMAP3_ISP_IOMEM_HIST,
  64         OMAP3_ISP_IOMEM_H3A,
  65         OMAP3_ISP_IOMEM_PREV,
  66         OMAP3_ISP_IOMEM_RESZ,
  67         OMAP3_ISP_IOMEM_SBL,
  68         OMAP3_ISP_IOMEM_CSI2A_REGS1,
  69         OMAP3_ISP_IOMEM_CSIPHY2,
  70         OMAP3_ISP_IOMEM_CSI2A_REGS2,
  71         OMAP3_ISP_IOMEM_CSI2C_REGS1,
  72         OMAP3_ISP_IOMEM_CSIPHY1,
  73         OMAP3_ISP_IOMEM_CSI2C_REGS2,
  74         OMAP3_ISP_IOMEM_343X_CONTROL_CSIRXFE,
  75         OMAP3_ISP_IOMEM_3630_CONTROL_CAMERA_PHY_CTRL,
  76         OMAP3_ISP_IOMEM_LAST
  77 };
  78
  79 enum isp_sbl_resource {
  80         OMAP3_ISP_SBL_CSI1_READ         = 0x1,
  81         OMAP3_ISP_SBL_CSI1_WRITE        = 0x2,
  82         OMAP3_ISP_SBL_CSI2A_WRITE       = 0x4,
  83         OMAP3_ISP_SBL_CSI2C_WRITE       = 0x8,
  84         OMAP3_ISP_SBL_CCDC_LSC_READ     = 0x10,
  85         OMAP3_ISP_SBL_CCDC_WRITE        = 0x20,
  86         OMAP3_ISP_SBL_PREVIEW_READ      = 0x40,
  87         OMAP3_ISP_SBL_PREVIEW_WRITE     = 0x80,
  88         OMAP3_ISP_SBL_RESIZER_READ      = 0x100,
  89         OMAP3_ISP_SBL_RESIZER_WRITE     = 0x200,
  90 };
  91
  92 enum isp_subclk_resource {
  93         OMAP3_ISP_SUBCLK_CCDC           = (1 << 0),
  94         OMAP3_ISP_SUBCLK_AEWB           = (1 << 1),
  95         OMAP3_ISP_SUBCLK_AF             = (1 << 2),
  96         OMAP3_ISP_SUBCLK_HIST           = (1 << 3),
  97         OMAP3_ISP_SUBCLK_PREVIEW        = (1 << 4),
  98         OMAP3_ISP_SUBCLK_RESIZER        = (1 << 5),
  99 };
 100
 101 /* ISP: OMAP 34xx ES 1.0 */
 102 #define ISP_REVISION_1_0                0x10
 103 /* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
 104 #define ISP_REVISION_2_0                0x20
 105 /* ISP2P: OMAP 36xx */
 106 #define ISP_REVISION_15_0               0xF0
 107
 108 /*
 109  * struct isp_res_mapping - Map ISP io resources to ISP revision.
 110  * @isp_rev: ISP_REVISION_x_x
 111  * @map: bitmap for enum isp_mem_resources
 112  */
 113 struct isp_res_mapping {
 114         u32 isp_rev;
 115         u32 map;
 116 };
 117
 118 /*
 119  * struct isp_reg - Structure for ISP register values.
 120  * @reg: 32-bit Register address.
 121  * @val: 32-bit Register value.
 122  */
 123 struct isp_reg {
 124         enum isp_mem_resources mmio_range;
 125         u32 reg;
 126         u32 val;
 127 };
 128
 129 enum isp_xclk_id {
 130         ISP_XCLK_A,
 131         ISP_XCLK_B,
 132 };
 133
 134 struct isp_xclk {
 135         struct isp_device *isp;
 136         struct clk_hw hw;
 137         struct clk_lookup *lookup;
 138         struct clk *clk;
 139         enum isp_xclk_id id;
 140
 141         spinlock_t lock;        /* Protects enabled and divider */
 142         bool enabled;
 143         unsigned int divider;
 144 };
 145
 146 /*
 147  * struct isp_device - ISP device structure.
 148  * @dev: Device pointer specific to the OMAP3 ISP.
 149  * @revision: Stores current ISP module revision.
 150  * @irq_num: Currently used IRQ number.
 151  * @mmio_base: Array with kernel base addresses for ioremapped ISP register
 152  *             regions.
 153  * @mmio_base_phys: Array with physical L4 bus addresses for ISP register
 154  *                  regions.
 155  * @stat_lock: Spinlock for handling statistics
 156  * @isp_mutex: Mutex for serializing requests to ISP.
 157  * @stop_failure: Indicates that an entity failed to stop.
 158  * @crashed: Bitmask of crashed entities (indexed by entity ID)
 159  * @has_context: Context has been saved at least once and can be restored.
 160  * @ref_count: Reference count for handling multiple ISP requests.
 161  * @cam_ick: Pointer to camera interface clock structure.
 162  * @cam_mclk: Pointer to camera functional clock structure.
 163  * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
 164  * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
 165  * @xclks: External clocks provided by the ISP
 166  * @irq: Currently attached ISP ISR callbacks information structure.
 167  * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
 168  * @isp_hist: Pointer to current settings for ISP Histogram SCM.
 169  * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
 170  *           White Balance SCM.
 171  * @isp_res: Pointer to current settings for ISP Resizer.
 172  * @isp_prev: Pointer to current settings for ISP Preview.
 173  * @isp_ccdc: Pointer to current settings for ISP CCDC.
 174  * @iommu: Pointer to requested IOMMU instance for ISP.
 175  * @platform_cb: ISP driver callback function pointers for platform code
 176  *
 177  * This structure is used to store the OMAP ISP Information.
 178  */
 179 struct isp_device {
 180         struct v4l2_device v4l2_dev;
 181         struct media_device media_dev;
 182         struct device *dev;
 183         u32 revision;
 184
 185         /* platform HW resources */
 186         struct isp_platform_data *pdata;
 187         unsigned int irq_num;
 188
 189         void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
 190         unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
 191
 192         /* ISP Obj */
 193         spinlock_t stat_lock;   /* common lock for statistic drivers */
 194         struct mutex isp_mutex; /* For handling ref_count field */
 195         bool stop_failure;
 196         u32 crashed;
 197         int has_context;
 198         int ref_count;
 199         unsigned int autoidle;
 200 #define ISP_CLK_CAM_ICK         0
 201 #define ISP_CLK_CAM_MCLK        1
 202 #define ISP_CLK_CSI2_FCK        2
 203 #define ISP_CLK_L3_ICK          3
 204         struct clk *clock[4];
 205         struct isp_xclk xclks[2];
 206
 207         /* ISP modules */
 208         struct ispstat isp_af;
 209         struct ispstat isp_aewb;
 210         struct ispstat isp_hist;
 211         struct isp_res_device isp_res;
 212         struct isp_prev_device isp_prev;
 213         struct isp_ccdc_device isp_ccdc;
 214         struct isp_csi2_device isp_csi2a;
 215         struct isp_csi2_device isp_csi2c;
 216         struct isp_ccp2_device isp_ccp2;
 217         struct isp_csiphy isp_csiphy1;
 218         struct isp_csiphy isp_csiphy2;
 219
 220         unsigned int sbl_resources;
 221         unsigned int subclk_resources;
 222
 223         struct iommu_domain *domain;
 224 };
 225
 226 #define v4l2_dev_to_isp_device(dev) \
 227         container_of(dev, struct isp_device, v4l2_dev)
 228
 229 void omap3isp_hist_dma_done(struct isp_device *isp);
 230
 231 void omap3isp_flush(struct isp_device *isp);
 232
 233 int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
 234                               atomic_t *stopping);
 235
 236 int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
 237                                      atomic_t *stopping);
 238
 239 int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
 240                                  enum isp_pipeline_stream_state state);
 241 void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe);
 242 void omap3isp_configure_bridge(struct isp_device *isp,
 243                                enum ccdc_input_entity input,
 244                                const struct isp_parallel_platform_data *pdata,
 245                                unsigned int shift, unsigned int bridge);
 246
 247 struct isp_device *omap3isp_get(struct isp_device *isp);
 248 void omap3isp_put(struct isp_device *isp);
 249
 250 void omap3isp_print_status(struct isp_device *isp);
 251
 252 void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
 253 void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
 254
 255 void omap3isp_subclk_enable(struct isp_device *isp,
 256                             enum isp_subclk_resource res);
 257 void omap3isp_subclk_disable(struct isp_device *isp,
 258                              enum isp_subclk_resource res);
 259
 260 int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
 261
 262 int omap3isp_register_entities(struct platform_device *pdev,
 263                                struct v4l2_device *v4l2_dev);
 264 void omap3isp_unregister_entities(struct platform_device *pdev);
 265
 266 /*
 267  * isp_reg_readl - Read value of an OMAP3 ISP register
 268  * @dev: Device pointer specific to the OMAP3 ISP.
 269  * @isp_mmio_range: Range to which the register offset refers to.
 270  * @reg_offset: Register offset to read from.
 271  *
 272  * Returns an unsigned 32 bit value with the required register contents.
 273  */
 274 static inline
 275 u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
 276                   u32 reg_offset)
 277 {
 278         return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
 279 }
 280
 281 /*
 282  * isp_reg_writel - Write value to an OMAP3 ISP register
 283  * @dev: Device pointer specific to the OMAP3 ISP.
 284  * @reg_value: 32 bit value to write to the register.
 285  * @isp_mmio_range: Range to which the register offset refers to.
 286  * @reg_offset: Register offset to write into.
 287  */
 288 static inline
 289 void isp_reg_writel(struct isp_device *isp, u32 reg_value,
 290                     enum isp_mem_resources isp_mmio_range, u32 reg_offset)
 291 {
 292         __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
 293 }
 294
 295 /*
 296  * isp_reg_and - Clear individual bits in an OMAP3 ISP register
 297  * @dev: Device pointer specific to the OMAP3 ISP.
 298  * @mmio_range: Range to which the register offset refers to.
 299  * @reg: Register offset to work on.
 300  * @clr_bits: 32 bit value which would be cleared in the register.
 301  */
 302 static inline
 303 void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
 304                  u32 reg, u32 clr_bits)
 305 {
 306         u32 v = isp_reg_readl(isp, mmio_range, reg);
 307
 308         isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
 309 }
 310
 311 /*
 312  * isp_reg_set - Set individual bits in an OMAP3 ISP register
 313  * @dev: Device pointer specific to the OMAP3 ISP.
 314  * @mmio_range: Range to which the register offset refers to.
 315  * @reg: Register offset to work on.
 316  * @set_bits: 32 bit value which would be set in the register.
 317  */
 318 static inline
 319 void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 320                  u32 reg, u32 set_bits)
 321 {
 322         u32 v = isp_reg_readl(isp, mmio_range, reg);
 323
 324         isp_reg_writel(isp, v | set_bits, mmio_range, reg);
 325 }
 326
 327 /*
 328  * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
 329  * @dev: Device pointer specific to the OMAP3 ISP.
 330  * @mmio_range: Range to which the register offset refers to.
 331  * @reg: Register offset to work on.
 332  * @clr_bits: 32 bit value which would be cleared in the register.
 333  * @set_bits: 32 bit value which would be set in the register.
 334  *
 335  * The clear operation is done first, and then the set operation.
 336  */
 337 static inline
 338 void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
 339                      u32 reg, u32 clr_bits, u32 set_bits)
 340 {
 341         u32 v = isp_reg_readl(isp, mmio_range, reg);
 342
 343         isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
 344 }
 345
 346 static inline enum v4l2_buf_type
 347 isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
 348 {
 349         if (pad >= subdev->entity.num_pads)
 350                 return 0;
 351
 352         if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
 353                 return V4L2_BUF_TYPE_VIDEO_OUTPUT;
 354         else
 355                 return V4L2_BUF_TYPE_VIDEO_CAPTURE;
 356 }
 357
 358 #endif  /* OMAP3_ISP_CORE_H */