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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / platform / omap3isp / ispccp2.c
blobe84fe0543e4719424c3224895ed7b5a218ea8904
1 /*
2 * ispccp2.c
3 *
4 * TI OMAP3 ISP - CCP2 module
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2010 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27 #include <linux/delay.h>
28 #include <linux/device.h>
29 #include <linux/mm.h>
30 #include <linux/module.h>
31 #include <linux/mutex.h>
32 #include <linux/uaccess.h>
33 #include <linux/regulator/consumer.h>
34
35 #include "isp.h"
36 #include "ispreg.h"
37 #include "ispccp2.h"
38
39 /* Number of LCX channels */
40 #define CCP2_LCx_CHANS_NUM 3
41 /* Max/Min size for CCP2 video port */
42 #define ISPCCP2_DAT_START_MIN 0
43 #define ISPCCP2_DAT_START_MAX 4095
44 #define ISPCCP2_DAT_SIZE_MIN 0
45 #define ISPCCP2_DAT_SIZE_MAX 4095
46 #define ISPCCP2_VPCLK_FRACDIV 65536
47 #define ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP 0x12
48 #define ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP 0x16
49 /* Max/Min size for CCP2 memory channel */
50 #define ISPCCP2_LCM_HSIZE_COUNT_MIN 16
51 #define ISPCCP2_LCM_HSIZE_COUNT_MAX 8191
52 #define ISPCCP2_LCM_HSIZE_SKIP_MIN 0
53 #define ISPCCP2_LCM_HSIZE_SKIP_MAX 8191
54 #define ISPCCP2_LCM_VSIZE_MIN 1
55 #define ISPCCP2_LCM_VSIZE_MAX 8191
56 #define ISPCCP2_LCM_HWORDS_MIN 1
57 #define ISPCCP2_LCM_HWORDS_MAX 4095
58 #define ISPCCP2_LCM_CTRL_BURST_SIZE_32X 5
59 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_FULL 0
60 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 2
61 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 2
62 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 3
63 #define ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 3
64 #define ISPCCP2_LCM_CTRL_DST_PORT_VP 0
65 #define ISPCCP2_LCM_CTRL_DST_PORT_MEM 1
66
67 /* Set only the required bits */
68 #define BIT_SET(var, shift, mask, val) \
69 do { \
70 var = ((var) & ~((mask) << (shift))) \
71 | ((val) << (shift)); \
72 } while (0)
73
74 /*
75 * ccp2_print_status - Print current CCP2 module register values.
76 */
77 #define CCP2_PRINT_REGISTER(isp, name)\
78 dev_dbg(isp->dev, "###CCP2 " #name "=0x%08x\n", \
79 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_##name))
80
81 static void ccp2_print_status(struct isp_ccp2_device *ccp2)
82 {
83 struct isp_device *isp = to_isp_device(ccp2);
84
85 dev_dbg(isp->dev, "-------------CCP2 Register dump-------------\n");
86
87 CCP2_PRINT_REGISTER(isp, SYSCONFIG);
88 CCP2_PRINT_REGISTER(isp, SYSSTATUS);
89 CCP2_PRINT_REGISTER(isp, LC01_IRQENABLE);
90 CCP2_PRINT_REGISTER(isp, LC01_IRQSTATUS);
91 CCP2_PRINT_REGISTER(isp, LC23_IRQENABLE);
92 CCP2_PRINT_REGISTER(isp, LC23_IRQSTATUS);
93 CCP2_PRINT_REGISTER(isp, LCM_IRQENABLE);
94 CCP2_PRINT_REGISTER(isp, LCM_IRQSTATUS);
95 CCP2_PRINT_REGISTER(isp, CTRL);
96 CCP2_PRINT_REGISTER(isp, LCx_CTRL(0));
97 CCP2_PRINT_REGISTER(isp, LCx_CODE(0));
98 CCP2_PRINT_REGISTER(isp, LCx_STAT_START(0));
99 CCP2_PRINT_REGISTER(isp, LCx_STAT_SIZE(0));
100 CCP2_PRINT_REGISTER(isp, LCx_SOF_ADDR(0));
101 CCP2_PRINT_REGISTER(isp, LCx_EOF_ADDR(0));
102 CCP2_PRINT_REGISTER(isp, LCx_DAT_START(0));
103 CCP2_PRINT_REGISTER(isp, LCx_DAT_SIZE(0));
104 CCP2_PRINT_REGISTER(isp, LCx_DAT_PING_ADDR(0));
105 CCP2_PRINT_REGISTER(isp, LCx_DAT_PONG_ADDR(0));
106 CCP2_PRINT_REGISTER(isp, LCx_DAT_OFST(0));
107 CCP2_PRINT_REGISTER(isp, LCM_CTRL);
108 CCP2_PRINT_REGISTER(isp, LCM_VSIZE);
109 CCP2_PRINT_REGISTER(isp, LCM_HSIZE);
110 CCP2_PRINT_REGISTER(isp, LCM_PREFETCH);
111 CCP2_PRINT_REGISTER(isp, LCM_SRC_ADDR);
112 CCP2_PRINT_REGISTER(isp, LCM_SRC_OFST);
113 CCP2_PRINT_REGISTER(isp, LCM_DST_ADDR);
114 CCP2_PRINT_REGISTER(isp, LCM_DST_OFST);
115
116 dev_dbg(isp->dev, "--------------------------------------------\n");
117 }
118
119 /*
120 * ccp2_reset - Reset the CCP2
121 * @ccp2: pointer to ISP CCP2 device
122 */
123 static void ccp2_reset(struct isp_ccp2_device *ccp2)
124 {
125 struct isp_device *isp = to_isp_device(ccp2);
126 int i = 0;
127
128 /* Reset the CSI1/CCP2B and wait for reset to complete */
129 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG,
130 ISPCCP2_SYSCONFIG_SOFT_RESET);
131 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSSTATUS) &
132 ISPCCP2_SYSSTATUS_RESET_DONE)) {
133 udelay(10);
134 if (i++ > 10) { /* try read 10 times */
135 dev_warn(isp->dev,
136 "omap3_isp: timeout waiting for ccp2 reset\n");
137 break;
138 }
139 }
140 }
141
142 /*
143 * ccp2_pwr_cfg - Configure the power mode settings
144 * @ccp2: pointer to ISP CCP2 device
145 */
146 static void ccp2_pwr_cfg(struct isp_ccp2_device *ccp2)
147 {
148 struct isp_device *isp = to_isp_device(ccp2);
149
150 isp_reg_writel(isp, ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART |
151 ((isp->revision == ISP_REVISION_15_0 && isp->autoidle) ?
152 ISPCCP2_SYSCONFIG_AUTO_IDLE : 0),
153 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG);
154 }
155
156 /*
157 * ccp2_if_enable - Enable CCP2 interface.
158 * @ccp2: pointer to ISP CCP2 device
159 * @enable: enable/disable flag
160 */
161 static int ccp2_if_enable(struct isp_ccp2_device *ccp2, u8 enable)
162 {
163 struct isp_device *isp = to_isp_device(ccp2);
164 int ret;
165 int i;
166
167 if (enable && ccp2->vdds_csib) {
168 ret = regulator_enable(ccp2->vdds_csib);
169 if (ret < 0)
170 return ret;
171 }
172
173 /* Enable/Disable all the LCx channels */
174 for (i = 0; i < CCP2_LCx_CHANS_NUM; i++)
175 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(i),
176 ISPCCP2_LCx_CTRL_CHAN_EN,
177 enable ? ISPCCP2_LCx_CTRL_CHAN_EN : 0);
178
179 /* Enable/Disable ccp2 interface in ccp2 mode */
180 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
181 ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN,
182 enable ? (ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN) : 0);
183
184 if (!enable && ccp2->vdds_csib)
185 regulator_disable(ccp2->vdds_csib);
186
187 return 0;
188 }
189
190 /*
191 * ccp2_mem_enable - Enable CCP2 memory interface.
192 * @ccp2: pointer to ISP CCP2 device
193 * @enable: enable/disable flag
194 */
195 static void ccp2_mem_enable(struct isp_ccp2_device *ccp2, u8 enable)
196 {
197 struct isp_device *isp = to_isp_device(ccp2);
198
199 if (enable)
200 ccp2_if_enable(ccp2, 0);
201
202 /* Enable/Disable ccp2 interface in ccp2 mode */
203 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
204 ISPCCP2_CTRL_MODE, enable ? ISPCCP2_CTRL_MODE : 0);
205
206 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL,
207 ISPCCP2_LCM_CTRL_CHAN_EN,
208 enable ? ISPCCP2_LCM_CTRL_CHAN_EN : 0);
209 }
210
211 /*
212 * ccp2_phyif_config - Initialize CCP2 phy interface config
213 * @ccp2: Pointer to ISP CCP2 device
214 * @config: CCP2 platform data
215 *
216 * Configure the CCP2 physical interface module from platform data.
217 *
218 * Returns -EIO if strobe is chosen in CSI1 mode, or 0 on success.
219 */
220 static int ccp2_phyif_config(struct isp_ccp2_device *ccp2,
221 const struct isp_ccp2_platform_data *pdata)
222 {
223 struct isp_device *isp = to_isp_device(ccp2);
224 u32 val;
225
226 /* CCP2B mode */
227 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) |
228 ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE;
229 /* Data/strobe physical layer */
230 BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK,
231 pdata->phy_layer);
232 BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK,
233 pdata->strobe_clk_pol);
234 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
235
236 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
237 if (!(val & ISPCCP2_CTRL_MODE)) {
238 if (pdata->ccp2_mode == ISP_CCP2_MODE_CCP2)
239 dev_warn(isp->dev, "OMAP3 CCP2 bus not available\n");
240 if (pdata->phy_layer == ISP_CCP2_PHY_DATA_STROBE)
241 /* Strobe mode requires CCP2 */
242 return -EIO;
243 }
244
245 return 0;
246 }
247
248 /*
249 * ccp2_vp_config - Initialize CCP2 video port interface.
250 * @ccp2: Pointer to ISP CCP2 device
251 * @vpclk_div: Video port divisor
252 *
253 * Configure the CCP2 video port with the given clock divisor. The valid divisor
254 * values depend on the ISP revision:
255 *
256 * - revision 1.0 and 2.0 1 to 4
257 * - revision 15.0 1 to 65536
258 *
259 * The exact divisor value used might differ from the requested value, as ISP
260 * revision 15.0 represent the divisor by 65536 divided by an integer.
261 */
262 static void ccp2_vp_config(struct isp_ccp2_device *ccp2,
263 unsigned int vpclk_div)
264 {
265 struct isp_device *isp = to_isp_device(ccp2);
266 u32 val;
267
268 /* ISPCCP2_CTRL Video port */
269 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
270 val |= ISPCCP2_CTRL_VP_ONLY_EN; /* Disable the memory write port */
271
272 if (isp->revision == ISP_REVISION_15_0) {
273 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 65536);
274 vpclk_div = min(ISPCCP2_VPCLK_FRACDIV / vpclk_div, 65535U);
275 BIT_SET(val, ISPCCP2_CTRL_VPCLK_DIV_SHIFT,
276 ISPCCP2_CTRL_VPCLK_DIV_MASK, vpclk_div);
277 } else {
278 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 4);
279 BIT_SET(val, ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT,
280 ISPCCP2_CTRL_VP_OUT_CTRL_MASK, vpclk_div - 1);
281 }
282
283 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
284 }
285
286 /*
287 * ccp2_lcx_config - Initialize CCP2 logical channel interface.
288 * @ccp2: Pointer to ISP CCP2 device
289 * @config: Pointer to ISP LCx config structure.
290 *
291 * This will analyze the parameters passed by the interface config
292 * and configure CSI1/CCP2 logical channel
293 *
294 */
295 static void ccp2_lcx_config(struct isp_ccp2_device *ccp2,
296 struct isp_interface_lcx_config *config)
297 {
298 struct isp_device *isp = to_isp_device(ccp2);
299 u32 val, format;
300
301 switch (config->format) {
302 case V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8:
303 format = ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP;
304 break;
305 case V4L2_MBUS_FMT_SGRBG10_1X10:
306 default:
307 format = ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP; /* RAW10+VP */
308 break;
309 }
310 /* ISPCCP2_LCx_CTRL logical channel #0 */
311 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0))
312 | (ISPCCP2_LCx_CTRL_REGION_EN); /* Region */
313
314 if (isp->revision == ISP_REVISION_15_0) {
315 /* CRC */
316 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0,
317 ISPCCP2_LCx_CTRL_CRC_MASK,
318 config->crc);
319 /* Format = RAW10+VP or RAW8+DPCM10+VP*/
320 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0,
321 ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0, format);
322 } else {
323 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT,
324 ISPCCP2_LCx_CTRL_CRC_MASK,
325 config->crc);
326
327 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT,
328 ISPCCP2_LCx_CTRL_FORMAT_MASK, format);
329 }
330 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0));
331
332 /* ISPCCP2_DAT_START for logical channel #0 */
333 isp_reg_writel(isp, config->data_start << ISPCCP2_LCx_DAT_SHIFT,
334 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_START(0));
335
336 /* ISPCCP2_DAT_SIZE for logical channel #0 */
337 isp_reg_writel(isp, config->data_size << ISPCCP2_LCx_DAT_SHIFT,
338 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_SIZE(0));
339
340 /* Enable error IRQs for logical channel #0 */
341 val = ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
342 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
343 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
344 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
345 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
346 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
347
348 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQSTATUS);
349 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQENABLE, val);
350 }
351
352 /*
353 * ccp2_if_configure - Configure ccp2 with data from sensor
354 * @ccp2: Pointer to ISP CCP2 device
355 *
356 * Return 0 on success or a negative error code
357 */
358 static int ccp2_if_configure(struct isp_ccp2_device *ccp2)
359 {
360 const struct isp_v4l2_subdevs_group *pdata;
361 struct v4l2_mbus_framefmt *format;
362 struct media_pad *pad;
363 struct v4l2_subdev *sensor;
364 u32 lines = 0;
365 int ret;
366
367 ccp2_pwr_cfg(ccp2);
368
369 pad = media_entity_remote_pad(&ccp2->pads[CCP2_PAD_SINK]);
370 sensor = media_entity_to_v4l2_subdev(pad->entity);
371 pdata = sensor->host_priv;
372
373 ret = ccp2_phyif_config(ccp2, &pdata->bus.ccp2);
374 if (ret < 0)
375 return ret;
376
377 ccp2_vp_config(ccp2, pdata->bus.ccp2.vpclk_div + 1);
378
379 v4l2_subdev_call(sensor, sensor, g_skip_top_lines, &lines);
380
381 format = &ccp2->formats[CCP2_PAD_SINK];
382
383 ccp2->if_cfg.data_start = lines;
384 ccp2->if_cfg.crc = pdata->bus.ccp2.crc;
385 ccp2->if_cfg.format = format->code;
386 ccp2->if_cfg.data_size = format->height;
387
388 ccp2_lcx_config(ccp2, &ccp2->if_cfg);
389
390 return 0;
391 }
392
393 static int ccp2_adjust_bandwidth(struct isp_ccp2_device *ccp2)
394 {
395 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
396 struct isp_device *isp = to_isp_device(ccp2);
397 const struct v4l2_mbus_framefmt *ofmt = &ccp2->formats[CCP2_PAD_SOURCE];
398 unsigned long l3_ick = pipe->l3_ick;
399 struct v4l2_fract *timeperframe;
400 unsigned int vpclk_div = 2;
401 unsigned int value;
402 u64 bound;
403 u64 area;
404
405 /* Compute the minimum clock divisor, based on the pipeline maximum
406 * data rate. This is an absolute lower bound if we don't want SBL
407 * overflows, so round the value up.
408 */
409 vpclk_div = max_t(unsigned int, DIV_ROUND_UP(l3_ick, pipe->max_rate),
410 vpclk_div);
411
412 /* Compute the maximum clock divisor, based on the requested frame rate.
413 * This is a soft lower bound to achieve a frame rate equal or higher
414 * than the requested value, so round the value down.
415 */
416 timeperframe = &pipe->max_timeperframe;
417
418 if (timeperframe->numerator) {
419 area = ofmt->width * ofmt->height;
420 bound = div_u64(area * timeperframe->denominator,
421 timeperframe->numerator);
422 value = min_t(u64, bound, l3_ick);
423 vpclk_div = max_t(unsigned int, l3_ick / value, vpclk_div);
424 }
425
426 dev_dbg(isp->dev, "%s: minimum clock divisor = %u\n", __func__,
427 vpclk_div);
428
429 return vpclk_div;
430 }
431
432 /*
433 * ccp2_mem_configure - Initialize CCP2 memory input/output interface
434 * @ccp2: Pointer to ISP CCP2 device
435 * @config: Pointer to ISP mem interface config structure
436 *
437 * This will analyze the parameters passed by the interface config
438 * structure, and configure the respective registers for proper
439 * CSI1/CCP2 memory input.
440 */
441 static void ccp2_mem_configure(struct isp_ccp2_device *ccp2,
442 struct isp_interface_mem_config *config)
443 {
444 struct isp_device *isp = to_isp_device(ccp2);
445 u32 sink_pixcode = ccp2->formats[CCP2_PAD_SINK].code;
446 u32 source_pixcode = ccp2->formats[CCP2_PAD_SOURCE].code;
447 unsigned int dpcm_decompress = 0;
448 u32 val, hwords;
449
450 if (sink_pixcode != source_pixcode &&
451 sink_pixcode == V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8)
452 dpcm_decompress = 1;
453
454 ccp2_pwr_cfg(ccp2);
455
456 /* Hsize, Skip */
457 isp_reg_writel(isp, ISPCCP2_LCM_HSIZE_SKIP_MIN |
458 (config->hsize_count << ISPCCP2_LCM_HSIZE_SHIFT),
459 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_HSIZE);
460
461 /* Vsize, no. of lines */
462 isp_reg_writel(isp, config->vsize_count << ISPCCP2_LCM_VSIZE_SHIFT,
463 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_VSIZE);
464
465 if (ccp2->video_in.bpl_padding == 0)
466 config->src_ofst = 0;
467 else
468 config->src_ofst = ccp2->video_in.bpl_value;
469
470 isp_reg_writel(isp, config->src_ofst, OMAP3_ISP_IOMEM_CCP2,
471 ISPCCP2_LCM_SRC_OFST);
472
473 /* Source and Destination formats */
474 val = ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 <<
475 ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT;
476
477 if (dpcm_decompress) {
478 /* source format is RAW8 */
479 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 <<
480 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
481
482 /* RAW8 + DPCM10 - simple predictor */
483 val |= ISPCCP2_LCM_CTRL_SRC_DPCM_PRED;
484
485 /* enable source DPCM decompression */
486 val |= ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 <<
487 ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT;
488 } else {
489 /* source format is RAW10 */
490 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 <<
491 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
492 }
493
494 /* Burst size to 32x64 */
495 val |= ISPCCP2_LCM_CTRL_BURST_SIZE_32X <<
496 ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT;
497
498 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL);
499
500 /* Prefetch setup */
501 if (dpcm_decompress)
502 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
503 config->hsize_count) >> 3;
504 else
505 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
506 config->hsize_count) >> 2;
507
508 isp_reg_writel(isp, hwords << ISPCCP2_LCM_PREFETCH_SHIFT,
509 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_PREFETCH);
510
511 /* Video port */
512 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
513 ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE);
514 ccp2_vp_config(ccp2, ccp2_adjust_bandwidth(ccp2));
515
516 /* Clear LCM interrupts */
517 isp_reg_writel(isp, ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ |
518 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ,
519 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQSTATUS);
520
521 /* Enable LCM interupts */
522 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQENABLE,
523 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ |
524 ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ);
525 }
526
527 /*
528 * ccp2_set_inaddr - Sets memory address of input frame.
529 * @ccp2: Pointer to ISP CCP2 device
530 * @addr: 32bit memory address aligned on 32byte boundary.
531 *
532 * Configures the memory address from which the input frame is to be read.
533 */
534 static void ccp2_set_inaddr(struct isp_ccp2_device *ccp2, u32 addr)
535 {
536 struct isp_device *isp = to_isp_device(ccp2);
537
538 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_SRC_ADDR);
539 }
540
541 /* -----------------------------------------------------------------------------
542 * Interrupt handling
543 */
544
545 static void ccp2_isr_buffer(struct isp_ccp2_device *ccp2)
546 {
547 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
548 struct isp_buffer *buffer;
549
550 buffer = omap3isp_video_buffer_next(&ccp2->video_in);
551 if (buffer != NULL)
552 ccp2_set_inaddr(ccp2, buffer->isp_addr);
553
554 pipe->state |= ISP_PIPELINE_IDLE_INPUT;
555
556 if (ccp2->state == ISP_PIPELINE_STREAM_SINGLESHOT) {
557 if (isp_pipeline_ready(pipe))
558 omap3isp_pipeline_set_stream(pipe,
559 ISP_PIPELINE_STREAM_SINGLESHOT);
560 }
561 }
562
563 /*
564 * omap3isp_ccp2_isr - Handle ISP CCP2 interrupts
565 * @ccp2: Pointer to ISP CCP2 device
566 *
567 * This will handle the CCP2 interrupts
568 */
569 void omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2)
570 {
571 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
572 struct isp_device *isp = to_isp_device(ccp2);
573 static const u32 ISPCCP2_LC01_ERROR =
574 ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
575 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
576 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
577 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
578 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
579 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
580 u32 lcx_irqstatus, lcm_irqstatus;
581
582 /* First clear the interrupts */
583 lcx_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
584 ISPCCP2_LC01_IRQSTATUS);
585 isp_reg_writel(isp, lcx_irqstatus, OMAP3_ISP_IOMEM_CCP2,
586 ISPCCP2_LC01_IRQSTATUS);
587
588 lcm_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
589 ISPCCP2_LCM_IRQSTATUS);
590 isp_reg_writel(isp, lcm_irqstatus, OMAP3_ISP_IOMEM_CCP2,
591 ISPCCP2_LCM_IRQSTATUS);
592 /* Errors */
593 if (lcx_irqstatus & ISPCCP2_LC01_ERROR) {
594 pipe->error = true;
595 dev_dbg(isp->dev, "CCP2 err:%x\n", lcx_irqstatus);
596 return;
597 }
598
599 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ) {
600 pipe->error = true;
601 dev_dbg(isp->dev, "CCP2 OCP err:%x\n", lcm_irqstatus);
602 }
603
604 if (omap3isp_module_sync_is_stopping(&ccp2->wait, &ccp2->stopping))
605 return;
606
607 /* Handle queued buffers on frame end interrupts */
608 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_EOF_IRQ)
609 ccp2_isr_buffer(ccp2);
610 }
611
612 /* -----------------------------------------------------------------------------
613 * V4L2 subdev operations
614 */
615
616 static const unsigned int ccp2_fmts[] = {
617 V4L2_MBUS_FMT_SGRBG10_1X10,
618 V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8,
619 };
620
621 /*
622 * __ccp2_get_format - helper function for getting ccp2 format
623 * @ccp2 : Pointer to ISP CCP2 device
624 * @fh : V4L2 subdev file handle
625 * @pad : pad number
626 * @which : wanted subdev format
627 * return format structure or NULL on error
628 */
629 static struct v4l2_mbus_framefmt *
630 __ccp2_get_format(struct isp_ccp2_device *ccp2, struct v4l2_subdev_fh *fh,
631 unsigned int pad, enum v4l2_subdev_format_whence which)
632 {
633 if (which == V4L2_SUBDEV_FORMAT_TRY)
634 return v4l2_subdev_get_try_format(fh, pad);
635 else
636 return &ccp2->formats[pad];
637 }
638
639 /*
640 * ccp2_try_format - Handle try format by pad subdev method
641 * @ccp2 : Pointer to ISP CCP2 device
642 * @fh : V4L2 subdev file handle
643 * @pad : pad num
644 * @fmt : pointer to v4l2 mbus format structure
645 * @which : wanted subdev format
646 */
647 static void ccp2_try_format(struct isp_ccp2_device *ccp2,
648 struct v4l2_subdev_fh *fh, unsigned int pad,
649 struct v4l2_mbus_framefmt *fmt,
650 enum v4l2_subdev_format_whence which)
651 {
652 struct v4l2_mbus_framefmt *format;
653
654 switch (pad) {
655 case CCP2_PAD_SINK:
656 if (fmt->code != V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8)
657 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
658
659 if (ccp2->input == CCP2_INPUT_SENSOR) {
660 fmt->width = clamp_t(u32, fmt->width,
661 ISPCCP2_DAT_START_MIN,
662 ISPCCP2_DAT_START_MAX);
663 fmt->height = clamp_t(u32, fmt->height,
664 ISPCCP2_DAT_SIZE_MIN,
665 ISPCCP2_DAT_SIZE_MAX);
666 } else if (ccp2->input == CCP2_INPUT_MEMORY) {
667 fmt->width = clamp_t(u32, fmt->width,
668 ISPCCP2_LCM_HSIZE_COUNT_MIN,
669 ISPCCP2_LCM_HSIZE_COUNT_MAX);
670 fmt->height = clamp_t(u32, fmt->height,
671 ISPCCP2_LCM_VSIZE_MIN,
672 ISPCCP2_LCM_VSIZE_MAX);
673 }
674 break;
675
676 case CCP2_PAD_SOURCE:
677 /* Source format - copy sink format and change pixel code
678 * to SGRBG10_1X10 as we don't support CCP2 write to memory.
679 * When CCP2 write to memory feature will be added this
680 * should be changed properly.
681 */
682 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SINK, which);
683 memcpy(fmt, format, sizeof(*fmt));
684 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
685 break;
686 }
687
688 fmt->field = V4L2_FIELD_NONE;
689 fmt->colorspace = V4L2_COLORSPACE_SRGB;
690 }
691
692 /*
693 * ccp2_enum_mbus_code - Handle pixel format enumeration
694 * @sd : pointer to v4l2 subdev structure
695 * @fh : V4L2 subdev file handle
696 * @code : pointer to v4l2_subdev_mbus_code_enum structure
697 * return -EINVAL or zero on success
698 */
699 static int ccp2_enum_mbus_code(struct v4l2_subdev *sd,
700 struct v4l2_subdev_fh *fh,
701 struct v4l2_subdev_mbus_code_enum *code)
702 {
703 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
704 struct v4l2_mbus_framefmt *format;
705
706 if (code->pad == CCP2_PAD_SINK) {
707 if (code->index >= ARRAY_SIZE(ccp2_fmts))
708 return -EINVAL;
709
710 code->code = ccp2_fmts[code->index];
711 } else {
712 if (code->index != 0)
713 return -EINVAL;
714
715 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SINK,
716 V4L2_SUBDEV_FORMAT_TRY);
717 code->code = format->code;
718 }
719
720 return 0;
721 }
722
723 static int ccp2_enum_frame_size(struct v4l2_subdev *sd,
724 struct v4l2_subdev_fh *fh,
725 struct v4l2_subdev_frame_size_enum *fse)
726 {
727 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
728 struct v4l2_mbus_framefmt format;
729
730 if (fse->index != 0)
731 return -EINVAL;
732
733 format.code = fse->code;
734 format.width = 1;
735 format.height = 1;
736 ccp2_try_format(ccp2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
737 fse->min_width = format.width;
738 fse->min_height = format.height;
739
740 if (format.code != fse->code)
741 return -EINVAL;
742
743 format.code = fse->code;
744 format.width = -1;
745 format.height = -1;
746 ccp2_try_format(ccp2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
747 fse->max_width = format.width;
748 fse->max_height = format.height;
749
750 return 0;
751 }
752
753 /*
754 * ccp2_get_format - Handle get format by pads subdev method
755 * @sd : pointer to v4l2 subdev structure
756 * @fh : V4L2 subdev file handle
757 * @fmt : pointer to v4l2 subdev format structure
758 * return -EINVAL or zero on success
759 */
760 static int ccp2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
761 struct v4l2_subdev_format *fmt)
762 {
763 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
764 struct v4l2_mbus_framefmt *format;
765
766 format = __ccp2_get_format(ccp2, fh, fmt->pad, fmt->which);
767 if (format == NULL)
768 return -EINVAL;
769
770 fmt->format = *format;
771 return 0;
772 }
773
774 /*
775 * ccp2_set_format - Handle set format by pads subdev method
776 * @sd : pointer to v4l2 subdev structure
777 * @fh : V4L2 subdev file handle
778 * @fmt : pointer to v4l2 subdev format structure
779 * returns zero
780 */
781 static int ccp2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
782 struct v4l2_subdev_format *fmt)
783 {
784 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
785 struct v4l2_mbus_framefmt *format;
786
787 format = __ccp2_get_format(ccp2, fh, fmt->pad, fmt->which);
788 if (format == NULL)
789 return -EINVAL;
790
791 ccp2_try_format(ccp2, fh, fmt->pad, &fmt->format, fmt->which);
792 *format = fmt->format;
793
794 /* Propagate the format from sink to source */
795 if (fmt->pad == CCP2_PAD_SINK) {
796 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SOURCE,
797 fmt->which);
798 *format = fmt->format;
799 ccp2_try_format(ccp2, fh, CCP2_PAD_SOURCE, format, fmt->which);
800 }
801
802 return 0;
803 }
804
805 /*
806 * ccp2_init_formats - Initialize formats on all pads
807 * @sd: ISP CCP2 V4L2 subdevice
808 * @fh: V4L2 subdev file handle
809 *
810 * Initialize all pad formats with default values. If fh is not NULL, try
811 * formats are initialized on the file handle. Otherwise active formats are
812 * initialized on the device.
813 */
814 static int ccp2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
815 {
816 struct v4l2_subdev_format format;
817
818 memset(&format, 0, sizeof(format));
819 format.pad = CCP2_PAD_SINK;
820 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
821 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
822 format.format.width = 4096;
823 format.format.height = 4096;
824 ccp2_set_format(sd, fh, &format);
825
826 return 0;
827 }
828
829 /*
830 * ccp2_s_stream - Enable/Disable streaming on ccp2 subdev
831 * @sd : pointer to v4l2 subdev structure
832 * @enable: 1 == Enable, 0 == Disable
833 * return zero
834 */
835 static int ccp2_s_stream(struct v4l2_subdev *sd, int enable)
836 {
837 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
838 struct isp_device *isp = to_isp_device(ccp2);
839 struct device *dev = to_device(ccp2);
840 int ret;
841
842 if (ccp2->state == ISP_PIPELINE_STREAM_STOPPED) {
843 if (enable == ISP_PIPELINE_STREAM_STOPPED)
844 return 0;
845 atomic_set(&ccp2->stopping, 0);
846 }
847
848 switch (enable) {
849 case ISP_PIPELINE_STREAM_CONTINUOUS:
850 if (ccp2->phy) {
851 ret = omap3isp_csiphy_acquire(ccp2->phy);
852 if (ret < 0)
853 return ret;
854 }
855
856 ccp2_if_configure(ccp2);
857 ccp2_print_status(ccp2);
858
859 /* Enable CSI1/CCP2 interface */
860 ret = ccp2_if_enable(ccp2, 1);
861 if (ret < 0) {
862 if (ccp2->phy)
863 omap3isp_csiphy_release(ccp2->phy);
864 return ret;
865 }
866 break;
867
868 case ISP_PIPELINE_STREAM_SINGLESHOT:
869 if (ccp2->state != ISP_PIPELINE_STREAM_SINGLESHOT) {
870 struct v4l2_mbus_framefmt *format;
871
872 format = &ccp2->formats[CCP2_PAD_SINK];
873
874 ccp2->mem_cfg.hsize_count = format->width;
875 ccp2->mem_cfg.vsize_count = format->height;
876 ccp2->mem_cfg.src_ofst = 0;
877
878 ccp2_mem_configure(ccp2, &ccp2->mem_cfg);
879 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI1_READ);
880 ccp2_print_status(ccp2);
881 }
882 ccp2_mem_enable(ccp2, 1);
883 break;
884
885 case ISP_PIPELINE_STREAM_STOPPED:
886 if (omap3isp_module_sync_idle(&sd->entity, &ccp2->wait,
887 &ccp2->stopping))
888 dev_dbg(dev, "%s: module stop timeout.\n", sd->name);
889 if (ccp2->input == CCP2_INPUT_MEMORY) {
890 ccp2_mem_enable(ccp2, 0);
891 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI1_READ);
892 } else if (ccp2->input == CCP2_INPUT_SENSOR) {
893 /* Disable CSI1/CCP2 interface */
894 ccp2_if_enable(ccp2, 0);
895 if (ccp2->phy)
896 omap3isp_csiphy_release(ccp2->phy);
897 }
898 break;
899 }
900
901 ccp2->state = enable;
902 return 0;
903 }
904
905 /* subdev video operations */
906 static const struct v4l2_subdev_video_ops ccp2_sd_video_ops = {
907 .s_stream = ccp2_s_stream,
908 };
909
910 /* subdev pad operations */
911 static const struct v4l2_subdev_pad_ops ccp2_sd_pad_ops = {
912 .enum_mbus_code = ccp2_enum_mbus_code,
913 .enum_frame_size = ccp2_enum_frame_size,
914 .get_fmt = ccp2_get_format,
915 .set_fmt = ccp2_set_format,
916 };
917
918 /* subdev operations */
919 static const struct v4l2_subdev_ops ccp2_sd_ops = {
920 .video = &ccp2_sd_video_ops,
921 .pad = &ccp2_sd_pad_ops,
922 };
923
924 /* subdev internal operations */
925 static const struct v4l2_subdev_internal_ops ccp2_sd_internal_ops = {
926 .open = ccp2_init_formats,
927 };
928
929 /* --------------------------------------------------------------------------
930 * ISP ccp2 video device node
931 */
932
933 /*
934 * ccp2_video_queue - Queue video buffer.
935 * @video : Pointer to isp video structure
936 * @buffer: Pointer to isp_buffer structure
937 * return -EIO or zero on success
938 */
939 static int ccp2_video_queue(struct isp_video *video, struct isp_buffer *buffer)
940 {
941 struct isp_ccp2_device *ccp2 = &video->isp->isp_ccp2;
942
943 ccp2_set_inaddr(ccp2, buffer->isp_addr);
944 return 0;
945 }
946
947 static const struct isp_video_operations ccp2_video_ops = {
948 .queue = ccp2_video_queue,
949 };
950
951 /* -----------------------------------------------------------------------------
952 * Media entity operations
953 */
954
955 /*
956 * ccp2_link_setup - Setup ccp2 connections.
957 * @entity : Pointer to media entity structure
958 * @local : Pointer to local pad array
959 * @remote : Pointer to remote pad array
960 * @flags : Link flags
961 * return -EINVAL on error or zero on success
962 */
963 static int ccp2_link_setup(struct media_entity *entity,
964 const struct media_pad *local,
965 const struct media_pad *remote, u32 flags)
966 {
967 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
968 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
969
970 switch (local->index | media_entity_type(remote->entity)) {
971 case CCP2_PAD_SINK | MEDIA_ENT_T_DEVNODE:
972 /* read from memory */
973 if (flags & MEDIA_LNK_FL_ENABLED) {
974 if (ccp2->input == CCP2_INPUT_SENSOR)
975 return -EBUSY;
976 ccp2->input = CCP2_INPUT_MEMORY;
977 } else {
978 if (ccp2->input == CCP2_INPUT_MEMORY)
979 ccp2->input = CCP2_INPUT_NONE;
980 }
981 break;
982
983 case CCP2_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
984 /* read from sensor/phy */
985 if (flags & MEDIA_LNK_FL_ENABLED) {
986 if (ccp2->input == CCP2_INPUT_MEMORY)
987 return -EBUSY;
988 ccp2->input = CCP2_INPUT_SENSOR;
989 } else {
990 if (ccp2->input == CCP2_INPUT_SENSOR)
991 ccp2->input = CCP2_INPUT_NONE;
992 } break;
993
994 case CCP2_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
995 /* write to video port/ccdc */
996 if (flags & MEDIA_LNK_FL_ENABLED)
997 ccp2->output = CCP2_OUTPUT_CCDC;
998 else
999 ccp2->output = CCP2_OUTPUT_NONE;
1000 break;
1001
1002 default:
1003 return -EINVAL;
1004 }
1005
1006 return 0;
1007 }
1008
1009 /* media operations */
1010 static const struct media_entity_operations ccp2_media_ops = {
1011 .link_setup = ccp2_link_setup,
1012 .link_validate = v4l2_subdev_link_validate,
1013 };
1014
1015 /*
1016 * omap3isp_ccp2_unregister_entities - Unregister media entities: subdev
1017 * @ccp2: Pointer to ISP CCP2 device
1018 */
1019 void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2)
1020 {
1021 v4l2_device_unregister_subdev(&ccp2->subdev);
1022 omap3isp_video_unregister(&ccp2->video_in);
1023 }
1024
1025 /*
1026 * omap3isp_ccp2_register_entities - Register the subdev media entity
1027 * @ccp2: Pointer to ISP CCP2 device
1028 * @vdev: Pointer to v4l device
1029 * return negative error code or zero on success
1030 */
1031
1032 int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2,
1033 struct v4l2_device *vdev)
1034 {
1035 int ret;
1036
1037 /* Register the subdev and video nodes. */
1038 ret = v4l2_device_register_subdev(vdev, &ccp2->subdev);
1039 if (ret < 0)
1040 goto error;
1041
1042 ret = omap3isp_video_register(&ccp2->video_in, vdev);
1043 if (ret < 0)
1044 goto error;
1045
1046 return 0;
1047
1048 error:
1049 omap3isp_ccp2_unregister_entities(ccp2);
1050 return ret;
1051 }
1052
1053 /* -----------------------------------------------------------------------------
1054 * ISP ccp2 initialisation and cleanup
1055 */
1056
1057 /*
1058 * ccp2_init_entities - Initialize ccp2 subdev and media entity.
1059 * @ccp2: Pointer to ISP CCP2 device
1060 * return negative error code or zero on success
1061 */
1062 static int ccp2_init_entities(struct isp_ccp2_device *ccp2)
1063 {
1064 struct v4l2_subdev *sd = &ccp2->subdev;
1065 struct media_pad *pads = ccp2->pads;
1066 struct media_entity *me = &sd->entity;
1067 int ret;
1068
1069 ccp2->input = CCP2_INPUT_NONE;
1070 ccp2->output = CCP2_OUTPUT_NONE;
1071
1072 v4l2_subdev_init(sd, &ccp2_sd_ops);
1073 sd->internal_ops = &ccp2_sd_internal_ops;
1074 strlcpy(sd->name, "OMAP3 ISP CCP2", sizeof(sd->name));
1075 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
1076 v4l2_set_subdevdata(sd, ccp2);
1077 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1078
1079 pads[CCP2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1080 | MEDIA_PAD_FL_MUST_CONNECT;
1081 pads[CCP2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1082
1083 me->ops = &ccp2_media_ops;
1084 ret = media_entity_init(me, CCP2_PADS_NUM, pads, 0);
1085 if (ret < 0)
1086 return ret;
1087
1088 ccp2_init_formats(sd, NULL);
1089
1090 /*
1091 * The CCP2 has weird line alignment requirements, possibly caused by
1092 * DPCM8 decompression. Line length for data read from memory must be a
1093 * multiple of 128 bits (16 bytes) in continuous mode (when no padding
1094 * is present at end of lines). Additionally, if padding is used, the
1095 * padded line length must be a multiple of 32 bytes. To simplify the
1096 * implementation we use a fixed 32 bytes alignment regardless of the
1097 * input format and width. If strict 128 bits alignment support is
1098 * required ispvideo will need to be made aware of this special dual
1099 * alignement requirements.
1100 */
1101 ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1102 ccp2->video_in.bpl_alignment = 32;
1103 ccp2->video_in.bpl_max = 0xffffffe0;
1104 ccp2->video_in.isp = to_isp_device(ccp2);
1105 ccp2->video_in.ops = &ccp2_video_ops;
1106 ccp2->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1107
1108 ret = omap3isp_video_init(&ccp2->video_in, "CCP2");
1109 if (ret < 0)
1110 goto error_video;
1111
1112 /* Connect the video node to the ccp2 subdev. */
1113 ret = media_entity_create_link(&ccp2->video_in.video.entity, 0,
1114 &ccp2->subdev.entity, CCP2_PAD_SINK, 0);
1115 if (ret < 0)
1116 goto error_link;
1117
1118 return 0;
1119
1120 error_link:
1121 omap3isp_video_cleanup(&ccp2->video_in);
1122 error_video:
1123 media_entity_cleanup(&ccp2->subdev.entity);
1124 return ret;
1125 }
1126
1127 /*
1128 * omap3isp_ccp2_init - CCP2 initialization.
1129 * @isp : Pointer to ISP device
1130 * return negative error code or zero on success
1131 */
1132 int omap3isp_ccp2_init(struct isp_device *isp)
1133 {
1134 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1135 int ret;
1136
1137 init_waitqueue_head(&ccp2->wait);
1138
1139 /*
1140 * On the OMAP34xx the CSI1 receiver is operated in the CSIb IO
1141 * complex, which is powered by vdds_csib power rail. Hence the
1142 * request for the regulator.
1143 *
1144 * On the OMAP36xx, the CCP2 uses the CSI PHY1 or PHY2, shared with
1145 * the CSI2c or CSI2a receivers. The PHY then needs to be explicitly
1146 * configured.
1147 *
1148 * TODO: Don't hardcode the usage of PHY1 (shared with CSI2c).
1149 */
1150 if (isp->revision == ISP_REVISION_2_0) {
1151 ccp2->vdds_csib = devm_regulator_get(isp->dev, "vdds_csib");
1152 if (IS_ERR(ccp2->vdds_csib)) {
1153 dev_dbg(isp->dev,
1154 "Could not get regulator vdds_csib\n");
1155 ccp2->vdds_csib = NULL;
1156 }
1157 } else if (isp->revision == ISP_REVISION_15_0) {
1158 ccp2->phy = &isp->isp_csiphy1;
1159 }
1160
1161 ret = ccp2_init_entities(ccp2);
1162 if (ret < 0)
1163 return ret;
1164
1165 ccp2_reset(ccp2);
1166 return 0;
1167 }
1168
1169 /*
1170 * omap3isp_ccp2_cleanup - CCP2 un-initialization
1171 * @isp : Pointer to ISP device
1172 */
1173 void omap3isp_ccp2_cleanup(struct isp_device *isp)
1174 {
1175 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1176
1177 omap3isp_video_cleanup(&ccp2->video_in);
1178 media_entity_cleanup(&ccp2->subdev.entity);
1179 }
Linux with added FPC-III support