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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / platform / omap3isp / isppreview.c
blob1c776c1186f1b9ff4a4ddbb79b6cb48c88e196f4
1 /*
2 * isppreview.c
3 *
4 * TI OMAP3 ISP driver - Preview module
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27 #include <linux/device.h>
28 #include <linux/mm.h>
29 #include <linux/module.h>
30 #include <linux/mutex.h>
31 #include <linux/uaccess.h>
32
33 #include "isp.h"
34 #include "ispreg.h"
35 #include "isppreview.h"
36
37 /* Default values in Office Fluorescent Light for RGBtoRGB Blending */
38 static struct omap3isp_prev_rgbtorgb flr_rgb2rgb = {
39 { /* RGB-RGB Matrix */
40 {0x01E2, 0x0F30, 0x0FEE},
41 {0x0F9B, 0x01AC, 0x0FB9},
42 {0x0FE0, 0x0EC0, 0x0260}
43 }, /* RGB Offset */
44 {0x0000, 0x0000, 0x0000}
45 };
46
47 /* Default values in Office Fluorescent Light for RGB to YUV Conversion*/
48 static struct omap3isp_prev_csc flr_prev_csc = {
49 { /* CSC Coef Matrix */
50 {66, 129, 25},
51 {-38, -75, 112},
52 {112, -94 , -18}
53 }, /* CSC Offset */
54 {0x0, 0x0, 0x0}
55 };
56
57 /* Default values in Office Fluorescent Light for CFA Gradient*/
58 #define FLR_CFA_GRADTHRS_HORZ 0x28
59 #define FLR_CFA_GRADTHRS_VERT 0x28
60
61 /* Default values in Office Fluorescent Light for Chroma Suppression*/
62 #define FLR_CSUP_GAIN 0x0D
63 #define FLR_CSUP_THRES 0xEB
64
65 /* Default values in Office Fluorescent Light for Noise Filter*/
66 #define FLR_NF_STRGTH 0x03
67
68 /* Default values for White Balance */
69 #define FLR_WBAL_DGAIN 0x100
70 #define FLR_WBAL_COEF 0x20
71
72 /* Default values in Office Fluorescent Light for Black Adjustment*/
73 #define FLR_BLKADJ_BLUE 0x0
74 #define FLR_BLKADJ_GREEN 0x0
75 #define FLR_BLKADJ_RED 0x0
76
77 #define DEF_DETECT_CORRECT_VAL 0xe
78
79 /*
80 * Margins and image size limits.
81 *
82 * The preview engine crops several rows and columns internally depending on
83 * which filters are enabled. To avoid format changes when the filters are
84 * enabled or disabled (which would prevent them from being turned on or off
85 * during streaming), the driver assumes all filters that can be configured
86 * during streaming are enabled when computing sink crop and source format
87 * limits.
88 *
89 * If a filter is disabled, additional cropping is automatically added at the
90 * preview engine input by the driver to avoid overflow at line and frame end.
91 * This is completely transparent for applications.
92 *
93 * Median filter 4 pixels
94 * Noise filter,
95 * Faulty pixels correction 4 pixels, 4 lines
96 * Color suppression 2 pixels
97 * or luma enhancement
98 * -------------------------------------------------------------
99 * Maximum total 10 pixels, 4 lines
100 *
101 * The color suppression and luma enhancement filters are applied after bayer to
102 * YUV conversion. They thus can crop one pixel on the left and one pixel on the
103 * right side of the image without changing the color pattern. When both those
104 * filters are disabled, the driver must crop the two pixels on the same side of
105 * the image to avoid changing the bayer pattern. The left margin is thus set to
106 * 6 pixels and the right margin to 4 pixels.
107 */
108
109 #define PREV_MARGIN_LEFT 6
110 #define PREV_MARGIN_RIGHT 4
111 #define PREV_MARGIN_TOP 2
112 #define PREV_MARGIN_BOTTOM 2
113
114 #define PREV_MIN_IN_WIDTH 64
115 #define PREV_MIN_IN_HEIGHT 8
116 #define PREV_MAX_IN_HEIGHT 16384
117
118 #define PREV_MIN_OUT_WIDTH 0
119 #define PREV_MIN_OUT_HEIGHT 0
120 #define PREV_MAX_OUT_WIDTH_REV_1 1280
121 #define PREV_MAX_OUT_WIDTH_REV_2 3300
122 #define PREV_MAX_OUT_WIDTH_REV_15 4096
123
124 /*
125 * Coeficient Tables for the submodules in Preview.
126 * Array is initialised with the values from.the tables text file.
127 */
128
129 /*
130 * CFA Filter Coefficient Table
131 *
132 */
133 static u32 cfa_coef_table[4][OMAP3ISP_PREV_CFA_BLK_SIZE] = {
134 #include "cfa_coef_table.h"
135 };
136
137 /*
138 * Default Gamma Correction Table - All components
139 */
140 static u32 gamma_table[] = {
141 #include "gamma_table.h"
142 };
143
144 /*
145 * Noise Filter Threshold table
146 */
147 static u32 noise_filter_table[] = {
148 #include "noise_filter_table.h"
149 };
150
151 /*
152 * Luminance Enhancement Table
153 */
154 static u32 luma_enhance_table[] = {
155 #include "luma_enhance_table.h"
156 };
157
158 /*
159 * preview_config_luma_enhancement - Configure the Luminance Enhancement table
160 */
161 static void
162 preview_config_luma_enhancement(struct isp_prev_device *prev,
163 const struct prev_params *params)
164 {
165 struct isp_device *isp = to_isp_device(prev);
166 const struct omap3isp_prev_luma *yt = &params->luma;
167 unsigned int i;
168
169 isp_reg_writel(isp, ISPPRV_YENH_TABLE_ADDR,
170 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
171 for (i = 0; i < OMAP3ISP_PREV_YENH_TBL_SIZE; i++) {
172 isp_reg_writel(isp, yt->table[i],
173 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
174 }
175 }
176
177 /*
178 * preview_enable_luma_enhancement - Enable/disable Luminance Enhancement
179 */
180 static void
181 preview_enable_luma_enhancement(struct isp_prev_device *prev, bool enable)
182 {
183 struct isp_device *isp = to_isp_device(prev);
184
185 if (enable)
186 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
187 ISPPRV_PCR_YNENHEN);
188 else
189 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
190 ISPPRV_PCR_YNENHEN);
191 }
192
193 /*
194 * preview_enable_invalaw - Enable/disable Inverse A-Law decompression
195 */
196 static void preview_enable_invalaw(struct isp_prev_device *prev, bool enable)
197 {
198 struct isp_device *isp = to_isp_device(prev);
199
200 if (enable)
201 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
202 ISPPRV_PCR_INVALAW);
203 else
204 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
205 ISPPRV_PCR_INVALAW);
206 }
207
208 /*
209 * preview_config_hmed - Configure the Horizontal Median Filter
210 */
211 static void preview_config_hmed(struct isp_prev_device *prev,
212 const struct prev_params *params)
213 {
214 struct isp_device *isp = to_isp_device(prev);
215 const struct omap3isp_prev_hmed *hmed = &params->hmed;
216
217 isp_reg_writel(isp, (hmed->odddist == 1 ? 0 : ISPPRV_HMED_ODDDIST) |
218 (hmed->evendist == 1 ? 0 : ISPPRV_HMED_EVENDIST) |
219 (hmed->thres << ISPPRV_HMED_THRESHOLD_SHIFT),
220 OMAP3_ISP_IOMEM_PREV, ISPPRV_HMED);
221 }
222
223 /*
224 * preview_enable_hmed - Enable/disable the Horizontal Median Filter
225 */
226 static void preview_enable_hmed(struct isp_prev_device *prev, bool enable)
227 {
228 struct isp_device *isp = to_isp_device(prev);
229
230 if (enable)
231 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
232 ISPPRV_PCR_HMEDEN);
233 else
234 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
235 ISPPRV_PCR_HMEDEN);
236 }
237
238 /*
239 * preview_config_cfa - Configure CFA Interpolation for Bayer formats
240 *
241 * The CFA table is organised in four blocks, one per Bayer component. The
242 * hardware expects blocks to follow the Bayer order of the input data, while
243 * the driver stores the table in GRBG order in memory. The blocks need to be
244 * reordered to support non-GRBG Bayer patterns.
245 */
246 static void preview_config_cfa(struct isp_prev_device *prev,
247 const struct prev_params *params)
248 {
249 static const unsigned int cfa_coef_order[4][4] = {
250 { 0, 1, 2, 3 }, /* GRBG */
251 { 1, 0, 3, 2 }, /* RGGB */
252 { 2, 3, 0, 1 }, /* BGGR */
253 { 3, 2, 1, 0 }, /* GBRG */
254 };
255 const unsigned int *order = cfa_coef_order[prev->params.cfa_order];
256 const struct omap3isp_prev_cfa *cfa = &params->cfa;
257 struct isp_device *isp = to_isp_device(prev);
258 unsigned int i;
259 unsigned int j;
260
261 isp_reg_writel(isp,
262 (cfa->gradthrs_vert << ISPPRV_CFA_GRADTH_VER_SHIFT) |
263 (cfa->gradthrs_horz << ISPPRV_CFA_GRADTH_HOR_SHIFT),
264 OMAP3_ISP_IOMEM_PREV, ISPPRV_CFA);
265
266 isp_reg_writel(isp, ISPPRV_CFA_TABLE_ADDR,
267 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
268
269 for (i = 0; i < 4; ++i) {
270 const __u32 *block = cfa->table[order[i]];
271
272 for (j = 0; j < OMAP3ISP_PREV_CFA_BLK_SIZE; ++j)
273 isp_reg_writel(isp, block[j], OMAP3_ISP_IOMEM_PREV,
274 ISPPRV_SET_TBL_DATA);
275 }
276 }
277
278 /*
279 * preview_config_chroma_suppression - Configure Chroma Suppression
280 */
281 static void
282 preview_config_chroma_suppression(struct isp_prev_device *prev,
283 const struct prev_params *params)
284 {
285 struct isp_device *isp = to_isp_device(prev);
286 const struct omap3isp_prev_csup *cs = &params->csup;
287
288 isp_reg_writel(isp,
289 cs->gain | (cs->thres << ISPPRV_CSUP_THRES_SHIFT) |
290 (cs->hypf_en << ISPPRV_CSUP_HPYF_SHIFT),
291 OMAP3_ISP_IOMEM_PREV, ISPPRV_CSUP);
292 }
293
294 /*
295 * preview_enable_chroma_suppression - Enable/disable Chrominance Suppression
296 */
297 static void
298 preview_enable_chroma_suppression(struct isp_prev_device *prev, bool enable)
299 {
300 struct isp_device *isp = to_isp_device(prev);
301
302 if (enable)
303 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
304 ISPPRV_PCR_SUPEN);
305 else
306 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
307 ISPPRV_PCR_SUPEN);
308 }
309
310 /*
311 * preview_config_whitebalance - Configure White Balance parameters
312 *
313 * Coefficient matrix always with default values.
314 */
315 static void
316 preview_config_whitebalance(struct isp_prev_device *prev,
317 const struct prev_params *params)
318 {
319 struct isp_device *isp = to_isp_device(prev);
320 const struct omap3isp_prev_wbal *wbal = &params->wbal;
321 u32 val;
322
323 isp_reg_writel(isp, wbal->dgain, OMAP3_ISP_IOMEM_PREV, ISPPRV_WB_DGAIN);
324
325 val = wbal->coef0 << ISPPRV_WBGAIN_COEF0_SHIFT;
326 val |= wbal->coef1 << ISPPRV_WBGAIN_COEF1_SHIFT;
327 val |= wbal->coef2 << ISPPRV_WBGAIN_COEF2_SHIFT;
328 val |= wbal->coef3 << ISPPRV_WBGAIN_COEF3_SHIFT;
329 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_WBGAIN);
330
331 isp_reg_writel(isp,
332 ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_0_SHIFT |
333 ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_1_SHIFT |
334 ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N0_2_SHIFT |
335 ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N0_3_SHIFT |
336 ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_0_SHIFT |
337 ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_1_SHIFT |
338 ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N1_2_SHIFT |
339 ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N1_3_SHIFT |
340 ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_0_SHIFT |
341 ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_1_SHIFT |
342 ISPPRV_WBSEL_COEF0 << ISPPRV_WBSEL_N2_2_SHIFT |
343 ISPPRV_WBSEL_COEF1 << ISPPRV_WBSEL_N2_3_SHIFT |
344 ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_0_SHIFT |
345 ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_1_SHIFT |
346 ISPPRV_WBSEL_COEF2 << ISPPRV_WBSEL_N3_2_SHIFT |
347 ISPPRV_WBSEL_COEF3 << ISPPRV_WBSEL_N3_3_SHIFT,
348 OMAP3_ISP_IOMEM_PREV, ISPPRV_WBSEL);
349 }
350
351 /*
352 * preview_config_blkadj - Configure Black Adjustment
353 */
354 static void
355 preview_config_blkadj(struct isp_prev_device *prev,
356 const struct prev_params *params)
357 {
358 struct isp_device *isp = to_isp_device(prev);
359 const struct omap3isp_prev_blkadj *blkadj = &params->blkadj;
360
361 isp_reg_writel(isp, (blkadj->blue << ISPPRV_BLKADJOFF_B_SHIFT) |
362 (blkadj->green << ISPPRV_BLKADJOFF_G_SHIFT) |
363 (blkadj->red << ISPPRV_BLKADJOFF_R_SHIFT),
364 OMAP3_ISP_IOMEM_PREV, ISPPRV_BLKADJOFF);
365 }
366
367 /*
368 * preview_config_rgb_blending - Configure RGB-RGB Blending
369 */
370 static void
371 preview_config_rgb_blending(struct isp_prev_device *prev,
372 const struct prev_params *params)
373 {
374 struct isp_device *isp = to_isp_device(prev);
375 const struct omap3isp_prev_rgbtorgb *rgbrgb = &params->rgb2rgb;
376 u32 val;
377
378 val = (rgbrgb->matrix[0][0] & 0xfff) << ISPPRV_RGB_MAT1_MTX_RR_SHIFT;
379 val |= (rgbrgb->matrix[0][1] & 0xfff) << ISPPRV_RGB_MAT1_MTX_GR_SHIFT;
380 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT1);
381
382 val = (rgbrgb->matrix[0][2] & 0xfff) << ISPPRV_RGB_MAT2_MTX_BR_SHIFT;
383 val |= (rgbrgb->matrix[1][0] & 0xfff) << ISPPRV_RGB_MAT2_MTX_RG_SHIFT;
384 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT2);
385
386 val = (rgbrgb->matrix[1][1] & 0xfff) << ISPPRV_RGB_MAT3_MTX_GG_SHIFT;
387 val |= (rgbrgb->matrix[1][2] & 0xfff) << ISPPRV_RGB_MAT3_MTX_BG_SHIFT;
388 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT3);
389
390 val = (rgbrgb->matrix[2][0] & 0xfff) << ISPPRV_RGB_MAT4_MTX_RB_SHIFT;
391 val |= (rgbrgb->matrix[2][1] & 0xfff) << ISPPRV_RGB_MAT4_MTX_GB_SHIFT;
392 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT4);
393
394 val = (rgbrgb->matrix[2][2] & 0xfff) << ISPPRV_RGB_MAT5_MTX_BB_SHIFT;
395 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_MAT5);
396
397 val = (rgbrgb->offset[0] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT;
398 val |= (rgbrgb->offset[1] & 0x3ff) << ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT;
399 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF1);
400
401 val = (rgbrgb->offset[2] & 0x3ff) << ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT;
402 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_RGB_OFF2);
403 }
404
405 /*
406 * preview_config_csc - Configure Color Space Conversion (RGB to YCbYCr)
407 */
408 static void
409 preview_config_csc(struct isp_prev_device *prev,
410 const struct prev_params *params)
411 {
412 struct isp_device *isp = to_isp_device(prev);
413 const struct omap3isp_prev_csc *csc = &params->csc;
414 u32 val;
415
416 val = (csc->matrix[0][0] & 0x3ff) << ISPPRV_CSC0_RY_SHIFT;
417 val |= (csc->matrix[0][1] & 0x3ff) << ISPPRV_CSC0_GY_SHIFT;
418 val |= (csc->matrix[0][2] & 0x3ff) << ISPPRV_CSC0_BY_SHIFT;
419 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC0);
420
421 val = (csc->matrix[1][0] & 0x3ff) << ISPPRV_CSC1_RCB_SHIFT;
422 val |= (csc->matrix[1][1] & 0x3ff) << ISPPRV_CSC1_GCB_SHIFT;
423 val |= (csc->matrix[1][2] & 0x3ff) << ISPPRV_CSC1_BCB_SHIFT;
424 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC1);
425
426 val = (csc->matrix[2][0] & 0x3ff) << ISPPRV_CSC2_RCR_SHIFT;
427 val |= (csc->matrix[2][1] & 0x3ff) << ISPPRV_CSC2_GCR_SHIFT;
428 val |= (csc->matrix[2][2] & 0x3ff) << ISPPRV_CSC2_BCR_SHIFT;
429 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC2);
430
431 val = (csc->offset[0] & 0xff) << ISPPRV_CSC_OFFSET_Y_SHIFT;
432 val |= (csc->offset[1] & 0xff) << ISPPRV_CSC_OFFSET_CB_SHIFT;
433 val |= (csc->offset[2] & 0xff) << ISPPRV_CSC_OFFSET_CR_SHIFT;
434 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_PREV, ISPPRV_CSC_OFFSET);
435 }
436
437 /*
438 * preview_config_yc_range - Configure the max and min Y and C values
439 */
440 static void
441 preview_config_yc_range(struct isp_prev_device *prev,
442 const struct prev_params *params)
443 {
444 struct isp_device *isp = to_isp_device(prev);
445 const struct omap3isp_prev_yclimit *yc = &params->yclimit;
446
447 isp_reg_writel(isp,
448 yc->maxC << ISPPRV_SETUP_YC_MAXC_SHIFT |
449 yc->maxY << ISPPRV_SETUP_YC_MAXY_SHIFT |
450 yc->minC << ISPPRV_SETUP_YC_MINC_SHIFT |
451 yc->minY << ISPPRV_SETUP_YC_MINY_SHIFT,
452 OMAP3_ISP_IOMEM_PREV, ISPPRV_SETUP_YC);
453 }
454
455 /*
456 * preview_config_dcor - Configure Couplet Defect Correction
457 */
458 static void
459 preview_config_dcor(struct isp_prev_device *prev,
460 const struct prev_params *params)
461 {
462 struct isp_device *isp = to_isp_device(prev);
463 const struct omap3isp_prev_dcor *dcor = &params->dcor;
464
465 isp_reg_writel(isp, dcor->detect_correct[0],
466 OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR0);
467 isp_reg_writel(isp, dcor->detect_correct[1],
468 OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR1);
469 isp_reg_writel(isp, dcor->detect_correct[2],
470 OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR2);
471 isp_reg_writel(isp, dcor->detect_correct[3],
472 OMAP3_ISP_IOMEM_PREV, ISPPRV_CDC_THR3);
473 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
474 ISPPRV_PCR_DCCOUP,
475 dcor->couplet_mode_en ? ISPPRV_PCR_DCCOUP : 0);
476 }
477
478 /*
479 * preview_enable_dcor - Enable/disable Couplet Defect Correction
480 */
481 static void preview_enable_dcor(struct isp_prev_device *prev, bool enable)
482 {
483 struct isp_device *isp = to_isp_device(prev);
484
485 if (enable)
486 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
487 ISPPRV_PCR_DCOREN);
488 else
489 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
490 ISPPRV_PCR_DCOREN);
491 }
492
493 /*
494 * preview_enable_drkframe_capture - Enable/disable Dark Frame Capture
495 */
496 static void
497 preview_enable_drkframe_capture(struct isp_prev_device *prev, bool enable)
498 {
499 struct isp_device *isp = to_isp_device(prev);
500
501 if (enable)
502 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
503 ISPPRV_PCR_DRKFCAP);
504 else
505 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
506 ISPPRV_PCR_DRKFCAP);
507 }
508
509 /*
510 * preview_enable_drkframe - Enable/disable Dark Frame Subtraction
511 */
512 static void preview_enable_drkframe(struct isp_prev_device *prev, bool enable)
513 {
514 struct isp_device *isp = to_isp_device(prev);
515
516 if (enable)
517 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
518 ISPPRV_PCR_DRKFEN);
519 else
520 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
521 ISPPRV_PCR_DRKFEN);
522 }
523
524 /*
525 * preview_config_noisefilter - Configure the Noise Filter
526 */
527 static void
528 preview_config_noisefilter(struct isp_prev_device *prev,
529 const struct prev_params *params)
530 {
531 struct isp_device *isp = to_isp_device(prev);
532 const struct omap3isp_prev_nf *nf = &params->nf;
533 unsigned int i;
534
535 isp_reg_writel(isp, nf->spread, OMAP3_ISP_IOMEM_PREV, ISPPRV_NF);
536 isp_reg_writel(isp, ISPPRV_NF_TABLE_ADDR,
537 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
538 for (i = 0; i < OMAP3ISP_PREV_NF_TBL_SIZE; i++) {
539 isp_reg_writel(isp, nf->table[i],
540 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_DATA);
541 }
542 }
543
544 /*
545 * preview_enable_noisefilter - Enable/disable the Noise Filter
546 */
547 static void
548 preview_enable_noisefilter(struct isp_prev_device *prev, bool enable)
549 {
550 struct isp_device *isp = to_isp_device(prev);
551
552 if (enable)
553 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
554 ISPPRV_PCR_NFEN);
555 else
556 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
557 ISPPRV_PCR_NFEN);
558 }
559
560 /*
561 * preview_config_gammacorrn - Configure the Gamma Correction tables
562 */
563 static void
564 preview_config_gammacorrn(struct isp_prev_device *prev,
565 const struct prev_params *params)
566 {
567 struct isp_device *isp = to_isp_device(prev);
568 const struct omap3isp_prev_gtables *gt = &params->gamma;
569 unsigned int i;
570
571 isp_reg_writel(isp, ISPPRV_REDGAMMA_TABLE_ADDR,
572 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
573 for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++)
574 isp_reg_writel(isp, gt->red[i], OMAP3_ISP_IOMEM_PREV,
575 ISPPRV_SET_TBL_DATA);
576
577 isp_reg_writel(isp, ISPPRV_GREENGAMMA_TABLE_ADDR,
578 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
579 for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++)
580 isp_reg_writel(isp, gt->green[i], OMAP3_ISP_IOMEM_PREV,
581 ISPPRV_SET_TBL_DATA);
582
583 isp_reg_writel(isp, ISPPRV_BLUEGAMMA_TABLE_ADDR,
584 OMAP3_ISP_IOMEM_PREV, ISPPRV_SET_TBL_ADDR);
585 for (i = 0; i < OMAP3ISP_PREV_GAMMA_TBL_SIZE; i++)
586 isp_reg_writel(isp, gt->blue[i], OMAP3_ISP_IOMEM_PREV,
587 ISPPRV_SET_TBL_DATA);
588 }
589
590 /*
591 * preview_enable_gammacorrn - Enable/disable Gamma Correction
592 *
593 * When gamma correction is disabled, the module is bypassed and its output is
594 * the 8 MSB of the 10-bit input .
595 */
596 static void
597 preview_enable_gammacorrn(struct isp_prev_device *prev, bool enable)
598 {
599 struct isp_device *isp = to_isp_device(prev);
600
601 if (enable)
602 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
603 ISPPRV_PCR_GAMMA_BYPASS);
604 else
605 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
606 ISPPRV_PCR_GAMMA_BYPASS);
607 }
608
609 /*
610 * preview_config_contrast - Configure the Contrast
611 *
612 * Value should be programmed before enabling the module.
613 */
614 static void
615 preview_config_contrast(struct isp_prev_device *prev,
616 const struct prev_params *params)
617 {
618 struct isp_device *isp = to_isp_device(prev);
619
620 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT,
621 0xff << ISPPRV_CNT_BRT_CNT_SHIFT,
622 params->contrast << ISPPRV_CNT_BRT_CNT_SHIFT);
623 }
624
625 /*
626 * preview_config_brightness - Configure the Brightness
627 */
628 static void
629 preview_config_brightness(struct isp_prev_device *prev,
630 const struct prev_params *params)
631 {
632 struct isp_device *isp = to_isp_device(prev);
633
634 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_CNT_BRT,
635 0xff << ISPPRV_CNT_BRT_BRT_SHIFT,
636 params->brightness << ISPPRV_CNT_BRT_BRT_SHIFT);
637 }
638
639 /*
640 * preview_update_contrast - Updates the contrast.
641 * @contrast: Pointer to hold the current programmed contrast value.
642 *
643 * Value should be programmed before enabling the module.
644 */
645 static void
646 preview_update_contrast(struct isp_prev_device *prev, u8 contrast)
647 {
648 struct prev_params *params;
649 unsigned long flags;
650
651 spin_lock_irqsave(&prev->params.lock, flags);
652 params = (prev->params.active & OMAP3ISP_PREV_CONTRAST)
653 ? &prev->params.params[0] : &prev->params.params[1];
654
655 if (params->contrast != (contrast * ISPPRV_CONTRAST_UNITS)) {
656 params->contrast = contrast * ISPPRV_CONTRAST_UNITS;
657 params->update |= OMAP3ISP_PREV_CONTRAST;
658 }
659 spin_unlock_irqrestore(&prev->params.lock, flags);
660 }
661
662 /*
663 * preview_update_brightness - Updates the brightness in preview module.
664 * @brightness: Pointer to hold the current programmed brightness value.
665 *
666 */
667 static void
668 preview_update_brightness(struct isp_prev_device *prev, u8 brightness)
669 {
670 struct prev_params *params;
671 unsigned long flags;
672
673 spin_lock_irqsave(&prev->params.lock, flags);
674 params = (prev->params.active & OMAP3ISP_PREV_BRIGHTNESS)
675 ? &prev->params.params[0] : &prev->params.params[1];
676
677 if (params->brightness != (brightness * ISPPRV_BRIGHT_UNITS)) {
678 params->brightness = brightness * ISPPRV_BRIGHT_UNITS;
679 params->update |= OMAP3ISP_PREV_BRIGHTNESS;
680 }
681 spin_unlock_irqrestore(&prev->params.lock, flags);
682 }
683
684 static u32
685 preview_params_lock(struct isp_prev_device *prev, u32 update, bool shadow)
686 {
687 u32 active = prev->params.active;
688
689 if (shadow) {
690 /* Mark all shadow parameters we are going to touch as busy. */
691 prev->params.params[0].busy |= ~active & update;
692 prev->params.params[1].busy |= active & update;
693 } else {
694 /* Mark all active parameters we are going to touch as busy. */
695 update = (prev->params.params[0].update & active)
696 | (prev->params.params[1].update & ~active);
697
698 prev->params.params[0].busy |= active & update;
699 prev->params.params[1].busy |= ~active & update;
700 }
701
702 return update;
703 }
704
705 static void
706 preview_params_unlock(struct isp_prev_device *prev, u32 update, bool shadow)
707 {
708 u32 active = prev->params.active;
709
710 if (shadow) {
711 /* Set the update flag for shadow parameters that have been
712 * updated and clear the busy flag for all shadow parameters.
713 */
714 prev->params.params[0].update |= (~active & update);
715 prev->params.params[1].update |= (active & update);
716 prev->params.params[0].busy &= active;
717 prev->params.params[1].busy &= ~active;
718 } else {
719 /* Clear the update flag for active parameters that have been
720 * applied and the busy flag for all active parameters.
721 */
722 prev->params.params[0].update &= ~(active & update);
723 prev->params.params[1].update &= ~(~active & update);
724 prev->params.params[0].busy &= ~active;
725 prev->params.params[1].busy &= active;
726 }
727 }
728
729 static void preview_params_switch(struct isp_prev_device *prev)
730 {
731 u32 to_switch;
732
733 /* Switch active parameters with updated shadow parameters when the
734 * shadow parameter has been updated and neither the active not the
735 * shadow parameter is busy.
736 */
737 to_switch = (prev->params.params[0].update & ~prev->params.active)
738 | (prev->params.params[1].update & prev->params.active);
739 to_switch &= ~(prev->params.params[0].busy |
740 prev->params.params[1].busy);
741 if (to_switch == 0)
742 return;
743
744 prev->params.active ^= to_switch;
745
746 /* Remove the update flag for the shadow copy of parameters we have
747 * switched.
748 */
749 prev->params.params[0].update &= ~(~prev->params.active & to_switch);
750 prev->params.params[1].update &= ~(prev->params.active & to_switch);
751 }
752
753 /* preview parameters update structure */
754 struct preview_update {
755 void (*config)(struct isp_prev_device *, const struct prev_params *);
756 void (*enable)(struct isp_prev_device *, bool);
757 unsigned int param_offset;
758 unsigned int param_size;
759 unsigned int config_offset;
760 bool skip;
761 };
762
763 /* Keep the array indexed by the OMAP3ISP_PREV_* bit number. */
764 static const struct preview_update update_attrs[] = {
765 /* OMAP3ISP_PREV_LUMAENH */ {
766 preview_config_luma_enhancement,
767 preview_enable_luma_enhancement,
768 offsetof(struct prev_params, luma),
769 FIELD_SIZEOF(struct prev_params, luma),
770 offsetof(struct omap3isp_prev_update_config, luma),
771 }, /* OMAP3ISP_PREV_INVALAW */ {
772 NULL,
773 preview_enable_invalaw,
774 }, /* OMAP3ISP_PREV_HRZ_MED */ {
775 preview_config_hmed,
776 preview_enable_hmed,
777 offsetof(struct prev_params, hmed),
778 FIELD_SIZEOF(struct prev_params, hmed),
779 offsetof(struct omap3isp_prev_update_config, hmed),
780 }, /* OMAP3ISP_PREV_CFA */ {
781 preview_config_cfa,
782 NULL,
783 offsetof(struct prev_params, cfa),
784 FIELD_SIZEOF(struct prev_params, cfa),
785 offsetof(struct omap3isp_prev_update_config, cfa),
786 }, /* OMAP3ISP_PREV_CHROMA_SUPP */ {
787 preview_config_chroma_suppression,
788 preview_enable_chroma_suppression,
789 offsetof(struct prev_params, csup),
790 FIELD_SIZEOF(struct prev_params, csup),
791 offsetof(struct omap3isp_prev_update_config, csup),
792 }, /* OMAP3ISP_PREV_WB */ {
793 preview_config_whitebalance,
794 NULL,
795 offsetof(struct prev_params, wbal),
796 FIELD_SIZEOF(struct prev_params, wbal),
797 offsetof(struct omap3isp_prev_update_config, wbal),
798 }, /* OMAP3ISP_PREV_BLKADJ */ {
799 preview_config_blkadj,
800 NULL,
801 offsetof(struct prev_params, blkadj),
802 FIELD_SIZEOF(struct prev_params, blkadj),
803 offsetof(struct omap3isp_prev_update_config, blkadj),
804 }, /* OMAP3ISP_PREV_RGB2RGB */ {
805 preview_config_rgb_blending,
806 NULL,
807 offsetof(struct prev_params, rgb2rgb),
808 FIELD_SIZEOF(struct prev_params, rgb2rgb),
809 offsetof(struct omap3isp_prev_update_config, rgb2rgb),
810 }, /* OMAP3ISP_PREV_COLOR_CONV */ {
811 preview_config_csc,
812 NULL,
813 offsetof(struct prev_params, csc),
814 FIELD_SIZEOF(struct prev_params, csc),
815 offsetof(struct omap3isp_prev_update_config, csc),
816 }, /* OMAP3ISP_PREV_YC_LIMIT */ {
817 preview_config_yc_range,
818 NULL,
819 offsetof(struct prev_params, yclimit),
820 FIELD_SIZEOF(struct prev_params, yclimit),
821 offsetof(struct omap3isp_prev_update_config, yclimit),
822 }, /* OMAP3ISP_PREV_DEFECT_COR */ {
823 preview_config_dcor,
824 preview_enable_dcor,
825 offsetof(struct prev_params, dcor),
826 FIELD_SIZEOF(struct prev_params, dcor),
827 offsetof(struct omap3isp_prev_update_config, dcor),
828 }, /* Previously OMAP3ISP_PREV_GAMMABYPASS, not used anymore */ {
829 NULL,
830 NULL,
831 }, /* OMAP3ISP_PREV_DRK_FRM_CAPTURE */ {
832 NULL,
833 preview_enable_drkframe_capture,
834 }, /* OMAP3ISP_PREV_DRK_FRM_SUBTRACT */ {
835 NULL,
836 preview_enable_drkframe,
837 }, /* OMAP3ISP_PREV_LENS_SHADING */ {
838 NULL,
839 preview_enable_drkframe,
840 }, /* OMAP3ISP_PREV_NF */ {
841 preview_config_noisefilter,
842 preview_enable_noisefilter,
843 offsetof(struct prev_params, nf),
844 FIELD_SIZEOF(struct prev_params, nf),
845 offsetof(struct omap3isp_prev_update_config, nf),
846 }, /* OMAP3ISP_PREV_GAMMA */ {
847 preview_config_gammacorrn,
848 preview_enable_gammacorrn,
849 offsetof(struct prev_params, gamma),
850 FIELD_SIZEOF(struct prev_params, gamma),
851 offsetof(struct omap3isp_prev_update_config, gamma),
852 }, /* OMAP3ISP_PREV_CONTRAST */ {
853 preview_config_contrast,
854 NULL,
855 0, 0, 0, true,
856 }, /* OMAP3ISP_PREV_BRIGHTNESS */ {
857 preview_config_brightness,
858 NULL,
859 0, 0, 0, true,
860 },
861 };
862
863 /*
864 * preview_config - Copy and update local structure with userspace preview
865 * configuration.
866 * @prev: ISP preview engine
867 * @cfg: Configuration
868 *
869 * Return zero if success or -EFAULT if the configuration can't be copied from
870 * userspace.
871 */
872 static int preview_config(struct isp_prev_device *prev,
873 struct omap3isp_prev_update_config *cfg)
874 {
875 unsigned long flags;
876 unsigned int i;
877 int rval = 0;
878 u32 update;
879 u32 active;
880
881 if (cfg->update == 0)
882 return 0;
883
884 /* Mark the shadow parameters we're going to update as busy. */
885 spin_lock_irqsave(&prev->params.lock, flags);
886 preview_params_lock(prev, cfg->update, true);
887 active = prev->params.active;
888 spin_unlock_irqrestore(&prev->params.lock, flags);
889
890 update = 0;
891
892 for (i = 0; i < ARRAY_SIZE(update_attrs); i++) {
893 const struct preview_update *attr = &update_attrs[i];
894 struct prev_params *params;
895 unsigned int bit = 1 << i;
896
897 if (attr->skip || !(cfg->update & bit))
898 continue;
899
900 params = &prev->params.params[!!(active & bit)];
901
902 if (cfg->flag & bit) {
903 void __user *from = *(void * __user *)
904 ((void *)cfg + attr->config_offset);
905 void *to = (void *)params + attr->param_offset;
906 size_t size = attr->param_size;
907
908 if (to && from && size) {
909 if (copy_from_user(to, from, size)) {
910 rval = -EFAULT;
911 break;
912 }
913 }
914 params->features |= bit;
915 } else {
916 params->features &= ~bit;
917 }
918
919 update |= bit;
920 }
921
922 spin_lock_irqsave(&prev->params.lock, flags);
923 preview_params_unlock(prev, update, true);
924 preview_params_switch(prev);
925 spin_unlock_irqrestore(&prev->params.lock, flags);
926
927 return rval;
928 }
929
930 /*
931 * preview_setup_hw - Setup preview registers and/or internal memory
932 * @prev: pointer to preview private structure
933 * @update: Bitmask of parameters to setup
934 * @active: Bitmask of parameters active in set 0
935 * Note: can be called from interrupt context
936 * Return none
937 */
938 static void preview_setup_hw(struct isp_prev_device *prev, u32 update,
939 u32 active)
940 {
941 unsigned int i;
942 u32 features;
943
944 if (update == 0)
945 return;
946
947 features = (prev->params.params[0].features & active)
948 | (prev->params.params[1].features & ~active);
949
950 for (i = 0; i < ARRAY_SIZE(update_attrs); i++) {
951 const struct preview_update *attr = &update_attrs[i];
952 struct prev_params *params;
953 unsigned int bit = 1 << i;
954
955 if (!(update & bit))
956 continue;
957
958 params = &prev->params.params[!(active & bit)];
959
960 if (params->features & bit) {
961 if (attr->config)
962 attr->config(prev, params);
963 if (attr->enable)
964 attr->enable(prev, true);
965 } else {
966 if (attr->enable)
967 attr->enable(prev, false);
968 }
969 }
970 }
971
972 /*
973 * preview_config_ycpos - Configure byte layout of YUV image.
974 * @mode: Indicates the required byte layout.
975 */
976 static void
977 preview_config_ycpos(struct isp_prev_device *prev,
978 enum v4l2_mbus_pixelcode pixelcode)
979 {
980 struct isp_device *isp = to_isp_device(prev);
981 enum preview_ycpos_mode mode;
982
983 switch (pixelcode) {
984 case V4L2_MBUS_FMT_YUYV8_1X16:
985 mode = YCPOS_CrYCbY;
986 break;
987 case V4L2_MBUS_FMT_UYVY8_1X16:
988 mode = YCPOS_YCrYCb;
989 break;
990 default:
991 return;
992 }
993
994 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
995 ISPPRV_PCR_YCPOS_CrYCbY,
996 mode << ISPPRV_PCR_YCPOS_SHIFT);
997 }
998
999 /*
1000 * preview_config_averager - Enable / disable / configure averager
1001 * @average: Average value to be configured.
1002 */
1003 static void preview_config_averager(struct isp_prev_device *prev, u8 average)
1004 {
1005 struct isp_device *isp = to_isp_device(prev);
1006
1007 isp_reg_writel(isp, ISPPRV_AVE_EVENDIST_2 << ISPPRV_AVE_EVENDIST_SHIFT |
1008 ISPPRV_AVE_ODDDIST_2 << ISPPRV_AVE_ODDDIST_SHIFT |
1009 average, OMAP3_ISP_IOMEM_PREV, ISPPRV_AVE);
1010 }
1011
1012
1013 /*
1014 * preview_config_input_format - Configure the input format
1015 * @prev: The preview engine
1016 * @info: Sink pad format information
1017 *
1018 * Enable and configure CFA interpolation for Bayer formats and disable it for
1019 * greyscale formats.
1020 *
1021 * The CFA table is organised in four blocks, one per Bayer component. The
1022 * hardware expects blocks to follow the Bayer order of the input data, while
1023 * the driver stores the table in GRBG order in memory. The blocks need to be
1024 * reordered to support non-GRBG Bayer patterns.
1025 */
1026 static void preview_config_input_format(struct isp_prev_device *prev,
1027 const struct isp_format_info *info)
1028 {
1029 struct isp_device *isp = to_isp_device(prev);
1030 struct prev_params *params;
1031
1032 if (info->width == 8)
1033 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1034 ISPPRV_PCR_WIDTH);
1035 else
1036 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1037 ISPPRV_PCR_WIDTH);
1038
1039 switch (info->flavor) {
1040 case V4L2_MBUS_FMT_SGRBG8_1X8:
1041 prev->params.cfa_order = 0;
1042 break;
1043 case V4L2_MBUS_FMT_SRGGB8_1X8:
1044 prev->params.cfa_order = 1;
1045 break;
1046 case V4L2_MBUS_FMT_SBGGR8_1X8:
1047 prev->params.cfa_order = 2;
1048 break;
1049 case V4L2_MBUS_FMT_SGBRG8_1X8:
1050 prev->params.cfa_order = 3;
1051 break;
1052 default:
1053 /* Disable CFA for non-Bayer formats. */
1054 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1055 ISPPRV_PCR_CFAEN);
1056 return;
1057 }
1058
1059 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR, ISPPRV_PCR_CFAEN);
1060 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1061 ISPPRV_PCR_CFAFMT_MASK, ISPPRV_PCR_CFAFMT_BAYER);
1062
1063 params = (prev->params.active & OMAP3ISP_PREV_CFA)
1064 ? &prev->params.params[0] : &prev->params.params[1];
1065
1066 preview_config_cfa(prev, params);
1067 }
1068
1069 /*
1070 * preview_config_input_size - Configure the input frame size
1071 *
1072 * The preview engine crops several rows and columns internally depending on
1073 * which processing blocks are enabled. The driver assumes all those blocks are
1074 * enabled when reporting source pad formats to userspace. If this assumption is
1075 * not true, rows and columns must be manually cropped at the preview engine
1076 * input to avoid overflows at the end of lines and frames.
1077 *
1078 * See the explanation at the PREV_MARGIN_* definitions for more details.
1079 */
1080 static void preview_config_input_size(struct isp_prev_device *prev, u32 active)
1081 {
1082 struct isp_device *isp = to_isp_device(prev);
1083 unsigned int sph = prev->crop.left;
1084 unsigned int eph = prev->crop.left + prev->crop.width - 1;
1085 unsigned int slv = prev->crop.top;
1086 unsigned int elv = prev->crop.top + prev->crop.height - 1;
1087 u32 features;
1088
1089 features = (prev->params.params[0].features & active)
1090 | (prev->params.params[1].features & ~active);
1091
1092 if (features & (OMAP3ISP_PREV_DEFECT_COR | OMAP3ISP_PREV_NF)) {
1093 sph -= 2;
1094 eph += 2;
1095 slv -= 2;
1096 elv += 2;
1097 }
1098 if (features & OMAP3ISP_PREV_HRZ_MED) {
1099 sph -= 2;
1100 eph += 2;
1101 }
1102 if (features & (OMAP3ISP_PREV_CHROMA_SUPP | OMAP3ISP_PREV_LUMAENH))
1103 sph -= 2;
1104
1105 isp_reg_writel(isp, (sph << ISPPRV_HORZ_INFO_SPH_SHIFT) | eph,
1106 OMAP3_ISP_IOMEM_PREV, ISPPRV_HORZ_INFO);
1107 isp_reg_writel(isp, (slv << ISPPRV_VERT_INFO_SLV_SHIFT) | elv,
1108 OMAP3_ISP_IOMEM_PREV, ISPPRV_VERT_INFO);
1109 }
1110
1111 /*
1112 * preview_config_inlineoffset - Configures the Read address line offset.
1113 * @prev: Preview module
1114 * @offset: Line offset
1115 *
1116 * According to the TRM, the line offset must be aligned on a 32 bytes boundary.
1117 * However, a hardware bug requires the memory start address to be aligned on a
1118 * 64 bytes boundary, so the offset probably should be aligned on 64 bytes as
1119 * well.
1120 */
1121 static void
1122 preview_config_inlineoffset(struct isp_prev_device *prev, u32 offset)
1123 {
1124 struct isp_device *isp = to_isp_device(prev);
1125
1126 isp_reg_writel(isp, offset & 0xffff, OMAP3_ISP_IOMEM_PREV,
1127 ISPPRV_RADR_OFFSET);
1128 }
1129
1130 /*
1131 * preview_set_inaddr - Sets memory address of input frame.
1132 * @addr: 32bit memory address aligned on 32byte boundary.
1133 *
1134 * Configures the memory address from which the input frame is to be read.
1135 */
1136 static void preview_set_inaddr(struct isp_prev_device *prev, u32 addr)
1137 {
1138 struct isp_device *isp = to_isp_device(prev);
1139
1140 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_RSDR_ADDR);
1141 }
1142
1143 /*
1144 * preview_config_outlineoffset - Configures the Write address line offset.
1145 * @offset: Line Offset for the preview output.
1146 *
1147 * The offset must be a multiple of 32 bytes.
1148 */
1149 static void preview_config_outlineoffset(struct isp_prev_device *prev,
1150 u32 offset)
1151 {
1152 struct isp_device *isp = to_isp_device(prev);
1153
1154 isp_reg_writel(isp, offset & 0xffff, OMAP3_ISP_IOMEM_PREV,
1155 ISPPRV_WADD_OFFSET);
1156 }
1157
1158 /*
1159 * preview_set_outaddr - Sets the memory address to store output frame
1160 * @addr: 32bit memory address aligned on 32byte boundary.
1161 *
1162 * Configures the memory address to which the output frame is written.
1163 */
1164 static void preview_set_outaddr(struct isp_prev_device *prev, u32 addr)
1165 {
1166 struct isp_device *isp = to_isp_device(prev);
1167
1168 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_PREV, ISPPRV_WSDR_ADDR);
1169 }
1170
1171 static void preview_adjust_bandwidth(struct isp_prev_device *prev)
1172 {
1173 struct isp_pipeline *pipe = to_isp_pipeline(&prev->subdev.entity);
1174 struct isp_device *isp = to_isp_device(prev);
1175 const struct v4l2_mbus_framefmt *ifmt = &prev->formats[PREV_PAD_SINK];
1176 unsigned long l3_ick = pipe->l3_ick;
1177 struct v4l2_fract *timeperframe;
1178 unsigned int cycles_per_frame;
1179 unsigned int requests_per_frame;
1180 unsigned int cycles_per_request;
1181 unsigned int minimum;
1182 unsigned int maximum;
1183 unsigned int value;
1184
1185 if (prev->input != PREVIEW_INPUT_MEMORY) {
1186 isp_reg_clr(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_SDR_REQ_EXP,
1187 ISPSBL_SDR_REQ_PRV_EXP_MASK);
1188 return;
1189 }
1190
1191 /* Compute the minimum number of cycles per request, based on the
1192 * pipeline maximum data rate. This is an absolute lower bound if we
1193 * don't want SBL overflows, so round the value up.
1194 */
1195 cycles_per_request = div_u64((u64)l3_ick / 2 * 256 + pipe->max_rate - 1,
1196 pipe->max_rate);
1197 minimum = DIV_ROUND_UP(cycles_per_request, 32);
1198
1199 /* Compute the maximum number of cycles per request, based on the
1200 * requested frame rate. This is a soft upper bound to achieve a frame
1201 * rate equal or higher than the requested value, so round the value
1202 * down.
1203 */
1204 timeperframe = &pipe->max_timeperframe;
1205
1206 requests_per_frame = DIV_ROUND_UP(ifmt->width * 2, 256) * ifmt->height;
1207 cycles_per_frame = div_u64((u64)l3_ick * timeperframe->numerator,
1208 timeperframe->denominator);
1209 cycles_per_request = cycles_per_frame / requests_per_frame;
1210
1211 maximum = cycles_per_request / 32;
1212
1213 value = max(minimum, maximum);
1214
1215 dev_dbg(isp->dev, "%s: cycles per request = %u\n", __func__, value);
1216 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_SDR_REQ_EXP,
1217 ISPSBL_SDR_REQ_PRV_EXP_MASK,
1218 value << ISPSBL_SDR_REQ_PRV_EXP_SHIFT);
1219 }
1220
1221 /*
1222 * omap3isp_preview_busy - Gets busy state of preview module.
1223 */
1224 int omap3isp_preview_busy(struct isp_prev_device *prev)
1225 {
1226 struct isp_device *isp = to_isp_device(prev);
1227
1228 return isp_reg_readl(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR)
1229 & ISPPRV_PCR_BUSY;
1230 }
1231
1232 /*
1233 * omap3isp_preview_restore_context - Restores the values of preview registers
1234 */
1235 void omap3isp_preview_restore_context(struct isp_device *isp)
1236 {
1237 struct isp_prev_device *prev = &isp->isp_prev;
1238 const u32 update = OMAP3ISP_PREV_FEATURES_END - 1;
1239
1240 prev->params.params[0].update = prev->params.active & update;
1241 prev->params.params[1].update = ~prev->params.active & update;
1242
1243 preview_setup_hw(prev, update, prev->params.active);
1244
1245 prev->params.params[0].update = 0;
1246 prev->params.params[1].update = 0;
1247 }
1248
1249 /*
1250 * preview_print_status - Dump preview module registers to the kernel log
1251 */
1252 #define PREV_PRINT_REGISTER(isp, name)\
1253 dev_dbg(isp->dev, "###PRV " #name "=0x%08x\n", \
1254 isp_reg_readl(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_##name))
1255
1256 static void preview_print_status(struct isp_prev_device *prev)
1257 {
1258 struct isp_device *isp = to_isp_device(prev);
1259
1260 dev_dbg(isp->dev, "-------------Preview Register dump----------\n");
1261
1262 PREV_PRINT_REGISTER(isp, PCR);
1263 PREV_PRINT_REGISTER(isp, HORZ_INFO);
1264 PREV_PRINT_REGISTER(isp, VERT_INFO);
1265 PREV_PRINT_REGISTER(isp, RSDR_ADDR);
1266 PREV_PRINT_REGISTER(isp, RADR_OFFSET);
1267 PREV_PRINT_REGISTER(isp, DSDR_ADDR);
1268 PREV_PRINT_REGISTER(isp, DRKF_OFFSET);
1269 PREV_PRINT_REGISTER(isp, WSDR_ADDR);
1270 PREV_PRINT_REGISTER(isp, WADD_OFFSET);
1271 PREV_PRINT_REGISTER(isp, AVE);
1272 PREV_PRINT_REGISTER(isp, HMED);
1273 PREV_PRINT_REGISTER(isp, NF);
1274 PREV_PRINT_REGISTER(isp, WB_DGAIN);
1275 PREV_PRINT_REGISTER(isp, WBGAIN);
1276 PREV_PRINT_REGISTER(isp, WBSEL);
1277 PREV_PRINT_REGISTER(isp, CFA);
1278 PREV_PRINT_REGISTER(isp, BLKADJOFF);
1279 PREV_PRINT_REGISTER(isp, RGB_MAT1);
1280 PREV_PRINT_REGISTER(isp, RGB_MAT2);
1281 PREV_PRINT_REGISTER(isp, RGB_MAT3);
1282 PREV_PRINT_REGISTER(isp, RGB_MAT4);
1283 PREV_PRINT_REGISTER(isp, RGB_MAT5);
1284 PREV_PRINT_REGISTER(isp, RGB_OFF1);
1285 PREV_PRINT_REGISTER(isp, RGB_OFF2);
1286 PREV_PRINT_REGISTER(isp, CSC0);
1287 PREV_PRINT_REGISTER(isp, CSC1);
1288 PREV_PRINT_REGISTER(isp, CSC2);
1289 PREV_PRINT_REGISTER(isp, CSC_OFFSET);
1290 PREV_PRINT_REGISTER(isp, CNT_BRT);
1291 PREV_PRINT_REGISTER(isp, CSUP);
1292 PREV_PRINT_REGISTER(isp, SETUP_YC);
1293 PREV_PRINT_REGISTER(isp, SET_TBL_ADDR);
1294 PREV_PRINT_REGISTER(isp, CDC_THR0);
1295 PREV_PRINT_REGISTER(isp, CDC_THR1);
1296 PREV_PRINT_REGISTER(isp, CDC_THR2);
1297 PREV_PRINT_REGISTER(isp, CDC_THR3);
1298
1299 dev_dbg(isp->dev, "--------------------------------------------\n");
1300 }
1301
1302 /*
1303 * preview_init_params - init image processing parameters.
1304 * @prev: pointer to previewer private structure
1305 */
1306 static void preview_init_params(struct isp_prev_device *prev)
1307 {
1308 struct prev_params *params;
1309 unsigned int i;
1310
1311 spin_lock_init(&prev->params.lock);
1312
1313 prev->params.active = ~0;
1314 prev->params.params[0].busy = 0;
1315 prev->params.params[0].update = OMAP3ISP_PREV_FEATURES_END - 1;
1316 prev->params.params[1].busy = 0;
1317 prev->params.params[1].update = 0;
1318
1319 params = &prev->params.params[0];
1320
1321 /* Init values */
1322 params->contrast = ISPPRV_CONTRAST_DEF * ISPPRV_CONTRAST_UNITS;
1323 params->brightness = ISPPRV_BRIGHT_DEF * ISPPRV_BRIGHT_UNITS;
1324 params->cfa.format = OMAP3ISP_CFAFMT_BAYER;
1325 memcpy(params->cfa.table, cfa_coef_table,
1326 sizeof(params->cfa.table));
1327 params->cfa.gradthrs_horz = FLR_CFA_GRADTHRS_HORZ;
1328 params->cfa.gradthrs_vert = FLR_CFA_GRADTHRS_VERT;
1329 params->csup.gain = FLR_CSUP_GAIN;
1330 params->csup.thres = FLR_CSUP_THRES;
1331 params->csup.hypf_en = 0;
1332 memcpy(params->luma.table, luma_enhance_table,
1333 sizeof(params->luma.table));
1334 params->nf.spread = FLR_NF_STRGTH;
1335 memcpy(params->nf.table, noise_filter_table, sizeof(params->nf.table));
1336 params->dcor.couplet_mode_en = 1;
1337 for (i = 0; i < OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS; i++)
1338 params->dcor.detect_correct[i] = DEF_DETECT_CORRECT_VAL;
1339 memcpy(params->gamma.blue, gamma_table, sizeof(params->gamma.blue));
1340 memcpy(params->gamma.green, gamma_table, sizeof(params->gamma.green));
1341 memcpy(params->gamma.red, gamma_table, sizeof(params->gamma.red));
1342 params->wbal.dgain = FLR_WBAL_DGAIN;
1343 params->wbal.coef0 = FLR_WBAL_COEF;
1344 params->wbal.coef1 = FLR_WBAL_COEF;
1345 params->wbal.coef2 = FLR_WBAL_COEF;
1346 params->wbal.coef3 = FLR_WBAL_COEF;
1347 params->blkadj.red = FLR_BLKADJ_RED;
1348 params->blkadj.green = FLR_BLKADJ_GREEN;
1349 params->blkadj.blue = FLR_BLKADJ_BLUE;
1350 params->rgb2rgb = flr_rgb2rgb;
1351 params->csc = flr_prev_csc;
1352 params->yclimit.minC = ISPPRV_YC_MIN;
1353 params->yclimit.maxC = ISPPRV_YC_MAX;
1354 params->yclimit.minY = ISPPRV_YC_MIN;
1355 params->yclimit.maxY = ISPPRV_YC_MAX;
1356
1357 params->features = OMAP3ISP_PREV_CFA | OMAP3ISP_PREV_DEFECT_COR
1358 | OMAP3ISP_PREV_NF | OMAP3ISP_PREV_GAMMA
1359 | OMAP3ISP_PREV_BLKADJ | OMAP3ISP_PREV_YC_LIMIT
1360 | OMAP3ISP_PREV_RGB2RGB | OMAP3ISP_PREV_COLOR_CONV
1361 | OMAP3ISP_PREV_WB | OMAP3ISP_PREV_BRIGHTNESS
1362 | OMAP3ISP_PREV_CONTRAST;
1363 }
1364
1365 /*
1366 * preview_max_out_width - Handle previewer hardware ouput limitations
1367 * @isp_revision : ISP revision
1368 * returns maximum width output for current isp revision
1369 */
1370 static unsigned int preview_max_out_width(struct isp_prev_device *prev)
1371 {
1372 struct isp_device *isp = to_isp_device(prev);
1373
1374 switch (isp->revision) {
1375 case ISP_REVISION_1_0:
1376 return PREV_MAX_OUT_WIDTH_REV_1;
1377
1378 case ISP_REVISION_2_0:
1379 default:
1380 return PREV_MAX_OUT_WIDTH_REV_2;
1381
1382 case ISP_REVISION_15_0:
1383 return PREV_MAX_OUT_WIDTH_REV_15;
1384 }
1385 }
1386
1387 static void preview_configure(struct isp_prev_device *prev)
1388 {
1389 struct isp_device *isp = to_isp_device(prev);
1390 const struct isp_format_info *info;
1391 struct v4l2_mbus_framefmt *format;
1392 unsigned long flags;
1393 u32 update;
1394 u32 active;
1395
1396 spin_lock_irqsave(&prev->params.lock, flags);
1397 /* Mark all active parameters we are going to touch as busy. */
1398 update = preview_params_lock(prev, 0, false);
1399 active = prev->params.active;
1400 spin_unlock_irqrestore(&prev->params.lock, flags);
1401
1402 /* PREV_PAD_SINK */
1403 format = &prev->formats[PREV_PAD_SINK];
1404 info = omap3isp_video_format_info(format->code);
1405
1406 preview_adjust_bandwidth(prev);
1407
1408 preview_config_input_format(prev, info);
1409 preview_config_input_size(prev, active);
1410
1411 if (prev->input == PREVIEW_INPUT_CCDC)
1412 preview_config_inlineoffset(prev, 0);
1413 else
1414 preview_config_inlineoffset(prev, ALIGN(format->width, 0x20) *
1415 info->bpp);
1416
1417 preview_setup_hw(prev, update, active);
1418
1419 /* PREV_PAD_SOURCE */
1420 format = &prev->formats[PREV_PAD_SOURCE];
1421
1422 if (prev->output & PREVIEW_OUTPUT_MEMORY)
1423 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1424 ISPPRV_PCR_SDRPORT);
1425 else
1426 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1427 ISPPRV_PCR_SDRPORT);
1428
1429 if (prev->output & PREVIEW_OUTPUT_RESIZER)
1430 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1431 ISPPRV_PCR_RSZPORT);
1432 else
1433 isp_reg_clr(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1434 ISPPRV_PCR_RSZPORT);
1435
1436 if (prev->output & PREVIEW_OUTPUT_MEMORY)
1437 preview_config_outlineoffset(prev,
1438 ALIGN(format->width, 0x10) * 2);
1439
1440 preview_config_averager(prev, 0);
1441 preview_config_ycpos(prev, format->code);
1442
1443 spin_lock_irqsave(&prev->params.lock, flags);
1444 preview_params_unlock(prev, update, false);
1445 spin_unlock_irqrestore(&prev->params.lock, flags);
1446 }
1447
1448 /* -----------------------------------------------------------------------------
1449 * Interrupt handling
1450 */
1451
1452 static void preview_enable_oneshot(struct isp_prev_device *prev)
1453 {
1454 struct isp_device *isp = to_isp_device(prev);
1455
1456 /* The PCR.SOURCE bit is automatically reset to 0 when the PCR.ENABLE
1457 * bit is set. As the preview engine is used in single-shot mode, we
1458 * need to set PCR.SOURCE before enabling the preview engine.
1459 */
1460 if (prev->input == PREVIEW_INPUT_MEMORY)
1461 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1462 ISPPRV_PCR_SOURCE);
1463
1464 isp_reg_set(isp, OMAP3_ISP_IOMEM_PREV, ISPPRV_PCR,
1465 ISPPRV_PCR_EN | ISPPRV_PCR_ONESHOT);
1466 }
1467
1468 void omap3isp_preview_isr_frame_sync(struct isp_prev_device *prev)
1469 {
1470 /*
1471 * If ISP_VIDEO_DMAQUEUE_QUEUED is set, DMA queue had an underrun
1472 * condition, the module was paused and now we have a buffer queued
1473 * on the output again. Restart the pipeline if running in continuous
1474 * mode.
1475 */
1476 if (prev->state == ISP_PIPELINE_STREAM_CONTINUOUS &&
1477 prev->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED) {
1478 preview_enable_oneshot(prev);
1479 isp_video_dmaqueue_flags_clr(&prev->video_out);
1480 }
1481 }
1482
1483 static void preview_isr_buffer(struct isp_prev_device *prev)
1484 {
1485 struct isp_pipeline *pipe = to_isp_pipeline(&prev->subdev.entity);
1486 struct isp_buffer *buffer;
1487 int restart = 0;
1488
1489 if (prev->input == PREVIEW_INPUT_MEMORY) {
1490 buffer = omap3isp_video_buffer_next(&prev->video_in);
1491 if (buffer != NULL)
1492 preview_set_inaddr(prev, buffer->isp_addr);
1493 pipe->state |= ISP_PIPELINE_IDLE_INPUT;
1494 }
1495
1496 if (prev->output & PREVIEW_OUTPUT_MEMORY) {
1497 buffer = omap3isp_video_buffer_next(&prev->video_out);
1498 if (buffer != NULL) {
1499 preview_set_outaddr(prev, buffer->isp_addr);
1500 restart = 1;
1501 }
1502 pipe->state |= ISP_PIPELINE_IDLE_OUTPUT;
1503 }
1504
1505 switch (prev->state) {
1506 case ISP_PIPELINE_STREAM_SINGLESHOT:
1507 if (isp_pipeline_ready(pipe))
1508 omap3isp_pipeline_set_stream(pipe,
1509 ISP_PIPELINE_STREAM_SINGLESHOT);
1510 break;
1511
1512 case ISP_PIPELINE_STREAM_CONTINUOUS:
1513 /* If an underrun occurs, the video queue operation handler will
1514 * restart the preview engine. Otherwise restart it immediately.
1515 */
1516 if (restart)
1517 preview_enable_oneshot(prev);
1518 break;
1519
1520 case ISP_PIPELINE_STREAM_STOPPED:
1521 default:
1522 return;
1523 }
1524 }
1525
1526 /*
1527 * omap3isp_preview_isr - ISP preview engine interrupt handler
1528 *
1529 * Manage the preview engine video buffers and configure shadowed registers.
1530 */
1531 void omap3isp_preview_isr(struct isp_prev_device *prev)
1532 {
1533 unsigned long flags;
1534 u32 update;
1535 u32 active;
1536
1537 if (omap3isp_module_sync_is_stopping(&prev->wait, &prev->stopping))
1538 return;
1539
1540 spin_lock_irqsave(&prev->params.lock, flags);
1541 preview_params_switch(prev);
1542 update = preview_params_lock(prev, 0, false);
1543 active = prev->params.active;
1544 spin_unlock_irqrestore(&prev->params.lock, flags);
1545
1546 preview_setup_hw(prev, update, active);
1547 preview_config_input_size(prev, active);
1548
1549 if (prev->input == PREVIEW_INPUT_MEMORY ||
1550 prev->output & PREVIEW_OUTPUT_MEMORY)
1551 preview_isr_buffer(prev);
1552 else if (prev->state == ISP_PIPELINE_STREAM_CONTINUOUS)
1553 preview_enable_oneshot(prev);
1554
1555 spin_lock_irqsave(&prev->params.lock, flags);
1556 preview_params_unlock(prev, update, false);
1557 spin_unlock_irqrestore(&prev->params.lock, flags);
1558 }
1559
1560 /* -----------------------------------------------------------------------------
1561 * ISP video operations
1562 */
1563
1564 static int preview_video_queue(struct isp_video *video,
1565 struct isp_buffer *buffer)
1566 {
1567 struct isp_prev_device *prev = &video->isp->isp_prev;
1568
1569 if (video->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1570 preview_set_inaddr(prev, buffer->isp_addr);
1571
1572 if (video->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1573 preview_set_outaddr(prev, buffer->isp_addr);
1574
1575 return 0;
1576 }
1577
1578 static const struct isp_video_operations preview_video_ops = {
1579 .queue = preview_video_queue,
1580 };
1581
1582 /* -----------------------------------------------------------------------------
1583 * V4L2 subdev operations
1584 */
1585
1586 /*
1587 * preview_s_ctrl - Handle set control subdev method
1588 * @ctrl: pointer to v4l2 control structure
1589 */
1590 static int preview_s_ctrl(struct v4l2_ctrl *ctrl)
1591 {
1592 struct isp_prev_device *prev =
1593 container_of(ctrl->handler, struct isp_prev_device, ctrls);
1594
1595 switch (ctrl->id) {
1596 case V4L2_CID_BRIGHTNESS:
1597 preview_update_brightness(prev, ctrl->val);
1598 break;
1599 case V4L2_CID_CONTRAST:
1600 preview_update_contrast(prev, ctrl->val);
1601 break;
1602 }
1603
1604 return 0;
1605 }
1606
1607 static const struct v4l2_ctrl_ops preview_ctrl_ops = {
1608 .s_ctrl = preview_s_ctrl,
1609 };
1610
1611 /*
1612 * preview_ioctl - Handle preview module private ioctl's
1613 * @prev: pointer to preview context structure
1614 * @cmd: configuration command
1615 * @arg: configuration argument
1616 * return -EINVAL or zero on success
1617 */
1618 static long preview_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1619 {
1620 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1621
1622 switch (cmd) {
1623 case VIDIOC_OMAP3ISP_PRV_CFG:
1624 return preview_config(prev, arg);
1625
1626 default:
1627 return -ENOIOCTLCMD;
1628 }
1629 }
1630
1631 /*
1632 * preview_set_stream - Enable/Disable streaming on preview subdev
1633 * @sd : pointer to v4l2 subdev structure
1634 * @enable: 1 == Enable, 0 == Disable
1635 * return -EINVAL or zero on success
1636 */
1637 static int preview_set_stream(struct v4l2_subdev *sd, int enable)
1638 {
1639 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1640 struct isp_video *video_out = &prev->video_out;
1641 struct isp_device *isp = to_isp_device(prev);
1642 struct device *dev = to_device(prev);
1643
1644 if (prev->state == ISP_PIPELINE_STREAM_STOPPED) {
1645 if (enable == ISP_PIPELINE_STREAM_STOPPED)
1646 return 0;
1647
1648 omap3isp_subclk_enable(isp, OMAP3_ISP_SUBCLK_PREVIEW);
1649 preview_configure(prev);
1650 atomic_set(&prev->stopping, 0);
1651 preview_print_status(prev);
1652 }
1653
1654 switch (enable) {
1655 case ISP_PIPELINE_STREAM_CONTINUOUS:
1656 if (prev->output & PREVIEW_OUTPUT_MEMORY)
1657 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE);
1658
1659 if (video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED ||
1660 !(prev->output & PREVIEW_OUTPUT_MEMORY))
1661 preview_enable_oneshot(prev);
1662
1663 isp_video_dmaqueue_flags_clr(video_out);
1664 break;
1665
1666 case ISP_PIPELINE_STREAM_SINGLESHOT:
1667 if (prev->input == PREVIEW_INPUT_MEMORY)
1668 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_READ);
1669 if (prev->output & PREVIEW_OUTPUT_MEMORY)
1670 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE);
1671
1672 preview_enable_oneshot(prev);
1673 break;
1674
1675 case ISP_PIPELINE_STREAM_STOPPED:
1676 if (omap3isp_module_sync_idle(&sd->entity, &prev->wait,
1677 &prev->stopping))
1678 dev_dbg(dev, "%s: stop timeout.\n", sd->name);
1679 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_PREVIEW_READ);
1680 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_PREVIEW_WRITE);
1681 omap3isp_subclk_disable(isp, OMAP3_ISP_SUBCLK_PREVIEW);
1682 isp_video_dmaqueue_flags_clr(video_out);
1683 break;
1684 }
1685
1686 prev->state = enable;
1687 return 0;
1688 }
1689
1690 static struct v4l2_mbus_framefmt *
1691 __preview_get_format(struct isp_prev_device *prev, struct v4l2_subdev_fh *fh,
1692 unsigned int pad, enum v4l2_subdev_format_whence which)
1693 {
1694 if (which == V4L2_SUBDEV_FORMAT_TRY)
1695 return v4l2_subdev_get_try_format(fh, pad);
1696 else
1697 return &prev->formats[pad];
1698 }
1699
1700 static struct v4l2_rect *
1701 __preview_get_crop(struct isp_prev_device *prev, struct v4l2_subdev_fh *fh,
1702 enum v4l2_subdev_format_whence which)
1703 {
1704 if (which == V4L2_SUBDEV_FORMAT_TRY)
1705 return v4l2_subdev_get_try_crop(fh, PREV_PAD_SINK);
1706 else
1707 return &prev->crop;
1708 }
1709
1710 /* previewer format descriptions */
1711 static const unsigned int preview_input_fmts[] = {
1712 V4L2_MBUS_FMT_Y8_1X8,
1713 V4L2_MBUS_FMT_SGRBG8_1X8,
1714 V4L2_MBUS_FMT_SRGGB8_1X8,
1715 V4L2_MBUS_FMT_SBGGR8_1X8,
1716 V4L2_MBUS_FMT_SGBRG8_1X8,
1717 V4L2_MBUS_FMT_Y10_1X10,
1718 V4L2_MBUS_FMT_SGRBG10_1X10,
1719 V4L2_MBUS_FMT_SRGGB10_1X10,
1720 V4L2_MBUS_FMT_SBGGR10_1X10,
1721 V4L2_MBUS_FMT_SGBRG10_1X10,
1722 };
1723
1724 static const unsigned int preview_output_fmts[] = {
1725 V4L2_MBUS_FMT_UYVY8_1X16,
1726 V4L2_MBUS_FMT_YUYV8_1X16,
1727 };
1728
1729 /*
1730 * preview_try_format - Validate a format
1731 * @prev: ISP preview engine
1732 * @fh: V4L2 subdev file handle
1733 * @pad: pad number
1734 * @fmt: format to be validated
1735 * @which: try/active format selector
1736 *
1737 * Validate and adjust the given format for the given pad based on the preview
1738 * engine limits and the format and crop rectangles on other pads.
1739 */
1740 static void preview_try_format(struct isp_prev_device *prev,
1741 struct v4l2_subdev_fh *fh, unsigned int pad,
1742 struct v4l2_mbus_framefmt *fmt,
1743 enum v4l2_subdev_format_whence which)
1744 {
1745 enum v4l2_mbus_pixelcode pixelcode;
1746 struct v4l2_rect *crop;
1747 unsigned int i;
1748
1749 switch (pad) {
1750 case PREV_PAD_SINK:
1751 /* When reading data from the CCDC, the input size has already
1752 * been mangled by the CCDC output pad so it can be accepted
1753 * as-is.
1754 *
1755 * When reading data from memory, clamp the requested width and
1756 * height. The TRM doesn't specify a minimum input height, make
1757 * sure we got enough lines to enable the noise filter and color
1758 * filter array interpolation.
1759 */
1760 if (prev->input == PREVIEW_INPUT_MEMORY) {
1761 fmt->width = clamp_t(u32, fmt->width, PREV_MIN_IN_WIDTH,
1762 preview_max_out_width(prev));
1763 fmt->height = clamp_t(u32, fmt->height,
1764 PREV_MIN_IN_HEIGHT,
1765 PREV_MAX_IN_HEIGHT);
1766 }
1767
1768 fmt->colorspace = V4L2_COLORSPACE_SRGB;
1769
1770 for (i = 0; i < ARRAY_SIZE(preview_input_fmts); i++) {
1771 if (fmt->code == preview_input_fmts[i])
1772 break;
1773 }
1774
1775 /* If not found, use SGRBG10 as default */
1776 if (i >= ARRAY_SIZE(preview_input_fmts))
1777 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
1778 break;
1779
1780 case PREV_PAD_SOURCE:
1781 pixelcode = fmt->code;
1782 *fmt = *__preview_get_format(prev, fh, PREV_PAD_SINK, which);
1783
1784 switch (pixelcode) {
1785 case V4L2_MBUS_FMT_YUYV8_1X16:
1786 case V4L2_MBUS_FMT_UYVY8_1X16:
1787 fmt->code = pixelcode;
1788 break;
1789
1790 default:
1791 fmt->code = V4L2_MBUS_FMT_YUYV8_1X16;
1792 break;
1793 }
1794
1795 /* The preview module output size is configurable through the
1796 * averager (horizontal scaling by 1/1, 1/2, 1/4 or 1/8). This
1797 * is not supported yet, hardcode the output size to the crop
1798 * rectangle size.
1799 */
1800 crop = __preview_get_crop(prev, fh, which);
1801 fmt->width = crop->width;
1802 fmt->height = crop->height;
1803
1804 fmt->colorspace = V4L2_COLORSPACE_JPEG;
1805 break;
1806 }
1807
1808 fmt->field = V4L2_FIELD_NONE;
1809 }
1810
1811 /*
1812 * preview_try_crop - Validate a crop rectangle
1813 * @prev: ISP preview engine
1814 * @sink: format on the sink pad
1815 * @crop: crop rectangle to be validated
1816 *
1817 * The preview engine crops lines and columns for its internal operation,
1818 * depending on which filters are enabled. Enforce minimum crop margins to
1819 * handle that transparently for userspace.
1820 *
1821 * See the explanation at the PREV_MARGIN_* definitions for more details.
1822 */
1823 static void preview_try_crop(struct isp_prev_device *prev,
1824 const struct v4l2_mbus_framefmt *sink,
1825 struct v4l2_rect *crop)
1826 {
1827 unsigned int left = PREV_MARGIN_LEFT;
1828 unsigned int right = sink->width - PREV_MARGIN_RIGHT;
1829 unsigned int top = PREV_MARGIN_TOP;
1830 unsigned int bottom = sink->height - PREV_MARGIN_BOTTOM;
1831
1832 /* When processing data on-the-fly from the CCDC, at least 2 pixels must
1833 * be cropped from the left and right sides of the image. As we don't
1834 * know which filters will be enabled, increase the left and right
1835 * margins by two.
1836 */
1837 if (prev->input == PREVIEW_INPUT_CCDC) {
1838 left += 2;
1839 right -= 2;
1840 }
1841
1842 /* The CFA filter crops 4 lines and 4 columns in Bayer mode, and 2 lines
1843 * and no columns in other modes. Increase the margins based on the sink
1844 * format.
1845 */
1846 if (sink->code != V4L2_MBUS_FMT_Y8_1X8 &&
1847 sink->code != V4L2_MBUS_FMT_Y10_1X10) {
1848 left += 2;
1849 right -= 2;
1850 top += 2;
1851 bottom -= 2;
1852 }
1853
1854 /* Restrict left/top to even values to keep the Bayer pattern. */
1855 crop->left &= ~1;
1856 crop->top &= ~1;
1857
1858 crop->left = clamp_t(u32, crop->left, left, right - PREV_MIN_OUT_WIDTH);
1859 crop->top = clamp_t(u32, crop->top, top, bottom - PREV_MIN_OUT_HEIGHT);
1860 crop->width = clamp_t(u32, crop->width, PREV_MIN_OUT_WIDTH,
1861 right - crop->left);
1862 crop->height = clamp_t(u32, crop->height, PREV_MIN_OUT_HEIGHT,
1863 bottom - crop->top);
1864 }
1865
1866 /*
1867 * preview_enum_mbus_code - Handle pixel format enumeration
1868 * @sd : pointer to v4l2 subdev structure
1869 * @fh : V4L2 subdev file handle
1870 * @code : pointer to v4l2_subdev_mbus_code_enum structure
1871 * return -EINVAL or zero on success
1872 */
1873 static int preview_enum_mbus_code(struct v4l2_subdev *sd,
1874 struct v4l2_subdev_fh *fh,
1875 struct v4l2_subdev_mbus_code_enum *code)
1876 {
1877 switch (code->pad) {
1878 case PREV_PAD_SINK:
1879 if (code->index >= ARRAY_SIZE(preview_input_fmts))
1880 return -EINVAL;
1881
1882 code->code = preview_input_fmts[code->index];
1883 break;
1884 case PREV_PAD_SOURCE:
1885 if (code->index >= ARRAY_SIZE(preview_output_fmts))
1886 return -EINVAL;
1887
1888 code->code = preview_output_fmts[code->index];
1889 break;
1890 default:
1891 return -EINVAL;
1892 }
1893
1894 return 0;
1895 }
1896
1897 static int preview_enum_frame_size(struct v4l2_subdev *sd,
1898 struct v4l2_subdev_fh *fh,
1899 struct v4l2_subdev_frame_size_enum *fse)
1900 {
1901 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1902 struct v4l2_mbus_framefmt format;
1903
1904 if (fse->index != 0)
1905 return -EINVAL;
1906
1907 format.code = fse->code;
1908 format.width = 1;
1909 format.height = 1;
1910 preview_try_format(prev, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
1911 fse->min_width = format.width;
1912 fse->min_height = format.height;
1913
1914 if (format.code != fse->code)
1915 return -EINVAL;
1916
1917 format.code = fse->code;
1918 format.width = -1;
1919 format.height = -1;
1920 preview_try_format(prev, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
1921 fse->max_width = format.width;
1922 fse->max_height = format.height;
1923
1924 return 0;
1925 }
1926
1927 /*
1928 * preview_get_selection - Retrieve a selection rectangle on a pad
1929 * @sd: ISP preview V4L2 subdevice
1930 * @fh: V4L2 subdev file handle
1931 * @sel: Selection rectangle
1932 *
1933 * The only supported rectangles are the crop rectangles on the sink pad.
1934 *
1935 * Return 0 on success or a negative error code otherwise.
1936 */
1937 static int preview_get_selection(struct v4l2_subdev *sd,
1938 struct v4l2_subdev_fh *fh,
1939 struct v4l2_subdev_selection *sel)
1940 {
1941 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1942 struct v4l2_mbus_framefmt *format;
1943
1944 if (sel->pad != PREV_PAD_SINK)
1945 return -EINVAL;
1946
1947 switch (sel->target) {
1948 case V4L2_SEL_TGT_CROP_BOUNDS:
1949 sel->r.left = 0;
1950 sel->r.top = 0;
1951 sel->r.width = INT_MAX;
1952 sel->r.height = INT_MAX;
1953
1954 format = __preview_get_format(prev, fh, PREV_PAD_SINK,
1955 sel->which);
1956 preview_try_crop(prev, format, &sel->r);
1957 break;
1958
1959 case V4L2_SEL_TGT_CROP:
1960 sel->r = *__preview_get_crop(prev, fh, sel->which);
1961 break;
1962
1963 default:
1964 return -EINVAL;
1965 }
1966
1967 return 0;
1968 }
1969
1970 /*
1971 * preview_set_selection - Set a selection rectangle on a pad
1972 * @sd: ISP preview V4L2 subdevice
1973 * @fh: V4L2 subdev file handle
1974 * @sel: Selection rectangle
1975 *
1976 * The only supported rectangle is the actual crop rectangle on the sink pad.
1977 *
1978 * Return 0 on success or a negative error code otherwise.
1979 */
1980 static int preview_set_selection(struct v4l2_subdev *sd,
1981 struct v4l2_subdev_fh *fh,
1982 struct v4l2_subdev_selection *sel)
1983 {
1984 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
1985 struct v4l2_mbus_framefmt *format;
1986
1987 if (sel->target != V4L2_SEL_TGT_CROP ||
1988 sel->pad != PREV_PAD_SINK)
1989 return -EINVAL;
1990
1991 /* The crop rectangle can't be changed while streaming. */
1992 if (prev->state != ISP_PIPELINE_STREAM_STOPPED)
1993 return -EBUSY;
1994
1995 /* Modifying the crop rectangle always changes the format on the source
1996 * pad. If the KEEP_CONFIG flag is set, just return the current crop
1997 * rectangle.
1998 */
1999 if (sel->flags & V4L2_SEL_FLAG_KEEP_CONFIG) {
2000 sel->r = *__preview_get_crop(prev, fh, sel->which);
2001 return 0;
2002 }
2003
2004 format = __preview_get_format(prev, fh, PREV_PAD_SINK, sel->which);
2005 preview_try_crop(prev, format, &sel->r);
2006 *__preview_get_crop(prev, fh, sel->which) = sel->r;
2007
2008 /* Update the source format. */
2009 format = __preview_get_format(prev, fh, PREV_PAD_SOURCE, sel->which);
2010 preview_try_format(prev, fh, PREV_PAD_SOURCE, format, sel->which);
2011
2012 return 0;
2013 }
2014
2015 /*
2016 * preview_get_format - Handle get format by pads subdev method
2017 * @sd : pointer to v4l2 subdev structure
2018 * @fh : V4L2 subdev file handle
2019 * @fmt: pointer to v4l2 subdev format structure
2020 * return -EINVAL or zero on success
2021 */
2022 static int preview_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2023 struct v4l2_subdev_format *fmt)
2024 {
2025 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
2026 struct v4l2_mbus_framefmt *format;
2027
2028 format = __preview_get_format(prev, fh, fmt->pad, fmt->which);
2029 if (format == NULL)
2030 return -EINVAL;
2031
2032 fmt->format = *format;
2033 return 0;
2034 }
2035
2036 /*
2037 * preview_set_format - Handle set format by pads subdev method
2038 * @sd : pointer to v4l2 subdev structure
2039 * @fh : V4L2 subdev file handle
2040 * @fmt: pointer to v4l2 subdev format structure
2041 * return -EINVAL or zero on success
2042 */
2043 static int preview_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
2044 struct v4l2_subdev_format *fmt)
2045 {
2046 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
2047 struct v4l2_mbus_framefmt *format;
2048 struct v4l2_rect *crop;
2049
2050 format = __preview_get_format(prev, fh, fmt->pad, fmt->which);
2051 if (format == NULL)
2052 return -EINVAL;
2053
2054 preview_try_format(prev, fh, fmt->pad, &fmt->format, fmt->which);
2055 *format = fmt->format;
2056
2057 /* Propagate the format from sink to source */
2058 if (fmt->pad == PREV_PAD_SINK) {
2059 /* Reset the crop rectangle. */
2060 crop = __preview_get_crop(prev, fh, fmt->which);
2061 crop->left = 0;
2062 crop->top = 0;
2063 crop->width = fmt->format.width;
2064 crop->height = fmt->format.height;
2065
2066 preview_try_crop(prev, &fmt->format, crop);
2067
2068 /* Update the source format. */
2069 format = __preview_get_format(prev, fh, PREV_PAD_SOURCE,
2070 fmt->which);
2071 preview_try_format(prev, fh, PREV_PAD_SOURCE, format,
2072 fmt->which);
2073 }
2074
2075 return 0;
2076 }
2077
2078 /*
2079 * preview_init_formats - Initialize formats on all pads
2080 * @sd: ISP preview V4L2 subdevice
2081 * @fh: V4L2 subdev file handle
2082 *
2083 * Initialize all pad formats with default values. If fh is not NULL, try
2084 * formats are initialized on the file handle. Otherwise active formats are
2085 * initialized on the device.
2086 */
2087 static int preview_init_formats(struct v4l2_subdev *sd,
2088 struct v4l2_subdev_fh *fh)
2089 {
2090 struct v4l2_subdev_format format;
2091
2092 memset(&format, 0, sizeof(format));
2093 format.pad = PREV_PAD_SINK;
2094 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
2095 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
2096 format.format.width = 4096;
2097 format.format.height = 4096;
2098 preview_set_format(sd, fh, &format);
2099
2100 return 0;
2101 }
2102
2103 /* subdev core operations */
2104 static const struct v4l2_subdev_core_ops preview_v4l2_core_ops = {
2105 .ioctl = preview_ioctl,
2106 };
2107
2108 /* subdev video operations */
2109 static const struct v4l2_subdev_video_ops preview_v4l2_video_ops = {
2110 .s_stream = preview_set_stream,
2111 };
2112
2113 /* subdev pad operations */
2114 static const struct v4l2_subdev_pad_ops preview_v4l2_pad_ops = {
2115 .enum_mbus_code = preview_enum_mbus_code,
2116 .enum_frame_size = preview_enum_frame_size,
2117 .get_fmt = preview_get_format,
2118 .set_fmt = preview_set_format,
2119 .get_selection = preview_get_selection,
2120 .set_selection = preview_set_selection,
2121 };
2122
2123 /* subdev operations */
2124 static const struct v4l2_subdev_ops preview_v4l2_ops = {
2125 .core = &preview_v4l2_core_ops,
2126 .video = &preview_v4l2_video_ops,
2127 .pad = &preview_v4l2_pad_ops,
2128 };
2129
2130 /* subdev internal operations */
2131 static const struct v4l2_subdev_internal_ops preview_v4l2_internal_ops = {
2132 .open = preview_init_formats,
2133 };
2134
2135 /* -----------------------------------------------------------------------------
2136 * Media entity operations
2137 */
2138
2139 /*
2140 * preview_link_setup - Setup previewer connections.
2141 * @entity : Pointer to media entity structure
2142 * @local : Pointer to local pad array
2143 * @remote : Pointer to remote pad array
2144 * @flags : Link flags
2145 * return -EINVAL or zero on success
2146 */
2147 static int preview_link_setup(struct media_entity *entity,
2148 const struct media_pad *local,
2149 const struct media_pad *remote, u32 flags)
2150 {
2151 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
2152 struct isp_prev_device *prev = v4l2_get_subdevdata(sd);
2153
2154 switch (local->index | media_entity_type(remote->entity)) {
2155 case PREV_PAD_SINK | MEDIA_ENT_T_DEVNODE:
2156 /* read from memory */
2157 if (flags & MEDIA_LNK_FL_ENABLED) {
2158 if (prev->input == PREVIEW_INPUT_CCDC)
2159 return -EBUSY;
2160 prev->input = PREVIEW_INPUT_MEMORY;
2161 } else {
2162 if (prev->input == PREVIEW_INPUT_MEMORY)
2163 prev->input = PREVIEW_INPUT_NONE;
2164 }
2165 break;
2166
2167 case PREV_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
2168 /* read from ccdc */
2169 if (flags & MEDIA_LNK_FL_ENABLED) {
2170 if (prev->input == PREVIEW_INPUT_MEMORY)
2171 return -EBUSY;
2172 prev->input = PREVIEW_INPUT_CCDC;
2173 } else {
2174 if (prev->input == PREVIEW_INPUT_CCDC)
2175 prev->input = PREVIEW_INPUT_NONE;
2176 }
2177 break;
2178
2179 /*
2180 * The ISP core doesn't support pipelines with multiple video outputs.
2181 * Revisit this when it will be implemented, and return -EBUSY for now.
2182 */
2183
2184 case PREV_PAD_SOURCE | MEDIA_ENT_T_DEVNODE:
2185 /* write to memory */
2186 if (flags & MEDIA_LNK_FL_ENABLED) {
2187 if (prev->output & ~PREVIEW_OUTPUT_MEMORY)
2188 return -EBUSY;
2189 prev->output |= PREVIEW_OUTPUT_MEMORY;
2190 } else {
2191 prev->output &= ~PREVIEW_OUTPUT_MEMORY;
2192 }
2193 break;
2194
2195 case PREV_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
2196 /* write to resizer */
2197 if (flags & MEDIA_LNK_FL_ENABLED) {
2198 if (prev->output & ~PREVIEW_OUTPUT_RESIZER)
2199 return -EBUSY;
2200 prev->output |= PREVIEW_OUTPUT_RESIZER;
2201 } else {
2202 prev->output &= ~PREVIEW_OUTPUT_RESIZER;
2203 }
2204 break;
2205
2206 default:
2207 return -EINVAL;
2208 }
2209
2210 return 0;
2211 }
2212
2213 /* media operations */
2214 static const struct media_entity_operations preview_media_ops = {
2215 .link_setup = preview_link_setup,
2216 .link_validate = v4l2_subdev_link_validate,
2217 };
2218
2219 void omap3isp_preview_unregister_entities(struct isp_prev_device *prev)
2220 {
2221 v4l2_device_unregister_subdev(&prev->subdev);
2222 omap3isp_video_unregister(&prev->video_in);
2223 omap3isp_video_unregister(&prev->video_out);
2224 }
2225
2226 int omap3isp_preview_register_entities(struct isp_prev_device *prev,
2227 struct v4l2_device *vdev)
2228 {
2229 int ret;
2230
2231 /* Register the subdev and video nodes. */
2232 ret = v4l2_device_register_subdev(vdev, &prev->subdev);
2233 if (ret < 0)
2234 goto error;
2235
2236 ret = omap3isp_video_register(&prev->video_in, vdev);
2237 if (ret < 0)
2238 goto error;
2239
2240 ret = omap3isp_video_register(&prev->video_out, vdev);
2241 if (ret < 0)
2242 goto error;
2243
2244 return 0;
2245
2246 error:
2247 omap3isp_preview_unregister_entities(prev);
2248 return ret;
2249 }
2250
2251 /* -----------------------------------------------------------------------------
2252 * ISP previewer initialisation and cleanup
2253 */
2254
2255 /*
2256 * preview_init_entities - Initialize subdev and media entity.
2257 * @prev : Pointer to preview structure
2258 * return -ENOMEM or zero on success
2259 */
2260 static int preview_init_entities(struct isp_prev_device *prev)
2261 {
2262 struct v4l2_subdev *sd = &prev->subdev;
2263 struct media_pad *pads = prev->pads;
2264 struct media_entity *me = &sd->entity;
2265 int ret;
2266
2267 prev->input = PREVIEW_INPUT_NONE;
2268
2269 v4l2_subdev_init(sd, &preview_v4l2_ops);
2270 sd->internal_ops = &preview_v4l2_internal_ops;
2271 strlcpy(sd->name, "OMAP3 ISP preview", sizeof(sd->name));
2272 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
2273 v4l2_set_subdevdata(sd, prev);
2274 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2275
2276 v4l2_ctrl_handler_init(&prev->ctrls, 2);
2277 v4l2_ctrl_new_std(&prev->ctrls, &preview_ctrl_ops, V4L2_CID_BRIGHTNESS,
2278 ISPPRV_BRIGHT_LOW, ISPPRV_BRIGHT_HIGH,
2279 ISPPRV_BRIGHT_STEP, ISPPRV_BRIGHT_DEF);
2280 v4l2_ctrl_new_std(&prev->ctrls, &preview_ctrl_ops, V4L2_CID_CONTRAST,
2281 ISPPRV_CONTRAST_LOW, ISPPRV_CONTRAST_HIGH,
2282 ISPPRV_CONTRAST_STEP, ISPPRV_CONTRAST_DEF);
2283 v4l2_ctrl_handler_setup(&prev->ctrls);
2284 sd->ctrl_handler = &prev->ctrls;
2285
2286 pads[PREV_PAD_SINK].flags = MEDIA_PAD_FL_SINK
2287 | MEDIA_PAD_FL_MUST_CONNECT;
2288 pads[PREV_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
2289
2290 me->ops = &preview_media_ops;
2291 ret = media_entity_init(me, PREV_PADS_NUM, pads, 0);
2292 if (ret < 0)
2293 return ret;
2294
2295 preview_init_formats(sd, NULL);
2296
2297 /* According to the OMAP34xx TRM, video buffers need to be aligned on a
2298 * 32 bytes boundary. However, an undocumented hardware bug requires a
2299 * 64 bytes boundary at the preview engine input.
2300 */
2301 prev->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2302 prev->video_in.ops = &preview_video_ops;
2303 prev->video_in.isp = to_isp_device(prev);
2304 prev->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 2 * 3;
2305 prev->video_in.bpl_alignment = 64;
2306 prev->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2307 prev->video_out.ops = &preview_video_ops;
2308 prev->video_out.isp = to_isp_device(prev);
2309 prev->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 2 * 3;
2310 prev->video_out.bpl_alignment = 32;
2311
2312 ret = omap3isp_video_init(&prev->video_in, "preview");
2313 if (ret < 0)
2314 goto error_video_in;
2315
2316 ret = omap3isp_video_init(&prev->video_out, "preview");
2317 if (ret < 0)
2318 goto error_video_out;
2319
2320 /* Connect the video nodes to the previewer subdev. */
2321 ret = media_entity_create_link(&prev->video_in.video.entity, 0,
2322 &prev->subdev.entity, PREV_PAD_SINK, 0);
2323 if (ret < 0)
2324 goto error_link;
2325
2326 ret = media_entity_create_link(&prev->subdev.entity, PREV_PAD_SOURCE,
2327 &prev->video_out.video.entity, 0, 0);
2328 if (ret < 0)
2329 goto error_link;
2330
2331 return 0;
2332
2333 error_link:
2334 omap3isp_video_cleanup(&prev->video_out);
2335 error_video_out:
2336 omap3isp_video_cleanup(&prev->video_in);
2337 error_video_in:
2338 media_entity_cleanup(&prev->subdev.entity);
2339 return ret;
2340 }
2341
2342 /*
2343 * omap3isp_preview_init - Previewer initialization.
2344 * @dev : Pointer to ISP device
2345 * return -ENOMEM or zero on success
2346 */
2347 int omap3isp_preview_init(struct isp_device *isp)
2348 {
2349 struct isp_prev_device *prev = &isp->isp_prev;
2350
2351 init_waitqueue_head(&prev->wait);
2352
2353 preview_init_params(prev);
2354
2355 return preview_init_entities(prev);
2356 }
2357
2358 void omap3isp_preview_cleanup(struct isp_device *isp)
2359 {
2360 struct isp_prev_device *prev = &isp->isp_prev;
2361
2362 v4l2_ctrl_handler_free(&prev->ctrls);
2363 omap3isp_video_cleanup(&prev->video_in);
2364 omap3isp_video_cleanup(&prev->video_out);
2365 media_entity_cleanup(&prev->subdev.entity);
2366 }
Linux with added FPC-III support