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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
blobe2aac592d29f6a3be2ec81ade46a89cb7e9727ee
1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <media/videobuf2-core.h>
26 #include "s5p_mfc_common.h"
27 #include "s5p_mfc_ctrl.h"
28 #include "s5p_mfc_debug.h"
29 #include "s5p_mfc_dec.h"
30 #include "s5p_mfc_enc.h"
31 #include "s5p_mfc_intr.h"
32 #include "s5p_mfc_opr.h"
33 #include "s5p_mfc_cmd.h"
34 #include "s5p_mfc_pm.h"
35
36 #define S5P_MFC_NAME "s5p-mfc"
37 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
40 int debug;
41 module_param(debug, int, S_IRUGO | S_IWUSR);
42 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44 /* Helper functions for interrupt processing */
45
46 /* Remove from hw execution round robin */
47 void clear_work_bit(struct s5p_mfc_ctx *ctx)
48 {
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
52 __clear_bit(ctx->num, &dev->ctx_work_bits);
53 spin_unlock(&dev->condlock);
54 }
55
56 /* Add to hw execution round robin */
57 void set_work_bit(struct s5p_mfc_ctx *ctx)
58 {
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64 }
65
66 /* Remove from hw execution round robin */
67 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68 {
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75 }
76
77 /* Add to hw execution round robin */
78 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79 {
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86 }
87
88 /* Wake up context wait_queue */
89 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
90 unsigned int err)
91 {
92 ctx->int_cond = 1;
93 ctx->int_type = reason;
94 ctx->int_err = err;
95 wake_up(&ctx->queue);
96 }
97
98 /* Wake up device wait_queue */
99 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
100 unsigned int err)
101 {
102 dev->int_cond = 1;
103 dev->int_type = reason;
104 dev->int_err = err;
105 wake_up(&dev->queue);
106 }
107
108 static void s5p_mfc_watchdog(unsigned long arg)
109 {
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
111
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115 /* This means that hw is busy and no interrupts were
116 * generated by hw for the Nth time of running this
117 * watchdog timer. This usually means a serious hw
118 * error. Now it is time to kill all instances and
119 * reset the MFC. */
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
122 }
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
126 }
127
128 static void s5p_mfc_watchdog_worker(struct work_struct *work)
129 {
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
132 unsigned long flags;
133 int mutex_locked;
134 int i, ret;
135
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
137
138 mfc_err("Driver timeout error handling\n");
139 /* Lock the mutex that protects open and release.
140 * This is necessary as they may load and unload firmware. */
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
142 if (!mutex_locked)
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
145
146 s5p_mfc_clock_off();
147
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
149 ctx = dev->ctx[i];
150 if (!ctx)
151 continue;
152 ctx->state = MFCINST_ERROR;
153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
154 &ctx->vq_dst);
155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
156 &ctx->vq_src);
157 clear_work_bit(ctx);
158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
159 }
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
162 /* Double check if there is at least one instance running.
163 * If no instance is in memory than no firmware should be present */
164 if (dev->num_inst > 0) {
165 ret = s5p_mfc_reload_firmware(dev);
166 if (ret) {
167 mfc_err("Failed to reload FW\n");
168 goto unlock;
169 }
170 s5p_mfc_clock_on();
171 ret = s5p_mfc_init_hw(dev);
172 if (ret)
173 mfc_err("Failed to reinit FW\n");
174 }
175 unlock:
176 if (mutex_locked)
177 mutex_unlock(&dev->mfc_mutex);
178 }
179
180 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
181 {
182 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
183 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
184 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
185 }
186
187 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
188 {
189 struct s5p_mfc_buf *dst_buf;
190 struct s5p_mfc_dev *dev = ctx->dev;
191
192 ctx->state = MFCINST_FINISHED;
193 ctx->sequence++;
194 while (!list_empty(&ctx->dst_queue)) {
195 dst_buf = list_entry(ctx->dst_queue.next,
196 struct s5p_mfc_buf, list);
197 mfc_debug(2, "Cleaning up buffer: %d\n",
198 dst_buf->b->v4l2_buf.index);
199 vb2_set_plane_payload(dst_buf->b, 0, 0);
200 vb2_set_plane_payload(dst_buf->b, 1, 0);
201 list_del(&dst_buf->list);
202 ctx->dst_queue_cnt--;
203 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
204
205 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
206 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
207 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
208 else
209 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
210
211 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
212 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
213 }
214 }
215
216 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
217 {
218 struct s5p_mfc_dev *dev = ctx->dev;
219 struct s5p_mfc_buf *dst_buf, *src_buf;
220 size_t dec_y_addr;
221 unsigned int frame_type;
222
223 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
224 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
225
226 /* Copy timestamp / timecode from decoded src to dst and set
227 appropriate flags */
228 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
229 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
230 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
231 dst_buf->b->v4l2_buf.timecode =
232 src_buf->b->v4l2_buf.timecode;
233 dst_buf->b->v4l2_buf.timestamp =
234 src_buf->b->v4l2_buf.timestamp;
235 switch (frame_type) {
236 case S5P_FIMV_DECODE_FRAME_I_FRAME:
237 dst_buf->b->v4l2_buf.flags |=
238 V4L2_BUF_FLAG_KEYFRAME;
239 break;
240 case S5P_FIMV_DECODE_FRAME_P_FRAME:
241 dst_buf->b->v4l2_buf.flags |=
242 V4L2_BUF_FLAG_PFRAME;
243 break;
244 case S5P_FIMV_DECODE_FRAME_B_FRAME:
245 dst_buf->b->v4l2_buf.flags |=
246 V4L2_BUF_FLAG_BFRAME;
247 break;
248 }
249 break;
250 }
251 }
252 }
253
254 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
255 {
256 struct s5p_mfc_dev *dev = ctx->dev;
257 struct s5p_mfc_buf *dst_buf;
258 size_t dspl_y_addr;
259 unsigned int frame_type;
260
261 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
262 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx);
263
264 /* If frame is same as previous then skip and do not dequeue */
265 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
266 if (!ctx->after_packed_pb)
267 ctx->sequence++;
268 ctx->after_packed_pb = 0;
269 return;
270 }
271 ctx->sequence++;
272 /* The MFC returns address of the buffer, now we have to
273 * check which videobuf does it correspond to */
274 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
275 /* Check if this is the buffer we're looking for */
276 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
277 list_del(&dst_buf->list);
278 ctx->dst_queue_cnt--;
279 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
280 if (s5p_mfc_hw_call(dev->mfc_ops,
281 get_pic_type_top, ctx) ==
282 s5p_mfc_hw_call(dev->mfc_ops,
283 get_pic_type_bot, ctx))
284 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
285 else
286 dst_buf->b->v4l2_buf.field =
287 V4L2_FIELD_INTERLACED;
288 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
289 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
290 clear_bit(dst_buf->b->v4l2_buf.index,
291 &ctx->dec_dst_flag);
292
293 vb2_buffer_done(dst_buf->b,
294 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
295
296 break;
297 }
298 }
299 }
300
301 /* Handle frame decoding interrupt */
302 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
303 unsigned int reason, unsigned int err)
304 {
305 struct s5p_mfc_dev *dev = ctx->dev;
306 unsigned int dst_frame_status;
307 struct s5p_mfc_buf *src_buf;
308 unsigned long flags;
309 unsigned int res_change;
310
311 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
312 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
313 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
314 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
315 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
316 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
317 if (ctx->state == MFCINST_RES_CHANGE_INIT)
318 ctx->state = MFCINST_RES_CHANGE_FLUSH;
319 if (res_change == S5P_FIMV_RES_INCREASE ||
320 res_change == S5P_FIMV_RES_DECREASE) {
321 ctx->state = MFCINST_RES_CHANGE_INIT;
322 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
323 wake_up_ctx(ctx, reason, err);
324 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
325 BUG();
326 s5p_mfc_clock_off();
327 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
328 return;
329 }
330 if (ctx->dpb_flush_flag)
331 ctx->dpb_flush_flag = 0;
332
333 spin_lock_irqsave(&dev->irqlock, flags);
334 /* All frames remaining in the buffer have been extracted */
335 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
336 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
337 s5p_mfc_handle_frame_all_extracted(ctx);
338 ctx->state = MFCINST_RES_CHANGE_END;
339 goto leave_handle_frame;
340 } else {
341 s5p_mfc_handle_frame_all_extracted(ctx);
342 }
343 }
344
345 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
346 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
347 s5p_mfc_handle_frame_copy_time(ctx);
348
349 /* A frame has been decoded and is in the buffer */
350 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
351 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
352 s5p_mfc_handle_frame_new(ctx, err);
353 } else {
354 mfc_debug(2, "No frame decode\n");
355 }
356 /* Mark source buffer as complete */
357 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
358 && !list_empty(&ctx->src_queue)) {
359 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
360 list);
361 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
362 get_consumed_stream, dev);
363 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
364 ctx->consumed_stream + STUFF_BYTE <
365 src_buf->b->v4l2_planes[0].bytesused) {
366 /* Run MFC again on the same buffer */
367 mfc_debug(2, "Running again the same buffer\n");
368 ctx->after_packed_pb = 1;
369 } else {
370 mfc_debug(2, "MFC needs next buffer\n");
371 ctx->consumed_stream = 0;
372 if (src_buf->flags & MFC_BUF_FLAG_EOS)
373 ctx->state = MFCINST_FINISHING;
374 list_del(&src_buf->list);
375 ctx->src_queue_cnt--;
376 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
377 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
378 else
379 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
380 }
381 }
382 leave_handle_frame:
383 spin_unlock_irqrestore(&dev->irqlock, flags);
384 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
385 || ctx->dst_queue_cnt < ctx->pb_count)
386 clear_work_bit(ctx);
387 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
388 wake_up_ctx(ctx, reason, err);
389 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
390 BUG();
391 s5p_mfc_clock_off();
392 /* if suspending, wake up device and do not try_run again*/
393 if (test_bit(0, &dev->enter_suspend))
394 wake_up_dev(dev, reason, err);
395 else
396 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
397 }
398
399 /* Error handling for interrupt */
400 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
401 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
402 {
403 unsigned long flags;
404
405 mfc_err("Interrupt Error: %08x\n", err);
406
407 if (ctx != NULL) {
408 /* Error recovery is dependent on the state of context */
409 switch (ctx->state) {
410 case MFCINST_RES_CHANGE_INIT:
411 case MFCINST_RES_CHANGE_FLUSH:
412 case MFCINST_RES_CHANGE_END:
413 case MFCINST_FINISHING:
414 case MFCINST_FINISHED:
415 case MFCINST_RUNNING:
416 /* It is highly probable that an error occurred
417 * while decoding a frame */
418 clear_work_bit(ctx);
419 ctx->state = MFCINST_ERROR;
420 /* Mark all dst buffers as having an error */
421 spin_lock_irqsave(&dev->irqlock, flags);
422 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
423 &ctx->dst_queue, &ctx->vq_dst);
424 /* Mark all src buffers as having an error */
425 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue,
426 &ctx->src_queue, &ctx->vq_src);
427 spin_unlock_irqrestore(&dev->irqlock, flags);
428 wake_up_ctx(ctx, reason, err);
429 break;
430 default:
431 clear_work_bit(ctx);
432 ctx->state = MFCINST_ERROR;
433 wake_up_ctx(ctx, reason, err);
434 break;
435 }
436 }
437 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
438 BUG();
439 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
440 s5p_mfc_clock_off();
441 wake_up_dev(dev, reason, err);
442 return;
443 }
444
445 /* Header parsing interrupt handling */
446 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
447 unsigned int reason, unsigned int err)
448 {
449 struct s5p_mfc_dev *dev;
450
451 if (ctx == NULL)
452 return;
453 dev = ctx->dev;
454 if (ctx->c_ops->post_seq_start) {
455 if (ctx->c_ops->post_seq_start(ctx))
456 mfc_err("post_seq_start() failed\n");
457 } else {
458 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
459 dev);
460 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
461 dev);
462
463 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
464
465 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
466 dev);
467 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
468 dev);
469 if (ctx->img_width == 0 || ctx->img_height == 0)
470 ctx->state = MFCINST_ERROR;
471 else
472 ctx->state = MFCINST_HEAD_PARSED;
473
474 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
475 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
476 !list_empty(&ctx->src_queue)) {
477 struct s5p_mfc_buf *src_buf;
478 src_buf = list_entry(ctx->src_queue.next,
479 struct s5p_mfc_buf, list);
480 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
481 dev) <
482 src_buf->b->v4l2_planes[0].bytesused)
483 ctx->head_processed = 0;
484 else
485 ctx->head_processed = 1;
486 } else {
487 ctx->head_processed = 1;
488 }
489 }
490 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
491 clear_work_bit(ctx);
492 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
493 BUG();
494 s5p_mfc_clock_off();
495 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
496 wake_up_ctx(ctx, reason, err);
497 }
498
499 /* Header parsing interrupt handling */
500 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
501 unsigned int reason, unsigned int err)
502 {
503 struct s5p_mfc_buf *src_buf;
504 struct s5p_mfc_dev *dev;
505 unsigned long flags;
506
507 if (ctx == NULL)
508 return;
509 dev = ctx->dev;
510 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
511 ctx->int_type = reason;
512 ctx->int_err = err;
513 ctx->int_cond = 1;
514 clear_work_bit(ctx);
515 if (err == 0) {
516 ctx->state = MFCINST_RUNNING;
517 if (!ctx->dpb_flush_flag && ctx->head_processed) {
518 spin_lock_irqsave(&dev->irqlock, flags);
519 if (!list_empty(&ctx->src_queue)) {
520 src_buf = list_entry(ctx->src_queue.next,
521 struct s5p_mfc_buf, list);
522 list_del(&src_buf->list);
523 ctx->src_queue_cnt--;
524 vb2_buffer_done(src_buf->b,
525 VB2_BUF_STATE_DONE);
526 }
527 spin_unlock_irqrestore(&dev->irqlock, flags);
528 } else {
529 ctx->dpb_flush_flag = 0;
530 }
531 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
532 BUG();
533
534 s5p_mfc_clock_off();
535
536 wake_up(&ctx->queue);
537 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
538 } else {
539 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
540 BUG();
541
542 s5p_mfc_clock_off();
543
544 wake_up(&ctx->queue);
545 }
546 }
547
548 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
549 unsigned int reason, unsigned int err)
550 {
551 struct s5p_mfc_dev *dev = ctx->dev;
552 struct s5p_mfc_buf *mb_entry;
553
554 mfc_debug(2, "Stream completed\n");
555
556 s5p_mfc_clear_int_flags(dev);
557 ctx->int_type = reason;
558 ctx->int_err = err;
559 ctx->state = MFCINST_FINISHED;
560
561 spin_lock(&dev->irqlock);
562 if (!list_empty(&ctx->dst_queue)) {
563 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
564 list);
565 list_del(&mb_entry->list);
566 ctx->dst_queue_cnt--;
567 vb2_set_plane_payload(mb_entry->b, 0, 0);
568 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
569 }
570 spin_unlock(&dev->irqlock);
571
572 clear_work_bit(ctx);
573
574 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
575
576 s5p_mfc_clock_off();
577 wake_up(&ctx->queue);
578 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
579 }
580
581 /* Interrupt processing */
582 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
583 {
584 struct s5p_mfc_dev *dev = priv;
585 struct s5p_mfc_ctx *ctx;
586 unsigned int reason;
587 unsigned int err;
588
589 mfc_debug_enter();
590 /* Reset the timeout watchdog */
591 atomic_set(&dev->watchdog_cnt, 0);
592 ctx = dev->ctx[dev->curr_ctx];
593 /* Get the reason of interrupt and the error code */
594 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
595 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
596 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
597 switch (reason) {
598 case S5P_MFC_R2H_CMD_ERR_RET:
599 /* An error has occurred */
600 if (ctx->state == MFCINST_RUNNING &&
601 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
602 dev->warn_start)
603 s5p_mfc_handle_frame(ctx, reason, err);
604 else
605 s5p_mfc_handle_error(dev, ctx, reason, err);
606 clear_bit(0, &dev->enter_suspend);
607 break;
608
609 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
610 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
611 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
612 if (ctx->c_ops->post_frame_start) {
613 if (ctx->c_ops->post_frame_start(ctx))
614 mfc_err("post_frame_start() failed\n");
615 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
616 wake_up_ctx(ctx, reason, err);
617 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
618 BUG();
619 s5p_mfc_clock_off();
620 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
621 } else {
622 s5p_mfc_handle_frame(ctx, reason, err);
623 }
624 break;
625
626 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
627 s5p_mfc_handle_seq_done(ctx, reason, err);
628 break;
629
630 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
631 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
632 ctx->state = MFCINST_GOT_INST;
633 clear_work_bit(ctx);
634 wake_up(&ctx->queue);
635 goto irq_cleanup_hw;
636
637 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
638 clear_work_bit(ctx);
639 ctx->state = MFCINST_FREE;
640 wake_up(&ctx->queue);
641 goto irq_cleanup_hw;
642
643 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
644 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
645 case S5P_MFC_R2H_CMD_SLEEP_RET:
646 case S5P_MFC_R2H_CMD_WAKEUP_RET:
647 if (ctx)
648 clear_work_bit(ctx);
649 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
650 wake_up_dev(dev, reason, err);
651 clear_bit(0, &dev->hw_lock);
652 clear_bit(0, &dev->enter_suspend);
653 break;
654
655 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
656 s5p_mfc_handle_init_buffers(ctx, reason, err);
657 break;
658
659 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
660 s5p_mfc_handle_stream_complete(ctx, reason, err);
661 break;
662
663 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
664 clear_work_bit(ctx);
665 ctx->state = MFCINST_RUNNING;
666 wake_up(&ctx->queue);
667 goto irq_cleanup_hw;
668
669 default:
670 mfc_debug(2, "Unknown int reason\n");
671 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
672 }
673 mfc_debug_leave();
674 return IRQ_HANDLED;
675 irq_cleanup_hw:
676 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
677 ctx->int_type = reason;
678 ctx->int_err = err;
679 ctx->int_cond = 1;
680 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
681 mfc_err("Failed to unlock hw\n");
682
683 s5p_mfc_clock_off();
684
685 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
686 mfc_debug(2, "Exit via irq_cleanup_hw\n");
687 return IRQ_HANDLED;
688 }
689
690 /* Open an MFC node */
691 static int s5p_mfc_open(struct file *file)
692 {
693 struct video_device *vdev = video_devdata(file);
694 struct s5p_mfc_dev *dev = video_drvdata(file);
695 struct s5p_mfc_ctx *ctx = NULL;
696 struct vb2_queue *q;
697 int ret = 0;
698
699 mfc_debug_enter();
700 if (mutex_lock_interruptible(&dev->mfc_mutex))
701 return -ERESTARTSYS;
702 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
703 /* Allocate memory for context */
704 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
705 if (!ctx) {
706 mfc_err("Not enough memory\n");
707 ret = -ENOMEM;
708 goto err_alloc;
709 }
710 v4l2_fh_init(&ctx->fh, video_devdata(file));
711 file->private_data = &ctx->fh;
712 v4l2_fh_add(&ctx->fh);
713 ctx->dev = dev;
714 INIT_LIST_HEAD(&ctx->src_queue);
715 INIT_LIST_HEAD(&ctx->dst_queue);
716 ctx->src_queue_cnt = 0;
717 ctx->dst_queue_cnt = 0;
718 /* Get context number */
719 ctx->num = 0;
720 while (dev->ctx[ctx->num]) {
721 ctx->num++;
722 if (ctx->num >= MFC_NUM_CONTEXTS) {
723 mfc_err("Too many open contexts\n");
724 ret = -EBUSY;
725 goto err_no_ctx;
726 }
727 }
728 /* Mark context as idle */
729 clear_work_bit_irqsave(ctx);
730 dev->ctx[ctx->num] = ctx;
731 if (vdev == dev->vfd_dec) {
732 ctx->type = MFCINST_DECODER;
733 ctx->c_ops = get_dec_codec_ops();
734 s5p_mfc_dec_init(ctx);
735 /* Setup ctrl handler */
736 ret = s5p_mfc_dec_ctrls_setup(ctx);
737 if (ret) {
738 mfc_err("Failed to setup mfc controls\n");
739 goto err_ctrls_setup;
740 }
741 } else if (vdev == dev->vfd_enc) {
742 ctx->type = MFCINST_ENCODER;
743 ctx->c_ops = get_enc_codec_ops();
744 /* only for encoder */
745 INIT_LIST_HEAD(&ctx->ref_queue);
746 ctx->ref_queue_cnt = 0;
747 s5p_mfc_enc_init(ctx);
748 /* Setup ctrl handler */
749 ret = s5p_mfc_enc_ctrls_setup(ctx);
750 if (ret) {
751 mfc_err("Failed to setup mfc controls\n");
752 goto err_ctrls_setup;
753 }
754 } else {
755 ret = -ENOENT;
756 goto err_bad_node;
757 }
758 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
759 ctx->inst_no = -1;
760 /* Load firmware if this is the first instance */
761 if (dev->num_inst == 1) {
762 dev->watchdog_timer.expires = jiffies +
763 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
764 add_timer(&dev->watchdog_timer);
765 ret = s5p_mfc_power_on();
766 if (ret < 0) {
767 mfc_err("power on failed\n");
768 goto err_pwr_enable;
769 }
770 s5p_mfc_clock_on();
771 ret = s5p_mfc_load_firmware(dev);
772 if (ret) {
773 s5p_mfc_clock_off();
774 goto err_load_fw;
775 }
776 /* Init the FW */
777 ret = s5p_mfc_init_hw(dev);
778 s5p_mfc_clock_off();
779 if (ret)
780 goto err_init_hw;
781 }
782 /* Init videobuf2 queue for CAPTURE */
783 q = &ctx->vq_dst;
784 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
785 q->drv_priv = &ctx->fh;
786 if (vdev == dev->vfd_dec) {
787 q->io_modes = VB2_MMAP;
788 q->ops = get_dec_queue_ops();
789 } else if (vdev == dev->vfd_enc) {
790 q->io_modes = VB2_MMAP | VB2_USERPTR;
791 q->ops = get_enc_queue_ops();
792 } else {
793 ret = -ENOENT;
794 goto err_queue_init;
795 }
796 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
797 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
798 ret = vb2_queue_init(q);
799 if (ret) {
800 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
801 goto err_queue_init;
802 }
803 /* Init videobuf2 queue for OUTPUT */
804 q = &ctx->vq_src;
805 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
806 q->io_modes = VB2_MMAP;
807 q->drv_priv = &ctx->fh;
808 if (vdev == dev->vfd_dec) {
809 q->io_modes = VB2_MMAP;
810 q->ops = get_dec_queue_ops();
811 } else if (vdev == dev->vfd_enc) {
812 q->io_modes = VB2_MMAP | VB2_USERPTR;
813 q->ops = get_enc_queue_ops();
814 } else {
815 ret = -ENOENT;
816 goto err_queue_init;
817 }
818 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
819 q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
820 ret = vb2_queue_init(q);
821 if (ret) {
822 mfc_err("Failed to initialize videobuf2 queue(output)\n");
823 goto err_queue_init;
824 }
825 init_waitqueue_head(&ctx->queue);
826 mutex_unlock(&dev->mfc_mutex);
827 mfc_debug_leave();
828 return ret;
829 /* Deinit when failure occurred */
830 err_queue_init:
831 if (dev->num_inst == 1)
832 s5p_mfc_deinit_hw(dev);
833 err_init_hw:
834 err_load_fw:
835 err_pwr_enable:
836 if (dev->num_inst == 1) {
837 if (s5p_mfc_power_off() < 0)
838 mfc_err("power off failed\n");
839 del_timer_sync(&dev->watchdog_timer);
840 }
841 err_ctrls_setup:
842 s5p_mfc_dec_ctrls_delete(ctx);
843 err_bad_node:
844 dev->ctx[ctx->num] = NULL;
845 err_no_ctx:
846 v4l2_fh_del(&ctx->fh);
847 v4l2_fh_exit(&ctx->fh);
848 kfree(ctx);
849 err_alloc:
850 dev->num_inst--;
851 mutex_unlock(&dev->mfc_mutex);
852 mfc_debug_leave();
853 return ret;
854 }
855
856 /* Release MFC context */
857 static int s5p_mfc_release(struct file *file)
858 {
859 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
860 struct s5p_mfc_dev *dev = ctx->dev;
861
862 mfc_debug_enter();
863 mutex_lock(&dev->mfc_mutex);
864 s5p_mfc_clock_on();
865 vb2_queue_release(&ctx->vq_src);
866 vb2_queue_release(&ctx->vq_dst);
867 /* Mark context as idle */
868 clear_work_bit_irqsave(ctx);
869 /* If instance was initialised then
870 * return instance and free resources */
871 if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
872 mfc_debug(2, "Has to free instance\n");
873 ctx->state = MFCINST_RETURN_INST;
874 set_work_bit_irqsave(ctx);
875 s5p_mfc_clean_ctx_int_flags(ctx);
876 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
877 /* Wait until instance is returned or timeout occurred */
878 if (s5p_mfc_wait_for_done_ctx
879 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
880 s5p_mfc_clock_off();
881 mfc_err("Err returning instance\n");
882 }
883 mfc_debug(2, "After free instance\n");
884 /* Free resources */
885 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
886 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
887 if (ctx->type == MFCINST_DECODER)
888 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer,
889 ctx);
890
891 ctx->inst_no = MFC_NO_INSTANCE_SET;
892 }
893 /* hardware locking scheme */
894 if (dev->curr_ctx == ctx->num)
895 clear_bit(0, &dev->hw_lock);
896 dev->num_inst--;
897 if (dev->num_inst == 0) {
898 mfc_debug(2, "Last instance\n");
899 s5p_mfc_deinit_hw(dev);
900 del_timer_sync(&dev->watchdog_timer);
901 if (s5p_mfc_power_off() < 0)
902 mfc_err("Power off failed\n");
903 }
904 mfc_debug(2, "Shutting down clock\n");
905 s5p_mfc_clock_off();
906 dev->ctx[ctx->num] = NULL;
907 s5p_mfc_dec_ctrls_delete(ctx);
908 v4l2_fh_del(&ctx->fh);
909 v4l2_fh_exit(&ctx->fh);
910 kfree(ctx);
911 mfc_debug_leave();
912 mutex_unlock(&dev->mfc_mutex);
913 return 0;
914 }
915
916 /* Poll */
917 static unsigned int s5p_mfc_poll(struct file *file,
918 struct poll_table_struct *wait)
919 {
920 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
921 struct s5p_mfc_dev *dev = ctx->dev;
922 struct vb2_queue *src_q, *dst_q;
923 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
924 unsigned int rc = 0;
925 unsigned long flags;
926
927 mutex_lock(&dev->mfc_mutex);
928 src_q = &ctx->vq_src;
929 dst_q = &ctx->vq_dst;
930 /*
931 * There has to be at least one buffer queued on each queued_list, which
932 * means either in driver already or waiting for driver to claim it
933 * and start processing.
934 */
935 if ((!src_q->streaming || list_empty(&src_q->queued_list))
936 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
937 rc = POLLERR;
938 goto end;
939 }
940 mutex_unlock(&dev->mfc_mutex);
941 poll_wait(file, &ctx->fh.wait, wait);
942 poll_wait(file, &src_q->done_wq, wait);
943 poll_wait(file, &dst_q->done_wq, wait);
944 mutex_lock(&dev->mfc_mutex);
945 if (v4l2_event_pending(&ctx->fh))
946 rc |= POLLPRI;
947 spin_lock_irqsave(&src_q->done_lock, flags);
948 if (!list_empty(&src_q->done_list))
949 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
950 done_entry);
951 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
952 || src_vb->state == VB2_BUF_STATE_ERROR))
953 rc |= POLLOUT | POLLWRNORM;
954 spin_unlock_irqrestore(&src_q->done_lock, flags);
955 spin_lock_irqsave(&dst_q->done_lock, flags);
956 if (!list_empty(&dst_q->done_list))
957 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
958 done_entry);
959 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
960 || dst_vb->state == VB2_BUF_STATE_ERROR))
961 rc |= POLLIN | POLLRDNORM;
962 spin_unlock_irqrestore(&dst_q->done_lock, flags);
963 end:
964 mutex_unlock(&dev->mfc_mutex);
965 return rc;
966 }
967
968 /* Mmap */
969 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
970 {
971 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
972 struct s5p_mfc_dev *dev = ctx->dev;
973 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
974 int ret;
975
976 if (mutex_lock_interruptible(&dev->mfc_mutex))
977 return -ERESTARTSYS;
978 if (offset < DST_QUEUE_OFF_BASE) {
979 mfc_debug(2, "mmaping source\n");
980 ret = vb2_mmap(&ctx->vq_src, vma);
981 } else { /* capture */
982 mfc_debug(2, "mmaping destination\n");
983 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
984 ret = vb2_mmap(&ctx->vq_dst, vma);
985 }
986 mutex_unlock(&dev->mfc_mutex);
987 return ret;
988 }
989
990 /* v4l2 ops */
991 static const struct v4l2_file_operations s5p_mfc_fops = {
992 .owner = THIS_MODULE,
993 .open = s5p_mfc_open,
994 .release = s5p_mfc_release,
995 .poll = s5p_mfc_poll,
996 .unlocked_ioctl = video_ioctl2,
997 .mmap = s5p_mfc_mmap,
998 };
999
1000 static int match_child(struct device *dev, void *data)
1001 {
1002 if (!dev_name(dev))
1003 return 0;
1004 return !strcmp(dev_name(dev), (char *)data);
1005 }
1006
1007 static void *mfc_get_drv_data(struct platform_device *pdev);
1008
1009 static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1010 {
1011 unsigned int mem_info[2] = { };
1012
1013 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1014 sizeof(struct device), GFP_KERNEL);
1015 if (!dev->mem_dev_l) {
1016 mfc_err("Not enough memory\n");
1017 return -ENOMEM;
1018 }
1019 device_initialize(dev->mem_dev_l);
1020 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1021 "samsung,mfc-l", mem_info, 2);
1022 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1023 mem_info[0], mem_info[1],
1024 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1025 mfc_err("Failed to declare coherent memory for\n"
1026 "MFC device\n");
1027 return -ENOMEM;
1028 }
1029
1030 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1031 sizeof(struct device), GFP_KERNEL);
1032 if (!dev->mem_dev_r) {
1033 mfc_err("Not enough memory\n");
1034 return -ENOMEM;
1035 }
1036 device_initialize(dev->mem_dev_r);
1037 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1038 "samsung,mfc-r", mem_info, 2);
1039 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1040 mem_info[0], mem_info[1],
1041 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1042 pr_err("Failed to declare coherent memory for\n"
1043 "MFC device\n");
1044 return -ENOMEM;
1045 }
1046 return 0;
1047 }
1048
1049 /* MFC probe function */
1050 static int s5p_mfc_probe(struct platform_device *pdev)
1051 {
1052 struct s5p_mfc_dev *dev;
1053 struct video_device *vfd;
1054 struct resource *res;
1055 int ret;
1056
1057 pr_debug("%s++\n", __func__);
1058 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1059 if (!dev) {
1060 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1061 return -ENOMEM;
1062 }
1063
1064 spin_lock_init(&dev->irqlock);
1065 spin_lock_init(&dev->condlock);
1066 dev->plat_dev = pdev;
1067 if (!dev->plat_dev) {
1068 dev_err(&pdev->dev, "No platform data specified\n");
1069 return -ENODEV;
1070 }
1071
1072 dev->variant = mfc_get_drv_data(pdev);
1073
1074 ret = s5p_mfc_init_pm(dev);
1075 if (ret < 0) {
1076 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1077 return ret;
1078 }
1079
1080 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1081
1082 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1083 if (IS_ERR(dev->regs_base))
1084 return PTR_ERR(dev->regs_base);
1085
1086 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1087 if (res == NULL) {
1088 dev_err(&pdev->dev, "failed to get irq resource\n");
1089 ret = -ENOENT;
1090 goto err_res;
1091 }
1092 dev->irq = res->start;
1093 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1094 0, pdev->name, dev);
1095 if (ret) {
1096 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1097 goto err_res;
1098 }
1099
1100 if (pdev->dev.of_node) {
1101 ret = s5p_mfc_alloc_memdevs(dev);
1102 if (ret < 0)
1103 goto err_res;
1104 } else {
1105 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1106 "s5p-mfc-l", match_child);
1107 if (!dev->mem_dev_l) {
1108 mfc_err("Mem child (L) device get failed\n");
1109 ret = -ENODEV;
1110 goto err_res;
1111 }
1112 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1113 "s5p-mfc-r", match_child);
1114 if (!dev->mem_dev_r) {
1115 mfc_err("Mem child (R) device get failed\n");
1116 ret = -ENODEV;
1117 goto err_res;
1118 }
1119 }
1120
1121 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1122 if (IS_ERR(dev->alloc_ctx[0])) {
1123 ret = PTR_ERR(dev->alloc_ctx[0]);
1124 goto err_res;
1125 }
1126 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1127 if (IS_ERR(dev->alloc_ctx[1])) {
1128 ret = PTR_ERR(dev->alloc_ctx[1]);
1129 goto err_mem_init_ctx_1;
1130 }
1131
1132 mutex_init(&dev->mfc_mutex);
1133
1134 ret = s5p_mfc_alloc_firmware(dev);
1135 if (ret)
1136 goto err_alloc_fw;
1137
1138 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1139 if (ret)
1140 goto err_v4l2_dev_reg;
1141 init_waitqueue_head(&dev->queue);
1142
1143 /* decoder */
1144 vfd = video_device_alloc();
1145 if (!vfd) {
1146 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1147 ret = -ENOMEM;
1148 goto err_dec_alloc;
1149 }
1150 vfd->fops = &s5p_mfc_fops,
1151 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1152 vfd->release = video_device_release,
1153 vfd->lock = &dev->mfc_mutex;
1154 vfd->v4l2_dev = &dev->v4l2_dev;
1155 vfd->vfl_dir = VFL_DIR_M2M;
1156 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1157 dev->vfd_dec = vfd;
1158 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1159 if (ret) {
1160 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1161 video_device_release(vfd);
1162 goto err_dec_reg;
1163 }
1164 v4l2_info(&dev->v4l2_dev,
1165 "decoder registered as /dev/video%d\n", vfd->num);
1166 video_set_drvdata(vfd, dev);
1167
1168 /* encoder */
1169 vfd = video_device_alloc();
1170 if (!vfd) {
1171 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1172 ret = -ENOMEM;
1173 goto err_enc_alloc;
1174 }
1175 vfd->fops = &s5p_mfc_fops,
1176 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1177 vfd->release = video_device_release,
1178 vfd->lock = &dev->mfc_mutex;
1179 vfd->v4l2_dev = &dev->v4l2_dev;
1180 vfd->vfl_dir = VFL_DIR_M2M;
1181 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1182 dev->vfd_enc = vfd;
1183 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1184 if (ret) {
1185 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1186 video_device_release(vfd);
1187 goto err_enc_reg;
1188 }
1189 v4l2_info(&dev->v4l2_dev,
1190 "encoder registered as /dev/video%d\n", vfd->num);
1191 video_set_drvdata(vfd, dev);
1192 platform_set_drvdata(pdev, dev);
1193
1194 dev->hw_lock = 0;
1195 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1196 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1197 atomic_set(&dev->watchdog_cnt, 0);
1198 init_timer(&dev->watchdog_timer);
1199 dev->watchdog_timer.data = (unsigned long)dev;
1200 dev->watchdog_timer.function = s5p_mfc_watchdog;
1201
1202 /* Initialize HW ops and commands based on MFC version */
1203 s5p_mfc_init_hw_ops(dev);
1204 s5p_mfc_init_hw_cmds(dev);
1205
1206 pr_debug("%s--\n", __func__);
1207 return 0;
1208
1209 /* Deinit MFC if probe had failed */
1210 err_enc_reg:
1211 video_device_release(dev->vfd_enc);
1212 err_enc_alloc:
1213 video_unregister_device(dev->vfd_dec);
1214 err_dec_reg:
1215 video_device_release(dev->vfd_dec);
1216 err_dec_alloc:
1217 v4l2_device_unregister(&dev->v4l2_dev);
1218 err_v4l2_dev_reg:
1219 s5p_mfc_release_firmware(dev);
1220 err_alloc_fw:
1221 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1222 err_mem_init_ctx_1:
1223 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1224 err_res:
1225 s5p_mfc_final_pm(dev);
1226
1227 pr_debug("%s-- with error\n", __func__);
1228 return ret;
1229
1230 }
1231
1232 /* Remove the driver */
1233 static int s5p_mfc_remove(struct platform_device *pdev)
1234 {
1235 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1236
1237 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1238
1239 del_timer_sync(&dev->watchdog_timer);
1240 flush_workqueue(dev->watchdog_workqueue);
1241 destroy_workqueue(dev->watchdog_workqueue);
1242
1243 video_unregister_device(dev->vfd_enc);
1244 video_unregister_device(dev->vfd_dec);
1245 v4l2_device_unregister(&dev->v4l2_dev);
1246 s5p_mfc_release_firmware(dev);
1247 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1248 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1249 if (pdev->dev.of_node) {
1250 put_device(dev->mem_dev_l);
1251 put_device(dev->mem_dev_r);
1252 }
1253
1254 s5p_mfc_final_pm(dev);
1255 return 0;
1256 }
1257
1258 #ifdef CONFIG_PM_SLEEP
1259
1260 static int s5p_mfc_suspend(struct device *dev)
1261 {
1262 struct platform_device *pdev = to_platform_device(dev);
1263 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1264 int ret;
1265
1266 if (m_dev->num_inst == 0)
1267 return 0;
1268
1269 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1270 mfc_err("Error: going to suspend for a second time\n");
1271 return -EIO;
1272 }
1273
1274 /* Check if we're processing then wait if it necessary. */
1275 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1276 /* Try and lock the HW */
1277 /* Wait on the interrupt waitqueue */
1278 ret = wait_event_interruptible_timeout(m_dev->queue,
1279 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1280 if (ret == 0) {
1281 mfc_err("Waiting for hardware to finish timed out\n");
1282 return -EIO;
1283 }
1284 }
1285
1286 return s5p_mfc_sleep(m_dev);
1287 }
1288
1289 static int s5p_mfc_resume(struct device *dev)
1290 {
1291 struct platform_device *pdev = to_platform_device(dev);
1292 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1293
1294 if (m_dev->num_inst == 0)
1295 return 0;
1296 return s5p_mfc_wakeup(m_dev);
1297 }
1298 #endif
1299
1300 #ifdef CONFIG_PM_RUNTIME
1301 static int s5p_mfc_runtime_suspend(struct device *dev)
1302 {
1303 struct platform_device *pdev = to_platform_device(dev);
1304 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1305
1306 atomic_set(&m_dev->pm.power, 0);
1307 return 0;
1308 }
1309
1310 static int s5p_mfc_runtime_resume(struct device *dev)
1311 {
1312 struct platform_device *pdev = to_platform_device(dev);
1313 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1314 int pre_power;
1315
1316 if (!m_dev->alloc_ctx)
1317 return 0;
1318 pre_power = atomic_read(&m_dev->pm.power);
1319 atomic_set(&m_dev->pm.power, 1);
1320 return 0;
1321 }
1322 #endif
1323
1324 /* Power management */
1325 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1326 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1327 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1328 NULL)
1329 };
1330
1331 struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1332 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1333 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1334 .dsc = DESC_BUF_SIZE,
1335 .shm = SHARED_BUF_SIZE,
1336 };
1337
1338 struct s5p_mfc_buf_size buf_size_v5 = {
1339 .fw = MAX_FW_SIZE,
1340 .cpb = MAX_CPB_SIZE,
1341 .priv = &mfc_buf_size_v5,
1342 };
1343
1344 struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1345 .base = MFC_BASE_ALIGN_ORDER,
1346 };
1347
1348 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1349 .version = MFC_VERSION,
1350 .port_num = MFC_NUM_PORTS,
1351 .buf_size = &buf_size_v5,
1352 .buf_align = &mfc_buf_align_v5,
1353 .fw_name = "s5p-mfc.fw",
1354 };
1355
1356 struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1357 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1358 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1359 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1360 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1361 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1362 };
1363
1364 struct s5p_mfc_buf_size buf_size_v6 = {
1365 .fw = MAX_FW_SIZE_V6,
1366 .cpb = MAX_CPB_SIZE_V6,
1367 .priv = &mfc_buf_size_v6,
1368 };
1369
1370 struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1371 .base = 0,
1372 };
1373
1374 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1375 .version = MFC_VERSION_V6,
1376 .port_num = MFC_NUM_PORTS_V6,
1377 .buf_size = &buf_size_v6,
1378 .buf_align = &mfc_buf_align_v6,
1379 .fw_name = "s5p-mfc-v6.fw",
1380 };
1381
1382 struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1383 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1384 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1385 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1386 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1387 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1388 };
1389
1390 struct s5p_mfc_buf_size buf_size_v7 = {
1391 .fw = MAX_FW_SIZE_V7,
1392 .cpb = MAX_CPB_SIZE_V7,
1393 .priv = &mfc_buf_size_v7,
1394 };
1395
1396 struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1397 .base = 0,
1398 };
1399
1400 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1401 .version = MFC_VERSION_V7,
1402 .port_num = MFC_NUM_PORTS_V7,
1403 .buf_size = &buf_size_v7,
1404 .buf_align = &mfc_buf_align_v7,
1405 .fw_name = "s5p-mfc-v7.fw",
1406 };
1407
1408 static struct platform_device_id mfc_driver_ids[] = {
1409 {
1410 .name = "s5p-mfc",
1411 .driver_data = (unsigned long)&mfc_drvdata_v5,
1412 }, {
1413 .name = "s5p-mfc-v5",
1414 .driver_data = (unsigned long)&mfc_drvdata_v5,
1415 }, {
1416 .name = "s5p-mfc-v6",
1417 .driver_data = (unsigned long)&mfc_drvdata_v6,
1418 }, {
1419 .name = "s5p-mfc-v7",
1420 .driver_data = (unsigned long)&mfc_drvdata_v7,
1421 },
1422 {},
1423 };
1424 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1425
1426 static const struct of_device_id exynos_mfc_match[] = {
1427 {
1428 .compatible = "samsung,mfc-v5",
1429 .data = &mfc_drvdata_v5,
1430 }, {
1431 .compatible = "samsung,mfc-v6",
1432 .data = &mfc_drvdata_v6,
1433 }, {
1434 .compatible = "samsung,mfc-v7",
1435 .data = &mfc_drvdata_v7,
1436 },
1437 {},
1438 };
1439 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1440
1441 static void *mfc_get_drv_data(struct platform_device *pdev)
1442 {
1443 struct s5p_mfc_variant *driver_data = NULL;
1444
1445 if (pdev->dev.of_node) {
1446 const struct of_device_id *match;
1447 match = of_match_node(exynos_mfc_match,
1448 pdev->dev.of_node);
1449 if (match)
1450 driver_data = (struct s5p_mfc_variant *)match->data;
1451 } else {
1452 driver_data = (struct s5p_mfc_variant *)
1453 platform_get_device_id(pdev)->driver_data;
1454 }
1455 return driver_data;
1456 }
1457
1458 static struct platform_driver s5p_mfc_driver = {
1459 .probe = s5p_mfc_probe,
1460 .remove = s5p_mfc_remove,
1461 .id_table = mfc_driver_ids,
1462 .driver = {
1463 .name = S5P_MFC_NAME,
1464 .owner = THIS_MODULE,
1465 .pm = &s5p_mfc_pm_ops,
1466 .of_match_table = exynos_mfc_match,
1467 },
1468 };
1469
1470 module_platform_driver(s5p_mfc_driver);
1471
1472 MODULE_LICENSE("GPL");
1473 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1474 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1475
Linux with added FPC-III support