drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c

   1 /*
   2  * linux/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c
   3  *
   4  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include "regs-mfc.h"
  14 #include "s5p_mfc_cmd.h"
  15 #include "s5p_mfc_common.h"
  16 #include "s5p_mfc_debug.h"
  17
  18 /* This function is used to send a command to the MFC */
  19 static int s5p_mfc_cmd_host2risc_v5(struct s5p_mfc_dev *dev, int cmd,
  20                                 struct s5p_mfc_cmd_args *args)
  21 {
  22         int cur_cmd;
  23         unsigned long timeout;
  24
  25         timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
  26         /* wait until host to risc command register becomes 'H2R_CMD_EMPTY' */
  27         do {
  28                 if (time_after(jiffies, timeout)) {
  29                         mfc_err("Timeout while waiting for hardware\n");
  30                         return -EIO;
  31                 }
  32                 cur_cmd = mfc_read(dev, S5P_FIMV_HOST2RISC_CMD);
  33         } while (cur_cmd != S5P_FIMV_H2R_CMD_EMPTY);
  34         mfc_write(dev, args->arg[0], S5P_FIMV_HOST2RISC_ARG1);
  35         mfc_write(dev, args->arg[1], S5P_FIMV_HOST2RISC_ARG2);
  36         mfc_write(dev, args->arg[2], S5P_FIMV_HOST2RISC_ARG3);
  37         mfc_write(dev, args->arg[3], S5P_FIMV_HOST2RISC_ARG4);
  38         /* Issue the command */
  39         mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD);
  40         return 0;
  41 }
  42
  43 /* Initialize the MFC */
  44 static int s5p_mfc_sys_init_cmd_v5(struct s5p_mfc_dev *dev)
  45 {
  46         struct s5p_mfc_cmd_args h2r_args;
  47
  48         memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  49         h2r_args.arg[0] = dev->fw_size;
  50         return s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_SYS_INIT,
  51                         &h2r_args);
  52 }
  53
  54 /* Suspend the MFC hardware */
  55 static int s5p_mfc_sleep_cmd_v5(struct s5p_mfc_dev *dev)
  56 {
  57         struct s5p_mfc_cmd_args h2r_args;
  58
  59         memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  60         return s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_SLEEP, &h2r_args);
  61 }
  62
  63 /* Wake up the MFC hardware */
  64 static int s5p_mfc_wakeup_cmd_v5(struct s5p_mfc_dev *dev)
  65 {
  66         struct s5p_mfc_cmd_args h2r_args;
  67
  68         memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  69         return s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_WAKEUP,
  70                         &h2r_args);
  71 }
  72
  73
  74 static int s5p_mfc_open_inst_cmd_v5(struct s5p_mfc_ctx *ctx)
  75 {
  76         struct s5p_mfc_dev *dev = ctx->dev;
  77         struct s5p_mfc_cmd_args h2r_args;
  78         int ret;
  79
  80         /* Preparing decoding - getting instance number */
  81         mfc_debug(2, "Getting instance number (codec: %d)\n", ctx->codec_mode);
  82         dev->curr_ctx = ctx->num;
  83         memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  84         switch (ctx->codec_mode) {
  85         case S5P_MFC_CODEC_H264_DEC:
  86                 h2r_args.arg[0] = S5P_FIMV_CODEC_H264_DEC;
  87                 break;
  88         case S5P_MFC_CODEC_VC1_DEC:
  89                 h2r_args.arg[0] = S5P_FIMV_CODEC_VC1_DEC;
  90                 break;
  91         case S5P_MFC_CODEC_MPEG4_DEC:
  92                 h2r_args.arg[0] = S5P_FIMV_CODEC_MPEG4_DEC;
  93                 break;
  94         case S5P_MFC_CODEC_MPEG2_DEC:
  95                 h2r_args.arg[0] = S5P_FIMV_CODEC_MPEG2_DEC;
  96                 break;
  97         case S5P_MFC_CODEC_H263_DEC:
  98                 h2r_args.arg[0] = S5P_FIMV_CODEC_H263_DEC;
  99                 break;
 100         case S5P_MFC_CODEC_VC1RCV_DEC:
 101                 h2r_args.arg[0] = S5P_FIMV_CODEC_VC1RCV_DEC;
 102                 break;
 103         case S5P_MFC_CODEC_H264_ENC:
 104                 h2r_args.arg[0] = S5P_FIMV_CODEC_H264_ENC;
 105                 break;
 106         case S5P_MFC_CODEC_MPEG4_ENC:
 107                 h2r_args.arg[0] = S5P_FIMV_CODEC_MPEG4_ENC;
 108                 break;
 109         case S5P_MFC_CODEC_H263_ENC:
 110                 h2r_args.arg[0] = S5P_FIMV_CODEC_H263_ENC;
 111                 break;
 112         default:
 113                 h2r_args.arg[0] = S5P_FIMV_CODEC_NONE;
 114         }
 115         h2r_args.arg[1] = 0; /* no crc & no pixelcache */
 116         h2r_args.arg[2] = ctx->ctx.ofs;
 117         h2r_args.arg[3] = ctx->ctx.size;
 118         ret = s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE,
 119                                                                 &h2r_args);
 120         if (ret) {
 121                 mfc_err("Failed to create a new instance\n");
 122                 ctx->state = MFCINST_ERROR;
 123         }
 124         return ret;
 125 }
 126
 127 static int s5p_mfc_close_inst_cmd_v5(struct s5p_mfc_ctx *ctx)
 128 {
 129         struct s5p_mfc_dev *dev = ctx->dev;
 130         struct s5p_mfc_cmd_args h2r_args;
 131         int ret;
 132
 133         if (ctx->state == MFCINST_FREE) {
 134                 mfc_err("Instance already returned\n");
 135                 ctx->state = MFCINST_ERROR;
 136                 return -EINVAL;
 137         }
 138         /* Closing decoding instance  */
 139         mfc_debug(2, "Returning instance number %d\n", ctx->inst_no);
 140         dev->curr_ctx = ctx->num;
 141         memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
 142         h2r_args.arg[0] = ctx->inst_no;
 143         ret = s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_CLOSE_INSTANCE,
 144                                                                 &h2r_args);
 145         if (ret) {
 146                 mfc_err("Failed to return an instance\n");
 147                 ctx->state = MFCINST_ERROR;
 148                 return -EINVAL;
 149         }
 150         return 0;
 151 }
 152
 153 /* Initialize cmd function pointers for MFC v5 */
 154 static struct s5p_mfc_hw_cmds s5p_mfc_cmds_v5 = {
 155         .cmd_host2risc = s5p_mfc_cmd_host2risc_v5,
 156         .sys_init_cmd = s5p_mfc_sys_init_cmd_v5,
 157         .sleep_cmd = s5p_mfc_sleep_cmd_v5,
 158         .wakeup_cmd = s5p_mfc_wakeup_cmd_v5,
 159         .open_inst_cmd = s5p_mfc_open_inst_cmd_v5,
 160         .close_inst_cmd = s5p_mfc_close_inst_cmd_v5,
 161 };
 162
 163 struct s5p_mfc_hw_cmds *s5p_mfc_init_hw_cmds_v5(void)
 164 {
 165         return &s5p_mfc_cmds_v5;
 166 }