drivers/mfd/mc13xxx-core.c

   1 /*
   2  * Copyright 2009-2010 Pengutronix
   3  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
   4  *
   5  * loosely based on an earlier driver that has
   6  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it under
   9  * the terms of the GNU General Public License version 2 as published by the
  10  * Free Software Foundation.
  11  */
  12
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mutex.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/mfd/core.h>
  19 #include <linux/mfd/mc13xxx.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_gpio.h>
  23
  24 #include "mc13xxx.h"
  25
  26 #define MC13XXX_IRQSTAT0        0
  27 #define MC13XXX_IRQSTAT0_ADCDONEI       (1 << 0)
  28 #define MC13XXX_IRQSTAT0_ADCBISDONEI    (1 << 1)
  29 #define MC13XXX_IRQSTAT0_TSI            (1 << 2)
  30 #define MC13783_IRQSTAT0_WHIGHI         (1 << 3)
  31 #define MC13783_IRQSTAT0_WLOWI          (1 << 4)
  32 #define MC13XXX_IRQSTAT0_CHGDETI        (1 << 6)
  33 #define MC13783_IRQSTAT0_CHGOVI         (1 << 7)
  34 #define MC13XXX_IRQSTAT0_CHGREVI        (1 << 8)
  35 #define MC13XXX_IRQSTAT0_CHGSHORTI      (1 << 9)
  36 #define MC13XXX_IRQSTAT0_CCCVI          (1 << 10)
  37 #define MC13XXX_IRQSTAT0_CHGCURRI       (1 << 11)
  38 #define MC13XXX_IRQSTAT0_BPONI          (1 << 12)
  39 #define MC13XXX_IRQSTAT0_LOBATLI        (1 << 13)
  40 #define MC13XXX_IRQSTAT0_LOBATHI        (1 << 14)
  41 #define MC13783_IRQSTAT0_UDPI           (1 << 15)
  42 #define MC13783_IRQSTAT0_USBI           (1 << 16)
  43 #define MC13783_IRQSTAT0_IDI            (1 << 19)
  44 #define MC13783_IRQSTAT0_SE1I           (1 << 21)
  45 #define MC13783_IRQSTAT0_CKDETI         (1 << 22)
  46 #define MC13783_IRQSTAT0_UDMI           (1 << 23)
  47
  48 #define MC13XXX_IRQMASK0        1
  49 #define MC13XXX_IRQMASK0_ADCDONEM       MC13XXX_IRQSTAT0_ADCDONEI
  50 #define MC13XXX_IRQMASK0_ADCBISDONEM    MC13XXX_IRQSTAT0_ADCBISDONEI
  51 #define MC13XXX_IRQMASK0_TSM            MC13XXX_IRQSTAT0_TSI
  52 #define MC13783_IRQMASK0_WHIGHM         MC13783_IRQSTAT0_WHIGHI
  53 #define MC13783_IRQMASK0_WLOWM          MC13783_IRQSTAT0_WLOWI
  54 #define MC13XXX_IRQMASK0_CHGDETM        MC13XXX_IRQSTAT0_CHGDETI
  55 #define MC13783_IRQMASK0_CHGOVM         MC13783_IRQSTAT0_CHGOVI
  56 #define MC13XXX_IRQMASK0_CHGREVM        MC13XXX_IRQSTAT0_CHGREVI
  57 #define MC13XXX_IRQMASK0_CHGSHORTM      MC13XXX_IRQSTAT0_CHGSHORTI
  58 #define MC13XXX_IRQMASK0_CCCVM          MC13XXX_IRQSTAT0_CCCVI
  59 #define MC13XXX_IRQMASK0_CHGCURRM       MC13XXX_IRQSTAT0_CHGCURRI
  60 #define MC13XXX_IRQMASK0_BPONM          MC13XXX_IRQSTAT0_BPONI
  61 #define MC13XXX_IRQMASK0_LOBATLM        MC13XXX_IRQSTAT0_LOBATLI
  62 #define MC13XXX_IRQMASK0_LOBATHM        MC13XXX_IRQSTAT0_LOBATHI
  63 #define MC13783_IRQMASK0_UDPM           MC13783_IRQSTAT0_UDPI
  64 #define MC13783_IRQMASK0_USBM           MC13783_IRQSTAT0_USBI
  65 #define MC13783_IRQMASK0_IDM            MC13783_IRQSTAT0_IDI
  66 #define MC13783_IRQMASK0_SE1M           MC13783_IRQSTAT0_SE1I
  67 #define MC13783_IRQMASK0_CKDETM         MC13783_IRQSTAT0_CKDETI
  68 #define MC13783_IRQMASK0_UDMM           MC13783_IRQSTAT0_UDMI
  69
  70 #define MC13XXX_IRQSTAT1        3
  71 #define MC13XXX_IRQSTAT1_1HZI           (1 << 0)
  72 #define MC13XXX_IRQSTAT1_TODAI          (1 << 1)
  73 #define MC13783_IRQSTAT1_ONOFD1I        (1 << 3)
  74 #define MC13783_IRQSTAT1_ONOFD2I        (1 << 4)
  75 #define MC13783_IRQSTAT1_ONOFD3I        (1 << 5)
  76 #define MC13XXX_IRQSTAT1_SYSRSTI        (1 << 6)
  77 #define MC13XXX_IRQSTAT1_RTCRSTI        (1 << 7)
  78 #define MC13XXX_IRQSTAT1_PCI            (1 << 8)
  79 #define MC13XXX_IRQSTAT1_WARMI          (1 << 9)
  80 #define MC13XXX_IRQSTAT1_MEMHLDI        (1 << 10)
  81 #define MC13783_IRQSTAT1_PWRRDYI        (1 << 11)
  82 #define MC13XXX_IRQSTAT1_THWARNLI       (1 << 12)
  83 #define MC13XXX_IRQSTAT1_THWARNHI       (1 << 13)
  84 #define MC13XXX_IRQSTAT1_CLKI           (1 << 14)
  85 #define MC13783_IRQSTAT1_SEMAFI         (1 << 15)
  86 #define MC13783_IRQSTAT1_MC2BI          (1 << 17)
  87 #define MC13783_IRQSTAT1_HSDETI         (1 << 18)
  88 #define MC13783_IRQSTAT1_HSLI           (1 << 19)
  89 #define MC13783_IRQSTAT1_ALSPTHI        (1 << 20)
  90 #define MC13783_IRQSTAT1_AHSSHORTI      (1 << 21)
  91
  92 #define MC13XXX_IRQMASK1        4
  93 #define MC13XXX_IRQMASK1_1HZM           MC13XXX_IRQSTAT1_1HZI
  94 #define MC13XXX_IRQMASK1_TODAM          MC13XXX_IRQSTAT1_TODAI
  95 #define MC13783_IRQMASK1_ONOFD1M        MC13783_IRQSTAT1_ONOFD1I
  96 #define MC13783_IRQMASK1_ONOFD2M        MC13783_IRQSTAT1_ONOFD2I
  97 #define MC13783_IRQMASK1_ONOFD3M        MC13783_IRQSTAT1_ONOFD3I
  98 #define MC13XXX_IRQMASK1_SYSRSTM        MC13XXX_IRQSTAT1_SYSRSTI
  99 #define MC13XXX_IRQMASK1_RTCRSTM        MC13XXX_IRQSTAT1_RTCRSTI
 100 #define MC13XXX_IRQMASK1_PCM            MC13XXX_IRQSTAT1_PCI
 101 #define MC13XXX_IRQMASK1_WARMM          MC13XXX_IRQSTAT1_WARMI
 102 #define MC13XXX_IRQMASK1_MEMHLDM        MC13XXX_IRQSTAT1_MEMHLDI
 103 #define MC13783_IRQMASK1_PWRRDYM        MC13783_IRQSTAT1_PWRRDYI
 104 #define MC13XXX_IRQMASK1_THWARNLM       MC13XXX_IRQSTAT1_THWARNLI
 105 #define MC13XXX_IRQMASK1_THWARNHM       MC13XXX_IRQSTAT1_THWARNHI
 106 #define MC13XXX_IRQMASK1_CLKM           MC13XXX_IRQSTAT1_CLKI
 107 #define MC13783_IRQMASK1_SEMAFM         MC13783_IRQSTAT1_SEMAFI
 108 #define MC13783_IRQMASK1_MC2BM          MC13783_IRQSTAT1_MC2BI
 109 #define MC13783_IRQMASK1_HSDETM         MC13783_IRQSTAT1_HSDETI
 110 #define MC13783_IRQMASK1_HSLM           MC13783_IRQSTAT1_HSLI
 111 #define MC13783_IRQMASK1_ALSPTHM        MC13783_IRQSTAT1_ALSPTHI
 112 #define MC13783_IRQMASK1_AHSSHORTM      MC13783_IRQSTAT1_AHSSHORTI
 113
 114 #define MC13XXX_REVISION        7
 115 #define MC13XXX_REVISION_REVMETAL       (0x07 <<  0)
 116 #define MC13XXX_REVISION_REVFULL        (0x03 <<  3)
 117 #define MC13XXX_REVISION_ICID           (0x07 <<  6)
 118 #define MC13XXX_REVISION_FIN            (0x03 <<  9)
 119 #define MC13XXX_REVISION_FAB            (0x03 << 11)
 120 #define MC13XXX_REVISION_ICIDCODE       (0x3f << 13)
 121
 122 #define MC34708_REVISION_REVMETAL       (0x07 <<  0)
 123 #define MC34708_REVISION_REVFULL        (0x07 <<  3)
 124 #define MC34708_REVISION_FIN            (0x07 <<  6)
 125 #define MC34708_REVISION_FAB            (0x07 <<  9)
 126
 127 #define MC13XXX_ADC1            44
 128 #define MC13XXX_ADC1_ADEN               (1 << 0)
 129 #define MC13XXX_ADC1_RAND               (1 << 1)
 130 #define MC13XXX_ADC1_ADSEL              (1 << 3)
 131 #define MC13XXX_ADC1_ASC                (1 << 20)
 132 #define MC13XXX_ADC1_ADTRIGIGN          (1 << 21)
 133
 134 #define MC13XXX_ADC2            45
 135
 136 void mc13xxx_lock(struct mc13xxx *mc13xxx)
 137 {
 138         if (!mutex_trylock(&mc13xxx->lock)) {
 139                 dev_dbg(mc13xxx->dev, "wait for %s from %pf\n",
 140                                 __func__, __builtin_return_address(0));
 141
 142                 mutex_lock(&mc13xxx->lock);
 143         }
 144         dev_dbg(mc13xxx->dev, "%s from %pf\n",
 145                         __func__, __builtin_return_address(0));
 146 }
 147 EXPORT_SYMBOL(mc13xxx_lock);
 148
 149 void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 150 {
 151         dev_dbg(mc13xxx->dev, "%s from %pf\n",
 152                         __func__, __builtin_return_address(0));
 153         mutex_unlock(&mc13xxx->lock);
 154 }
 155 EXPORT_SYMBOL(mc13xxx_unlock);
 156
 157 int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 158 {
 159         int ret;
 160
 161         ret = regmap_read(mc13xxx->regmap, offset, val);
 162         dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 163
 164         return ret;
 165 }
 166 EXPORT_SYMBOL(mc13xxx_reg_read);
 167
 168 int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 169 {
 170         dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
 171
 172         if (val >= BIT(24))
 173                 return -EINVAL;
 174
 175         return regmap_write(mc13xxx->regmap, offset, val);
 176 }
 177 EXPORT_SYMBOL(mc13xxx_reg_write);
 178
 179 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
 180                 u32 mask, u32 val)
 181 {
 182         BUG_ON(val & ~mask);
 183         dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
 184                         offset, val, mask);
 185
 186         return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
 187 }
 188 EXPORT_SYMBOL(mc13xxx_reg_rmw);
 189
 190 int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
 191 {
 192         int ret;
 193         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 194         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 195         u32 mask;
 196
 197         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 198                 return -EINVAL;
 199
 200         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 201         if (ret)
 202                 return ret;
 203
 204         if (mask & irqbit)
 205                 /* already masked */
 206                 return 0;
 207
 208         return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
 209 }
 210 EXPORT_SYMBOL(mc13xxx_irq_mask);
 211
 212 int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
 213 {
 214         int ret;
 215         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 216         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 217         u32 mask;
 218
 219         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 220                 return -EINVAL;
 221
 222         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 223         if (ret)
 224                 return ret;
 225
 226         if (!(mask & irqbit))
 227                 /* already unmasked */
 228                 return 0;
 229
 230         return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
 231 }
 232 EXPORT_SYMBOL(mc13xxx_irq_unmask);
 233
 234 int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
 235                 int *enabled, int *pending)
 236 {
 237         int ret;
 238         unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
 239         unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 240         u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
 241
 242         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 243                 return -EINVAL;
 244
 245         if (enabled) {
 246                 u32 mask;
 247
 248                 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 249                 if (ret)
 250                         return ret;
 251
 252                 *enabled = mask & irqbit;
 253         }
 254
 255         if (pending) {
 256                 u32 stat;
 257
 258                 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 259                 if (ret)
 260                         return ret;
 261
 262                 *pending = stat & irqbit;
 263         }
 264
 265         return 0;
 266 }
 267 EXPORT_SYMBOL(mc13xxx_irq_status);
 268
 269 int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
 270 {
 271         unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
 272         unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
 273
 274         BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
 275
 276         return mc13xxx_reg_write(mc13xxx, offstat, val);
 277 }
 278 EXPORT_SYMBOL(mc13xxx_irq_ack);
 279
 280 int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
 281                 irq_handler_t handler, const char *name, void *dev)
 282 {
 283         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 284         BUG_ON(!handler);
 285
 286         if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
 287                 return -EINVAL;
 288
 289         if (mc13xxx->irqhandler[irq])
 290                 return -EBUSY;
 291
 292         mc13xxx->irqhandler[irq] = handler;
 293         mc13xxx->irqdata[irq] = dev;
 294
 295         return 0;
 296 }
 297 EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
 298
 299 int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
 300                 irq_handler_t handler, const char *name, void *dev)
 301 {
 302         int ret;
 303
 304         ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
 305         if (ret)
 306                 return ret;
 307
 308         ret = mc13xxx_irq_unmask(mc13xxx, irq);
 309         if (ret) {
 310                 mc13xxx->irqhandler[irq] = NULL;
 311                 mc13xxx->irqdata[irq] = NULL;
 312                 return ret;
 313         }
 314
 315         return 0;
 316 }
 317 EXPORT_SYMBOL(mc13xxx_irq_request);
 318
 319 int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
 320 {
 321         int ret;
 322         BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 323
 324         if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
 325                         mc13xxx->irqdata[irq] != dev)
 326                 return -EINVAL;
 327
 328         ret = mc13xxx_irq_mask(mc13xxx, irq);
 329         if (ret)
 330                 return ret;
 331
 332         mc13xxx->irqhandler[irq] = NULL;
 333         mc13xxx->irqdata[irq] = NULL;
 334
 335         return 0;
 336 }
 337 EXPORT_SYMBOL(mc13xxx_irq_free);
 338
 339 static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
 340 {
 341         return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
 342 }
 343
 344 /*
 345  * returns: number of handled irqs or negative error
 346  * locking: holds mc13xxx->lock
 347  */
 348 static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
 349                 unsigned int offstat, unsigned int offmask, int baseirq)
 350 {
 351         u32 stat, mask;
 352         int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
 353         int num_handled = 0;
 354
 355         if (ret)
 356                 return ret;
 357
 358         ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
 359         if (ret)
 360                 return ret;
 361
 362         while (stat & ~mask) {
 363                 int irq = __ffs(stat & ~mask);
 364
 365                 stat &= ~(1 << irq);
 366
 367                 if (likely(mc13xxx->irqhandler[baseirq + irq])) {
 368                         irqreturn_t handled;
 369
 370                         handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
 371                         if (handled == IRQ_HANDLED)
 372                                 num_handled++;
 373                 } else {
 374                         dev_err(mc13xxx->dev,
 375                                         "BUG: irq %u but no handler\n",
 376                                         baseirq + irq);
 377
 378                         mask |= 1 << irq;
 379
 380                         ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
 381                 }
 382         }
 383
 384         return num_handled;
 385 }
 386
 387 static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
 388 {
 389         struct mc13xxx *mc13xxx = data;
 390         irqreturn_t ret;
 391         int handled = 0;
 392
 393         mc13xxx_lock(mc13xxx);
 394
 395         ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
 396                         MC13XXX_IRQMASK0, 0);
 397         if (ret > 0)
 398                 handled = 1;
 399
 400         ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
 401                         MC13XXX_IRQMASK1, 24);
 402         if (ret > 0)
 403                 handled = 1;
 404
 405         mc13xxx_unlock(mc13xxx);
 406
 407         return IRQ_RETVAL(handled);
 408 }
 409
 410 #define maskval(reg, mask)      (((reg) & (mask)) >> __ffs(mask))
 411 static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
 412 {
 413         dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
 414                         "fin: %d, fab: %d, icid: %d/%d\n",
 415                         mc13xxx->variant->name,
 416                         maskval(revision, MC13XXX_REVISION_REVFULL),
 417                         maskval(revision, MC13XXX_REVISION_REVMETAL),
 418                         maskval(revision, MC13XXX_REVISION_FIN),
 419                         maskval(revision, MC13XXX_REVISION_FAB),
 420                         maskval(revision, MC13XXX_REVISION_ICID),
 421                         maskval(revision, MC13XXX_REVISION_ICIDCODE));
 422 }
 423
 424 static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
 425 {
 426         dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
 427                         mc13xxx->variant->name,
 428                         maskval(revision, MC34708_REVISION_REVFULL),
 429                         maskval(revision, MC34708_REVISION_REVMETAL),
 430                         maskval(revision, MC34708_REVISION_FIN),
 431                         maskval(revision, MC34708_REVISION_FAB));
 432 }
 433
 434 /* These are only exported for mc13xxx-i2c and mc13xxx-spi */
 435 struct mc13xxx_variant mc13xxx_variant_mc13783 = {
 436         .name = "mc13783",
 437         .print_revision = mc13xxx_print_revision,
 438 };
 439 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);
 440
 441 struct mc13xxx_variant mc13xxx_variant_mc13892 = {
 442         .name = "mc13892",
 443         .print_revision = mc13xxx_print_revision,
 444 };
 445 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);
 446
 447 struct mc13xxx_variant mc13xxx_variant_mc34708 = {
 448         .name = "mc34708",
 449         .print_revision = mc34708_print_revision,
 450 };
 451 EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);
 452
 453 static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
 454 {
 455         return mc13xxx->variant->name;
 456 }
 457
 458 int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
 459 {
 460         return mc13xxx->flags;
 461 }
 462 EXPORT_SYMBOL(mc13xxx_get_flags);
 463
 464 #define MC13XXX_ADC1_CHAN0_SHIFT        5
 465 #define MC13XXX_ADC1_CHAN1_SHIFT        8
 466 #define MC13783_ADC1_ATO_SHIFT          11
 467 #define MC13783_ADC1_ATOX               (1 << 19)
 468
 469 struct mc13xxx_adcdone_data {
 470         struct mc13xxx *mc13xxx;
 471         struct completion done;
 472 };
 473
 474 static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
 475 {
 476         struct mc13xxx_adcdone_data *adcdone_data = data;
 477
 478         mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
 479
 480         complete_all(&adcdone_data->done);
 481
 482         return IRQ_HANDLED;
 483 }
 484
 485 #define MC13XXX_ADC_WORKING (1 << 0)
 486
 487 int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 488                 unsigned int channel, u8 ato, bool atox,
 489                 unsigned int *sample)
 490 {
 491         u32 adc0, adc1, old_adc0;
 492         int i, ret;
 493         struct mc13xxx_adcdone_data adcdone_data = {
 494                 .mc13xxx = mc13xxx,
 495         };
 496         init_completion(&adcdone_data.done);
 497
 498         dev_dbg(mc13xxx->dev, "%s\n", __func__);
 499
 500         mc13xxx_lock(mc13xxx);
 501
 502         if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
 503                 ret = -EBUSY;
 504                 goto out;
 505         }
 506
 507         mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
 508
 509         mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
 510
 511         adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2;
 512         adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
 513
 514         if (channel > 7)
 515                 adc1 |= MC13XXX_ADC1_ADSEL;
 516
 517         switch (mode) {
 518         case MC13XXX_ADC_MODE_TS:
 519                 adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
 520                         MC13XXX_ADC0_TSMOD1;
 521                 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 522                 break;
 523
 524         case MC13XXX_ADC_MODE_SINGLE_CHAN:
 525                 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
 526                 adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
 527                 adc1 |= MC13XXX_ADC1_RAND;
 528                 break;
 529
 530         case MC13XXX_ADC_MODE_MULT_CHAN:
 531                 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
 532                 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
 533                 break;
 534
 535         default:
 536                 mc13xxx_unlock(mc13xxx);
 537                 return -EINVAL;
 538         }
 539
 540         adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
 541         if (atox)
 542                 adc1 |= MC13783_ADC1_ATOX;
 543
 544         dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
 545         mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
 546                         mc13xxx_handler_adcdone, __func__, &adcdone_data);
 547         mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
 548
 549         mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
 550         mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
 551
 552         mc13xxx_unlock(mc13xxx);
 553
 554         ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
 555
 556         if (!ret)
 557                 ret = -ETIMEDOUT;
 558
 559         mc13xxx_lock(mc13xxx);
 560
 561         mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
 562
 563         if (ret > 0)
 564                 for (i = 0; i < 4; ++i) {
 565                         ret = mc13xxx_reg_read(mc13xxx,
 566                                         MC13XXX_ADC2, &sample[i]);
 567                         if (ret)
 568                                 break;
 569                 }
 570
 571         if (mode == MC13XXX_ADC_MODE_TS)
 572                 /* restore TSMOD */
 573                 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
 574
 575         mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
 576 out:
 577         mc13xxx_unlock(mc13xxx);
 578
 579         return ret;
 580 }
 581 EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
 582
 583 static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
 584                 const char *format, void *pdata, size_t pdata_size)
 585 {
 586         char buf[30];
 587         const char *name = mc13xxx_get_chipname(mc13xxx);
 588
 589         struct mfd_cell cell = {
 590                 .platform_data = pdata,
 591                 .pdata_size = pdata_size,
 592         };
 593
 594         /* there is no asnprintf in the kernel :-( */
 595         if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
 596                 return -E2BIG;
 597
 598         cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
 599         if (!cell.name)
 600                 return -ENOMEM;
 601
 602         return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0, NULL);
 603 }
 604
 605 static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
 606 {
 607         return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
 608 }
 609
 610 #ifdef CONFIG_OF
 611 static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 612 {
 613         struct device_node *np = mc13xxx->dev->of_node;
 614
 615         if (!np)
 616                 return -ENODEV;
 617
 618         if (of_get_property(np, "fsl,mc13xxx-uses-adc", NULL))
 619                 mc13xxx->flags |= MC13XXX_USE_ADC;
 620
 621         if (of_get_property(np, "fsl,mc13xxx-uses-codec", NULL))
 622                 mc13xxx->flags |= MC13XXX_USE_CODEC;
 623
 624         if (of_get_property(np, "fsl,mc13xxx-uses-rtc", NULL))
 625                 mc13xxx->flags |= MC13XXX_USE_RTC;
 626
 627         if (of_get_property(np, "fsl,mc13xxx-uses-touch", NULL))
 628                 mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
 629
 630         return 0;
 631 }
 632 #else
 633 static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 634 {
 635         return -ENODEV;
 636 }
 637 #endif
 638
 639 int mc13xxx_common_init(struct device *dev)
 640 {
 641         struct mc13xxx_platform_data *pdata = dev_get_platdata(dev);
 642         struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
 643         int ret;
 644         u32 revision;
 645
 646         mc13xxx->dev = dev;
 647
 648         ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
 649         if (ret)
 650                 return ret;
 651
 652         mc13xxx->variant->print_revision(mc13xxx, revision);
 653
 654         /* mask all irqs */
 655         ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
 656         if (ret)
 657                 return ret;
 658
 659         ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
 660         if (ret)
 661                 return ret;
 662
 663         ret = request_threaded_irq(mc13xxx->irq, NULL, mc13xxx_irq_thread,
 664                         IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
 665         if (ret)
 666                 return ret;
 667
 668         mutex_init(&mc13xxx->lock);
 669
 670         if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
 671                 mc13xxx->flags = pdata->flags;
 672
 673         if (mc13xxx->flags & MC13XXX_USE_ADC)
 674                 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
 675
 676         if (mc13xxx->flags & MC13XXX_USE_CODEC)
 677                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
 678                                         pdata->codec, sizeof(*pdata->codec));
 679
 680         if (mc13xxx->flags & MC13XXX_USE_RTC)
 681                 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
 682
 683         if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
 684                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
 685                                 &pdata->touch, sizeof(pdata->touch));
 686
 687         if (pdata) {
 688                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
 689                         &pdata->regulators, sizeof(pdata->regulators));
 690                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
 691                                 pdata->leds, sizeof(*pdata->leds));
 692                 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
 693                                 pdata->buttons, sizeof(*pdata->buttons));
 694         } else {
 695                 mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
 696                 mc13xxx_add_subdevice(mc13xxx, "%s-led");
 697                 mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
 698         }
 699
 700         return 0;
 701 }
 702 EXPORT_SYMBOL_GPL(mc13xxx_common_init);
 703
 704 int mc13xxx_common_exit(struct device *dev)
 705 {
 706         struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
 707
 708         free_irq(mc13xxx->irq, mc13xxx);
 709         mfd_remove_devices(dev);
 710         mutex_destroy(&mc13xxx->lock);
 711
 712         return 0;
 713 }
 714 EXPORT_SYMBOL_GPL(mc13xxx_common_exit);
 715
 716 MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
 717 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
 718 MODULE_LICENSE("GPL v2");