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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / mfd / twl6030-irq.c
blob18a607e2ca0607d5fb80c765a53f5f8c13352b6f
1 /*
2 * twl6030-irq.c - TWL6030 irq support
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 *
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
8 *
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
11 *
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
14 *
15 * TWL6030 specific code and IRQ handling changes by
16 * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
17 * Balaji T K <balajitk@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 */
33
34 #include <linux/init.h>
35 #include <linux/export.h>
36 #include <linux/interrupt.h>
37 #include <linux/irq.h>
38 #include <linux/kthread.h>
39 #include <linux/i2c/twl.h>
40 #include <linux/platform_device.h>
41 #include <linux/suspend.h>
42 #include <linux/of.h>
43 #include <linux/irqdomain.h>
44 #include <linux/of_device.h>
45
46 #include "twl-core.h"
47
48 /*
49 * TWL6030 (unlike its predecessors, which had two level interrupt handling)
50 * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
51 * It exposes status bits saying who has raised an interrupt. There are
52 * three mask registers that corresponds to these status registers, that
53 * enables/disables these interrupts.
54 *
55 * We set up IRQs starting at a platform-specified base. An interrupt map table,
56 * specifies mapping between interrupt number and the associated module.
57 */
58 #define TWL6030_NR_IRQS 20
59
60 static int twl6030_interrupt_mapping[24] = {
61 PWR_INTR_OFFSET, /* Bit 0 PWRON */
62 PWR_INTR_OFFSET, /* Bit 1 RPWRON */
63 PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
64 RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
65 RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
66 HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
67 SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
68 SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
69
70 SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
71 BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
72 SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
73 MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
74 RSV_INTR_OFFSET, /* Bit 12 Reserved */
75 MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
76 MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
77 GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
78
79 USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
80 USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
81 USBOTG_INTR_OFFSET, /* Bit 18 ID */
82 USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
83 CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
84 CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
85 CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
86 RSV_INTR_OFFSET, /* Bit 23 Reserved */
87 };
88
89 static int twl6032_interrupt_mapping[24] = {
90 PWR_INTR_OFFSET, /* Bit 0 PWRON */
91 PWR_INTR_OFFSET, /* Bit 1 RPWRON */
92 PWR_INTR_OFFSET, /* Bit 2 SYS_VLOW */
93 RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
94 RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
95 HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
96 SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
97 PWR_INTR_OFFSET, /* Bit 7 SPDURATION */
98
99 PWR_INTR_OFFSET, /* Bit 8 WATCHDOG */
100 BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
101 SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
102 MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
103 MADC_INTR_OFFSET, /* Bit 12 GPADC_RT_EOC */
104 MADC_INTR_OFFSET, /* Bit 13 GPADC_SW_EOC */
105 GASGAUGE_INTR_OFFSET, /* Bit 14 CC_EOC */
106 GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
107
108 USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
109 USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
110 USBOTG_INTR_OFFSET, /* Bit 18 ID */
111 USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
112 CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
113 CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
114 CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
115 RSV_INTR_OFFSET, /* Bit 23 Reserved */
116 };
117
118 /*----------------------------------------------------------------------*/
119
120 struct twl6030_irq {
121 unsigned int irq_base;
122 int twl_irq;
123 bool irq_wake_enabled;
124 atomic_t wakeirqs;
125 struct notifier_block pm_nb;
126 struct irq_chip irq_chip;
127 struct irq_domain *irq_domain;
128 const int *irq_mapping_tbl;
129 };
130
131 static struct twl6030_irq *twl6030_irq;
132
133 static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
134 unsigned long pm_event, void *unused)
135 {
136 int chained_wakeups;
137 struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
138 pm_nb);
139
140 switch (pm_event) {
141 case PM_SUSPEND_PREPARE:
142 chained_wakeups = atomic_read(&pdata->wakeirqs);
143
144 if (chained_wakeups && !pdata->irq_wake_enabled) {
145 if (enable_irq_wake(pdata->twl_irq))
146 pr_err("twl6030 IRQ wake enable failed\n");
147 else
148 pdata->irq_wake_enabled = true;
149 } else if (!chained_wakeups && pdata->irq_wake_enabled) {
150 disable_irq_wake(pdata->twl_irq);
151 pdata->irq_wake_enabled = false;
152 }
153
154 disable_irq(pdata->twl_irq);
155 break;
156
157 case PM_POST_SUSPEND:
158 enable_irq(pdata->twl_irq);
159 break;
160
161 default:
162 break;
163 }
164
165 return NOTIFY_DONE;
166 }
167
168 /*
169 * Threaded irq handler for the twl6030 interrupt.
170 * We query the interrupt controller in the twl6030 to determine
171 * which module is generating the interrupt request and call
172 * handle_nested_irq for that module.
173 */
174 static irqreturn_t twl6030_irq_thread(int irq, void *data)
175 {
176 int i, ret;
177 union {
178 u8 bytes[4];
179 __le32 int_sts;
180 } sts;
181 u32 int_sts; /* sts.int_sts converted to CPU endianness */
182 struct twl6030_irq *pdata = data;
183
184 /* read INT_STS_A, B and C in one shot using a burst read */
185 ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
186 if (ret) {
187 pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
188 return IRQ_HANDLED;
189 }
190
191 sts.bytes[3] = 0; /* Only 24 bits are valid*/
192
193 /*
194 * Since VBUS status bit is not reliable for VBUS disconnect
195 * use CHARGER VBUS detection status bit instead.
196 */
197 if (sts.bytes[2] & 0x10)
198 sts.bytes[2] |= 0x08;
199
200 int_sts = le32_to_cpu(sts.int_sts);
201 for (i = 0; int_sts; int_sts >>= 1, i++)
202 if (int_sts & 0x1) {
203 int module_irq =
204 irq_find_mapping(pdata->irq_domain,
205 pdata->irq_mapping_tbl[i]);
206 if (module_irq)
207 handle_nested_irq(module_irq);
208 else
209 pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
210 i);
211 pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
212 i, module_irq);
213 }
214
215 /*
216 * NOTE:
217 * Simulation confirms that documentation is wrong w.r.t the
218 * interrupt status clear operation. A single *byte* write to
219 * any one of STS_A to STS_C register results in all three
220 * STS registers being reset. Since it does not matter which
221 * value is written, all three registers are cleared on a
222 * single byte write, so we just use 0x0 to clear.
223 */
224 ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
225 if (ret)
226 pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
227
228 return IRQ_HANDLED;
229 }
230
231 /*----------------------------------------------------------------------*/
232
233 static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
234 {
235 struct twl6030_irq *pdata = irq_get_chip_data(d->irq);
236
237 if (on)
238 atomic_inc(&pdata->wakeirqs);
239 else
240 atomic_dec(&pdata->wakeirqs);
241
242 return 0;
243 }
244
245 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
246 {
247 int ret;
248 u8 unmask_value;
249 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
250 REG_INT_STS_A + offset);
251 unmask_value &= (~(bit_mask));
252 ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
253 REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
254 return ret;
255 }
256 EXPORT_SYMBOL(twl6030_interrupt_unmask);
257
258 int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
259 {
260 int ret;
261 u8 mask_value;
262 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
263 REG_INT_STS_A + offset);
264 mask_value |= (bit_mask);
265 ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
266 REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
267 return ret;
268 }
269 EXPORT_SYMBOL(twl6030_interrupt_mask);
270
271 int twl6030_mmc_card_detect_config(void)
272 {
273 int ret;
274 u8 reg_val = 0;
275
276 /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
277 twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
278 REG_INT_MSK_LINE_B);
279 twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
280 REG_INT_MSK_STS_B);
281 /*
282 * Initially Configuring MMC_CTRL for receiving interrupts &
283 * Card status on TWL6030 for MMC1
284 */
285 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
286 if (ret < 0) {
287 pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
288 return ret;
289 }
290 reg_val &= ~VMMC_AUTO_OFF;
291 reg_val |= SW_FC;
292 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
293 if (ret < 0) {
294 pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
295 return ret;
296 }
297
298 /* Configuring PullUp-PullDown register */
299 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
300 TWL6030_CFG_INPUT_PUPD3);
301 if (ret < 0) {
302 pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
303 ret);
304 return ret;
305 }
306 reg_val &= ~(MMC_PU | MMC_PD);
307 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
308 TWL6030_CFG_INPUT_PUPD3);
309 if (ret < 0) {
310 pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
311 ret);
312 return ret;
313 }
314
315 return irq_find_mapping(twl6030_irq->irq_domain,
316 MMCDETECT_INTR_OFFSET);
317 }
318 EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
319
320 int twl6030_mmc_card_detect(struct device *dev, int slot)
321 {
322 int ret = -EIO;
323 u8 read_reg = 0;
324 struct platform_device *pdev = to_platform_device(dev);
325
326 if (pdev->id) {
327 /* TWL6030 provide's Card detect support for
328 * only MMC1 controller.
329 */
330 pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
331 return ret;
332 }
333 /*
334 * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
335 * 0 - Card not present ,1 - Card present
336 */
337 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
338 TWL6030_MMCCTRL);
339 if (ret >= 0)
340 ret = read_reg & STS_MMC;
341 return ret;
342 }
343 EXPORT_SYMBOL(twl6030_mmc_card_detect);
344
345 static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
346 irq_hw_number_t hwirq)
347 {
348 struct twl6030_irq *pdata = d->host_data;
349
350 irq_set_chip_data(virq, pdata);
351 irq_set_chip_and_handler(virq, &pdata->irq_chip, handle_simple_irq);
352 irq_set_nested_thread(virq, true);
353 irq_set_parent(virq, pdata->twl_irq);
354
355 #ifdef CONFIG_ARM
356 /*
357 * ARM requires an extra step to clear IRQ_NOREQUEST, which it
358 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
359 */
360 set_irq_flags(virq, IRQF_VALID);
361 #else
362 /* same effect on other architectures */
363 irq_set_noprobe(virq);
364 #endif
365
366 return 0;
367 }
368
369 static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
370 {
371 #ifdef CONFIG_ARM
372 set_irq_flags(virq, 0);
373 #endif
374 irq_set_chip_and_handler(virq, NULL, NULL);
375 irq_set_chip_data(virq, NULL);
376 }
377
378 static struct irq_domain_ops twl6030_irq_domain_ops = {
379 .map = twl6030_irq_map,
380 .unmap = twl6030_irq_unmap,
381 .xlate = irq_domain_xlate_onetwocell,
382 };
383
384 static const struct of_device_id twl6030_of_match[] = {
385 {.compatible = "ti,twl6030", &twl6030_interrupt_mapping},
386 {.compatible = "ti,twl6032", &twl6032_interrupt_mapping},
387 { },
388 };
389
390 int twl6030_init_irq(struct device *dev, int irq_num)
391 {
392 struct device_node *node = dev->of_node;
393 int nr_irqs;
394 int status;
395 u8 mask[3];
396 const struct of_device_id *of_id;
397
398 of_id = of_match_device(twl6030_of_match, dev);
399 if (!of_id || !of_id->data) {
400 dev_err(dev, "Unknown TWL device model\n");
401 return -EINVAL;
402 }
403
404 nr_irqs = TWL6030_NR_IRQS;
405
406 twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
407 if (!twl6030_irq) {
408 dev_err(dev, "twl6030_irq: Memory allocation failed\n");
409 return -ENOMEM;
410 }
411
412 mask[0] = 0xFF;
413 mask[1] = 0xFF;
414 mask[2] = 0xFF;
415
416 /* mask all int lines */
417 status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
418 /* mask all int sts */
419 status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
420 /* clear INT_STS_A,B,C */
421 status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
422
423 if (status < 0) {
424 dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
425 return status;
426 }
427
428 /*
429 * install an irq handler for each of the modules;
430 * clone dummy irq_chip since PIH can't *do* anything
431 */
432 twl6030_irq->irq_chip = dummy_irq_chip;
433 twl6030_irq->irq_chip.name = "twl6030";
434 twl6030_irq->irq_chip.irq_set_type = NULL;
435 twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;
436
437 twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
438 atomic_set(&twl6030_irq->wakeirqs, 0);
439 twl6030_irq->irq_mapping_tbl = of_id->data;
440
441 twl6030_irq->irq_domain =
442 irq_domain_add_linear(node, nr_irqs,
443 &twl6030_irq_domain_ops, twl6030_irq);
444 if (!twl6030_irq->irq_domain) {
445 dev_err(dev, "Can't add irq_domain\n");
446 return -ENOMEM;
447 }
448
449 dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);
450
451 /* install an irq handler to demultiplex the TWL6030 interrupt */
452 status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
453 IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
454 if (status < 0) {
455 dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
456 goto fail_irq;
457 }
458
459 twl6030_irq->twl_irq = irq_num;
460 register_pm_notifier(&twl6030_irq->pm_nb);
461 return 0;
462
463 fail_irq:
464 irq_domain_remove(twl6030_irq->irq_domain);
465 return status;
466 }
467
468 int twl6030_exit_irq(void)
469 {
470 if (twl6030_irq && twl6030_irq->twl_irq) {
471 unregister_pm_notifier(&twl6030_irq->pm_nb);
472 free_irq(twl6030_irq->twl_irq, NULL);
473 /*
474 * TODO: IRQ domain and allocated nested IRQ descriptors
475 * should be freed somehow here. Now It can't be done, because
476 * child devices will not be deleted during removing of
477 * TWL Core driver and they will still contain allocated
478 * virt IRQs in their Resources tables.
479 * The same prevents us from using devm_request_threaded_irq()
480 * in this module.
481 */
482 }
483 return 0;
484 }
485
Linux with added FPC-III support