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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / mmc / host / jz4740_mmc.c
blobde2139cf344477bbe8922448a963c9e1094dd882
1 /*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SD/MMC controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #include <linux/mmc/host.h>
17 #include <linux/mmc/slot-gpio.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
25 #include <linux/scatterlist.h>
26 #include <linux/clk.h>
27
28 #include <linux/bitops.h>
29 #include <linux/gpio.h>
30 #include <asm/mach-jz4740/gpio.h>
31 #include <asm/cacheflush.h>
32 #include <linux/dma-mapping.h>
33
34 #include <asm/mach-jz4740/jz4740_mmc.h>
35
36 #define JZ_REG_MMC_STRPCL 0x00
37 #define JZ_REG_MMC_STATUS 0x04
38 #define JZ_REG_MMC_CLKRT 0x08
39 #define JZ_REG_MMC_CMDAT 0x0C
40 #define JZ_REG_MMC_RESTO 0x10
41 #define JZ_REG_MMC_RDTO 0x14
42 #define JZ_REG_MMC_BLKLEN 0x18
43 #define JZ_REG_MMC_NOB 0x1C
44 #define JZ_REG_MMC_SNOB 0x20
45 #define JZ_REG_MMC_IMASK 0x24
46 #define JZ_REG_MMC_IREG 0x28
47 #define JZ_REG_MMC_CMD 0x2C
48 #define JZ_REG_MMC_ARG 0x30
49 #define JZ_REG_MMC_RESP_FIFO 0x34
50 #define JZ_REG_MMC_RXFIFO 0x38
51 #define JZ_REG_MMC_TXFIFO 0x3C
52
53 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
54 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
55 #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
56 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
57 #define JZ_MMC_STRPCL_RESET BIT(3)
58 #define JZ_MMC_STRPCL_START_OP BIT(2)
59 #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
60 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
61 #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
62
63
64 #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
65 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
66 #define JZ_MMC_STATUS_PRG_DONE BIT(13)
67 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
68 #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
69 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
70 #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
71 #define JZ_MMC_STATUS_CLK_EN BIT(8)
72 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
73 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
74 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
75 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
76 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
77 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
78 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
79 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
80
81 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
82 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
83
84
85 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
86 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
87 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
88 #define JZ_MMC_CMDAT_INIT BIT(7)
89 #define JZ_MMC_CMDAT_BUSY BIT(6)
90 #define JZ_MMC_CMDAT_STREAM BIT(5)
91 #define JZ_MMC_CMDAT_WRITE BIT(4)
92 #define JZ_MMC_CMDAT_DATA_EN BIT(3)
93 #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
94 #define JZ_MMC_CMDAT_RSP_R1 1
95 #define JZ_MMC_CMDAT_RSP_R2 2
96 #define JZ_MMC_CMDAT_RSP_R3 3
97
98 #define JZ_MMC_IRQ_SDIO BIT(7)
99 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
100 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
101 #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
102 #define JZ_MMC_IRQ_PRG_DONE BIT(1)
103 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
104
105
106 #define JZ_MMC_CLK_RATE 24000000
107
108 enum jz4740_mmc_state {
109 JZ4740_MMC_STATE_READ_RESPONSE,
110 JZ4740_MMC_STATE_TRANSFER_DATA,
111 JZ4740_MMC_STATE_SEND_STOP,
112 JZ4740_MMC_STATE_DONE,
113 };
114
115 struct jz4740_mmc_host {
116 struct mmc_host *mmc;
117 struct platform_device *pdev;
118 struct jz4740_mmc_platform_data *pdata;
119 struct clk *clk;
120
121 int irq;
122 int card_detect_irq;
123
124 void __iomem *base;
125 struct mmc_request *req;
126 struct mmc_command *cmd;
127
128 unsigned long waiting;
129
130 uint32_t cmdat;
131
132 uint16_t irq_mask;
133
134 spinlock_t lock;
135
136 struct timer_list timeout_timer;
137 struct sg_mapping_iter miter;
138 enum jz4740_mmc_state state;
139 };
140
141 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
142 unsigned int irq, bool enabled)
143 {
144 unsigned long flags;
145
146 spin_lock_irqsave(&host->lock, flags);
147 if (enabled)
148 host->irq_mask &= ~irq;
149 else
150 host->irq_mask |= irq;
151 spin_unlock_irqrestore(&host->lock, flags);
152
153 writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
154 }
155
156 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
157 bool start_transfer)
158 {
159 uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
160
161 if (start_transfer)
162 val |= JZ_MMC_STRPCL_START_OP;
163
164 writew(val, host->base + JZ_REG_MMC_STRPCL);
165 }
166
167 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
168 {
169 uint32_t status;
170 unsigned int timeout = 1000;
171
172 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
173 do {
174 status = readl(host->base + JZ_REG_MMC_STATUS);
175 } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
176 }
177
178 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
179 {
180 uint32_t status;
181 unsigned int timeout = 1000;
182
183 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
184 udelay(10);
185 do {
186 status = readl(host->base + JZ_REG_MMC_STATUS);
187 } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
188 }
189
190 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
191 {
192 struct mmc_request *req;
193
194 req = host->req;
195 host->req = NULL;
196
197 mmc_request_done(host->mmc, req);
198 }
199
200 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
201 unsigned int irq)
202 {
203 unsigned int timeout = 0x800;
204 uint16_t status;
205
206 do {
207 status = readw(host->base + JZ_REG_MMC_IREG);
208 } while (!(status & irq) && --timeout);
209
210 if (timeout == 0) {
211 set_bit(0, &host->waiting);
212 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
213 jz4740_mmc_set_irq_enabled(host, irq, true);
214 return true;
215 }
216
217 return false;
218 }
219
220 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
221 struct mmc_data *data)
222 {
223 int status;
224
225 status = readl(host->base + JZ_REG_MMC_STATUS);
226 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
227 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
228 host->req->cmd->error = -ETIMEDOUT;
229 data->error = -ETIMEDOUT;
230 } else {
231 host->req->cmd->error = -EIO;
232 data->error = -EIO;
233 }
234 } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
235 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
236 host->req->cmd->error = -ETIMEDOUT;
237 data->error = -ETIMEDOUT;
238 } else {
239 host->req->cmd->error = -EIO;
240 data->error = -EIO;
241 }
242 }
243 }
244
245 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
246 struct mmc_data *data)
247 {
248 struct sg_mapping_iter *miter = &host->miter;
249 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
250 uint32_t *buf;
251 bool timeout;
252 size_t i, j;
253
254 while (sg_miter_next(miter)) {
255 buf = miter->addr;
256 i = miter->length / 4;
257 j = i / 8;
258 i = i & 0x7;
259 while (j) {
260 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
261 if (unlikely(timeout))
262 goto poll_timeout;
263
264 writel(buf[0], fifo_addr);
265 writel(buf[1], fifo_addr);
266 writel(buf[2], fifo_addr);
267 writel(buf[3], fifo_addr);
268 writel(buf[4], fifo_addr);
269 writel(buf[5], fifo_addr);
270 writel(buf[6], fifo_addr);
271 writel(buf[7], fifo_addr);
272 buf += 8;
273 --j;
274 }
275 if (unlikely(i)) {
276 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
277 if (unlikely(timeout))
278 goto poll_timeout;
279
280 while (i) {
281 writel(*buf, fifo_addr);
282 ++buf;
283 --i;
284 }
285 }
286 data->bytes_xfered += miter->length;
287 }
288 sg_miter_stop(miter);
289
290 return false;
291
292 poll_timeout:
293 miter->consumed = (void *)buf - miter->addr;
294 data->bytes_xfered += miter->consumed;
295 sg_miter_stop(miter);
296
297 return true;
298 }
299
300 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
301 struct mmc_data *data)
302 {
303 struct sg_mapping_iter *miter = &host->miter;
304 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
305 uint32_t *buf;
306 uint32_t d;
307 uint16_t status;
308 size_t i, j;
309 unsigned int timeout;
310
311 while (sg_miter_next(miter)) {
312 buf = miter->addr;
313 i = miter->length;
314 j = i / 32;
315 i = i & 0x1f;
316 while (j) {
317 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
318 if (unlikely(timeout))
319 goto poll_timeout;
320
321 buf[0] = readl(fifo_addr);
322 buf[1] = readl(fifo_addr);
323 buf[2] = readl(fifo_addr);
324 buf[3] = readl(fifo_addr);
325 buf[4] = readl(fifo_addr);
326 buf[5] = readl(fifo_addr);
327 buf[6] = readl(fifo_addr);
328 buf[7] = readl(fifo_addr);
329
330 buf += 8;
331 --j;
332 }
333
334 if (unlikely(i)) {
335 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
336 if (unlikely(timeout))
337 goto poll_timeout;
338
339 while (i >= 4) {
340 *buf++ = readl(fifo_addr);
341 i -= 4;
342 }
343 if (unlikely(i > 0)) {
344 d = readl(fifo_addr);
345 memcpy(buf, &d, i);
346 }
347 }
348 data->bytes_xfered += miter->length;
349
350 /* This can go away once MIPS implements
351 * flush_kernel_dcache_page */
352 flush_dcache_page(miter->page);
353 }
354 sg_miter_stop(miter);
355
356 /* For whatever reason there is sometime one word more in the fifo then
357 * requested */
358 timeout = 1000;
359 status = readl(host->base + JZ_REG_MMC_STATUS);
360 while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
361 d = readl(fifo_addr);
362 status = readl(host->base + JZ_REG_MMC_STATUS);
363 }
364
365 return false;
366
367 poll_timeout:
368 miter->consumed = (void *)buf - miter->addr;
369 data->bytes_xfered += miter->consumed;
370 sg_miter_stop(miter);
371
372 return true;
373 }
374
375 static void jz4740_mmc_timeout(unsigned long data)
376 {
377 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
378
379 if (!test_and_clear_bit(0, &host->waiting))
380 return;
381
382 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
383
384 host->req->cmd->error = -ETIMEDOUT;
385 jz4740_mmc_request_done(host);
386 }
387
388 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
389 struct mmc_command *cmd)
390 {
391 int i;
392 uint16_t tmp;
393 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
394
395 if (cmd->flags & MMC_RSP_136) {
396 tmp = readw(fifo_addr);
397 for (i = 0; i < 4; ++i) {
398 cmd->resp[i] = tmp << 24;
399 tmp = readw(fifo_addr);
400 cmd->resp[i] |= tmp << 8;
401 tmp = readw(fifo_addr);
402 cmd->resp[i] |= tmp >> 8;
403 }
404 } else {
405 cmd->resp[0] = readw(fifo_addr) << 24;
406 cmd->resp[0] |= readw(fifo_addr) << 8;
407 cmd->resp[0] |= readw(fifo_addr) & 0xff;
408 }
409 }
410
411 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
412 struct mmc_command *cmd)
413 {
414 uint32_t cmdat = host->cmdat;
415
416 host->cmdat &= ~JZ_MMC_CMDAT_INIT;
417 jz4740_mmc_clock_disable(host);
418
419 host->cmd = cmd;
420
421 if (cmd->flags & MMC_RSP_BUSY)
422 cmdat |= JZ_MMC_CMDAT_BUSY;
423
424 switch (mmc_resp_type(cmd)) {
425 case MMC_RSP_R1B:
426 case MMC_RSP_R1:
427 cmdat |= JZ_MMC_CMDAT_RSP_R1;
428 break;
429 case MMC_RSP_R2:
430 cmdat |= JZ_MMC_CMDAT_RSP_R2;
431 break;
432 case MMC_RSP_R3:
433 cmdat |= JZ_MMC_CMDAT_RSP_R3;
434 break;
435 default:
436 break;
437 }
438
439 if (cmd->data) {
440 cmdat |= JZ_MMC_CMDAT_DATA_EN;
441 if (cmd->data->flags & MMC_DATA_WRITE)
442 cmdat |= JZ_MMC_CMDAT_WRITE;
443 if (cmd->data->flags & MMC_DATA_STREAM)
444 cmdat |= JZ_MMC_CMDAT_STREAM;
445
446 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
447 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
448 }
449
450 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
451 writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
452 writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
453
454 jz4740_mmc_clock_enable(host, 1);
455 }
456
457 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
458 {
459 struct mmc_command *cmd = host->req->cmd;
460 struct mmc_data *data = cmd->data;
461 int direction;
462
463 if (data->flags & MMC_DATA_READ)
464 direction = SG_MITER_TO_SG;
465 else
466 direction = SG_MITER_FROM_SG;
467
468 sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
469 }
470
471
472 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
473 {
474 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
475 struct mmc_command *cmd = host->req->cmd;
476 struct mmc_request *req = host->req;
477 bool timeout = false;
478
479 if (cmd->error)
480 host->state = JZ4740_MMC_STATE_DONE;
481
482 switch (host->state) {
483 case JZ4740_MMC_STATE_READ_RESPONSE:
484 if (cmd->flags & MMC_RSP_PRESENT)
485 jz4740_mmc_read_response(host, cmd);
486
487 if (!cmd->data)
488 break;
489
490 jz_mmc_prepare_data_transfer(host);
491
492 case JZ4740_MMC_STATE_TRANSFER_DATA:
493 if (cmd->data->flags & MMC_DATA_READ)
494 timeout = jz4740_mmc_read_data(host, cmd->data);
495 else
496 timeout = jz4740_mmc_write_data(host, cmd->data);
497
498 if (unlikely(timeout)) {
499 host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
500 break;
501 }
502
503 jz4740_mmc_transfer_check_state(host, cmd->data);
504
505 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
506 if (unlikely(timeout)) {
507 host->state = JZ4740_MMC_STATE_SEND_STOP;
508 break;
509 }
510 writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
511
512 case JZ4740_MMC_STATE_SEND_STOP:
513 if (!req->stop)
514 break;
515
516 jz4740_mmc_send_command(host, req->stop);
517
518 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE);
519 if (timeout) {
520 host->state = JZ4740_MMC_STATE_DONE;
521 break;
522 }
523 case JZ4740_MMC_STATE_DONE:
524 break;
525 }
526
527 if (!timeout)
528 jz4740_mmc_request_done(host);
529
530 return IRQ_HANDLED;
531 }
532
533 static irqreturn_t jz_mmc_irq(int irq, void *devid)
534 {
535 struct jz4740_mmc_host *host = devid;
536 struct mmc_command *cmd = host->cmd;
537 uint16_t irq_reg, status, tmp;
538
539 irq_reg = readw(host->base + JZ_REG_MMC_IREG);
540
541 tmp = irq_reg;
542 irq_reg &= ~host->irq_mask;
543
544 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
545 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
546
547 if (tmp != irq_reg)
548 writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
549
550 if (irq_reg & JZ_MMC_IRQ_SDIO) {
551 writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
552 mmc_signal_sdio_irq(host->mmc);
553 irq_reg &= ~JZ_MMC_IRQ_SDIO;
554 }
555
556 if (host->req && cmd && irq_reg) {
557 if (test_and_clear_bit(0, &host->waiting)) {
558 del_timer(&host->timeout_timer);
559
560 status = readl(host->base + JZ_REG_MMC_STATUS);
561
562 if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
563 cmd->error = -ETIMEDOUT;
564 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
565 cmd->error = -EIO;
566 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
567 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
568 if (cmd->data)
569 cmd->data->error = -EIO;
570 cmd->error = -EIO;
571 }
572
573 jz4740_mmc_set_irq_enabled(host, irq_reg, false);
574 writew(irq_reg, host->base + JZ_REG_MMC_IREG);
575
576 return IRQ_WAKE_THREAD;
577 }
578 }
579
580 return IRQ_HANDLED;
581 }
582
583 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
584 {
585 int div = 0;
586 int real_rate;
587
588 jz4740_mmc_clock_disable(host);
589 clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
590
591 real_rate = clk_get_rate(host->clk);
592
593 while (real_rate > rate && div < 7) {
594 ++div;
595 real_rate >>= 1;
596 }
597
598 writew(div, host->base + JZ_REG_MMC_CLKRT);
599 return real_rate;
600 }
601
602 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
603 {
604 struct jz4740_mmc_host *host = mmc_priv(mmc);
605
606 host->req = req;
607
608 writew(0xffff, host->base + JZ_REG_MMC_IREG);
609
610 writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
611 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
612
613 host->state = JZ4740_MMC_STATE_READ_RESPONSE;
614 set_bit(0, &host->waiting);
615 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
616 jz4740_mmc_send_command(host, req->cmd);
617 }
618
619 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
620 {
621 struct jz4740_mmc_host *host = mmc_priv(mmc);
622 if (ios->clock)
623 jz4740_mmc_set_clock_rate(host, ios->clock);
624
625 switch (ios->power_mode) {
626 case MMC_POWER_UP:
627 jz4740_mmc_reset(host);
628 if (gpio_is_valid(host->pdata->gpio_power))
629 gpio_set_value(host->pdata->gpio_power,
630 !host->pdata->power_active_low);
631 host->cmdat |= JZ_MMC_CMDAT_INIT;
632 clk_prepare_enable(host->clk);
633 break;
634 case MMC_POWER_ON:
635 break;
636 default:
637 if (gpio_is_valid(host->pdata->gpio_power))
638 gpio_set_value(host->pdata->gpio_power,
639 host->pdata->power_active_low);
640 clk_disable_unprepare(host->clk);
641 break;
642 }
643
644 switch (ios->bus_width) {
645 case MMC_BUS_WIDTH_1:
646 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
647 break;
648 case MMC_BUS_WIDTH_4:
649 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
650 break;
651 default:
652 break;
653 }
654 }
655
656 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
657 {
658 struct jz4740_mmc_host *host = mmc_priv(mmc);
659 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
660 }
661
662 static const struct mmc_host_ops jz4740_mmc_ops = {
663 .request = jz4740_mmc_request,
664 .set_ios = jz4740_mmc_set_ios,
665 .get_ro = mmc_gpio_get_ro,
666 .get_cd = mmc_gpio_get_cd,
667 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
668 };
669
670 static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
671 JZ_GPIO_BULK_PIN(MSC_CMD),
672 JZ_GPIO_BULK_PIN(MSC_CLK),
673 JZ_GPIO_BULK_PIN(MSC_DATA0),
674 JZ_GPIO_BULK_PIN(MSC_DATA1),
675 JZ_GPIO_BULK_PIN(MSC_DATA2),
676 JZ_GPIO_BULK_PIN(MSC_DATA3),
677 };
678
679 static int jz4740_mmc_request_gpio(struct device *dev, int gpio,
680 const char *name, bool output, int value)
681 {
682 int ret;
683
684 if (!gpio_is_valid(gpio))
685 return 0;
686
687 ret = gpio_request(gpio, name);
688 if (ret) {
689 dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
690 return ret;
691 }
692
693 if (output)
694 gpio_direction_output(gpio, value);
695 else
696 gpio_direction_input(gpio);
697
698 return 0;
699 }
700
701 static int jz4740_mmc_request_gpios(struct mmc_host *mmc,
702 struct platform_device *pdev)
703 {
704 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
705 int ret = 0;
706
707 if (!pdata)
708 return 0;
709
710 if (!pdata->card_detect_active_low)
711 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
712 if (!pdata->read_only_active_low)
713 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
714
715 if (gpio_is_valid(pdata->gpio_card_detect)) {
716 ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0);
717 if (ret)
718 return ret;
719 }
720
721 if (gpio_is_valid(pdata->gpio_read_only)) {
722 ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only);
723 if (ret)
724 return ret;
725 }
726
727 return jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
728 "MMC read only", true, pdata->power_active_low);
729 }
730
731 static void jz4740_mmc_free_gpios(struct platform_device *pdev)
732 {
733 struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
734
735 if (!pdata)
736 return;
737
738 if (gpio_is_valid(pdata->gpio_power))
739 gpio_free(pdata->gpio_power);
740 }
741
742 static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
743 {
744 size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
745 if (host->pdata && host->pdata->data_1bit)
746 num_pins -= 3;
747
748 return num_pins;
749 }
750
751 static int jz4740_mmc_probe(struct platform_device* pdev)
752 {
753 int ret;
754 struct mmc_host *mmc;
755 struct jz4740_mmc_host *host;
756 struct jz4740_mmc_platform_data *pdata;
757 struct resource *res;
758
759 pdata = pdev->dev.platform_data;
760
761 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
762 if (!mmc) {
763 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
764 return -ENOMEM;
765 }
766
767 host = mmc_priv(mmc);
768 host->pdata = pdata;
769
770 host->irq = platform_get_irq(pdev, 0);
771 if (host->irq < 0) {
772 ret = host->irq;
773 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
774 goto err_free_host;
775 }
776
777 host->clk = devm_clk_get(&pdev->dev, "mmc");
778 if (IS_ERR(host->clk)) {
779 ret = PTR_ERR(host->clk);
780 dev_err(&pdev->dev, "Failed to get mmc clock\n");
781 goto err_free_host;
782 }
783
784 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
785 host->base = devm_ioremap_resource(&pdev->dev, res);
786 if (IS_ERR(host->base)) {
787 ret = PTR_ERR(host->base);
788 goto err_free_host;
789 }
790
791 ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
792 if (ret) {
793 dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
794 goto err_free_host;
795 }
796
797 ret = jz4740_mmc_request_gpios(mmc, pdev);
798 if (ret)
799 goto err_gpio_bulk_free;
800
801 mmc->ops = &jz4740_mmc_ops;
802 mmc->f_min = JZ_MMC_CLK_RATE / 128;
803 mmc->f_max = JZ_MMC_CLK_RATE;
804 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
805 mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
806 mmc->caps |= MMC_CAP_SDIO_IRQ;
807
808 mmc->max_blk_size = (1 << 10) - 1;
809 mmc->max_blk_count = (1 << 15) - 1;
810 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
811
812 mmc->max_segs = 128;
813 mmc->max_seg_size = mmc->max_req_size;
814
815 host->mmc = mmc;
816 host->pdev = pdev;
817 spin_lock_init(&host->lock);
818 host->irq_mask = 0xffff;
819
820 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
821 dev_name(&pdev->dev), host);
822 if (ret) {
823 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
824 goto err_free_gpios;
825 }
826
827 jz4740_mmc_reset(host);
828 jz4740_mmc_clock_disable(host);
829 setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
830 (unsigned long)host);
831 /* It is not important when it times out, it just needs to timeout. */
832 set_timer_slack(&host->timeout_timer, HZ);
833
834 platform_set_drvdata(pdev, host);
835 ret = mmc_add_host(mmc);
836
837 if (ret) {
838 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
839 goto err_free_irq;
840 }
841 dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
842
843 return 0;
844
845 err_free_irq:
846 free_irq(host->irq, host);
847 err_free_gpios:
848 jz4740_mmc_free_gpios(pdev);
849 err_gpio_bulk_free:
850 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
851 err_free_host:
852 mmc_free_host(mmc);
853
854 return ret;
855 }
856
857 static int jz4740_mmc_remove(struct platform_device *pdev)
858 {
859 struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
860
861 del_timer_sync(&host->timeout_timer);
862 jz4740_mmc_set_irq_enabled(host, 0xff, false);
863 jz4740_mmc_reset(host);
864
865 mmc_remove_host(host->mmc);
866
867 free_irq(host->irq, host);
868
869 jz4740_mmc_free_gpios(pdev);
870 jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
871
872 mmc_free_host(host->mmc);
873
874 return 0;
875 }
876
877 #ifdef CONFIG_PM_SLEEP
878
879 static int jz4740_mmc_suspend(struct device *dev)
880 {
881 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
882
883 jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
884
885 return 0;
886 }
887
888 static int jz4740_mmc_resume(struct device *dev)
889 {
890 struct jz4740_mmc_host *host = dev_get_drvdata(dev);
891
892 jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
893
894 return 0;
895 }
896
897 static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
898 jz4740_mmc_resume);
899 #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
900 #else
901 #define JZ4740_MMC_PM_OPS NULL
902 #endif
903
904 static struct platform_driver jz4740_mmc_driver = {
905 .probe = jz4740_mmc_probe,
906 .remove = jz4740_mmc_remove,
907 .driver = {
908 .name = "jz4740-mmc",
909 .owner = THIS_MODULE,
910 .pm = JZ4740_MMC_PM_OPS,
911 },
912 };
913
914 module_platform_driver(jz4740_mmc_driver);
915
916 MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
917 MODULE_LICENSE("GPL");
918 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
Linux with added FPC-III support