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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / mmc / host / omap.c
blob98b6b6ef7e5c9d737a749e9a3ddf631f5d92c1c0
1 /*
2 * linux/drivers/mmc/host/omap.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/timer.h>
25 #include <linux/of.h>
26 #include <linux/omap-dma.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/card.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
31 #include <linux/slab.h>
32 #include <linux/platform_data/mmc-omap.h>
33
34
35 #define OMAP_MMC_REG_CMD 0x00
36 #define OMAP_MMC_REG_ARGL 0x01
37 #define OMAP_MMC_REG_ARGH 0x02
38 #define OMAP_MMC_REG_CON 0x03
39 #define OMAP_MMC_REG_STAT 0x04
40 #define OMAP_MMC_REG_IE 0x05
41 #define OMAP_MMC_REG_CTO 0x06
42 #define OMAP_MMC_REG_DTO 0x07
43 #define OMAP_MMC_REG_DATA 0x08
44 #define OMAP_MMC_REG_BLEN 0x09
45 #define OMAP_MMC_REG_NBLK 0x0a
46 #define OMAP_MMC_REG_BUF 0x0b
47 #define OMAP_MMC_REG_SDIO 0x0d
48 #define OMAP_MMC_REG_REV 0x0f
49 #define OMAP_MMC_REG_RSP0 0x10
50 #define OMAP_MMC_REG_RSP1 0x11
51 #define OMAP_MMC_REG_RSP2 0x12
52 #define OMAP_MMC_REG_RSP3 0x13
53 #define OMAP_MMC_REG_RSP4 0x14
54 #define OMAP_MMC_REG_RSP5 0x15
55 #define OMAP_MMC_REG_RSP6 0x16
56 #define OMAP_MMC_REG_RSP7 0x17
57 #define OMAP_MMC_REG_IOSR 0x18
58 #define OMAP_MMC_REG_SYSC 0x19
59 #define OMAP_MMC_REG_SYSS 0x1a
60
61 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
62 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
63 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
64 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
65 #define OMAP_MMC_STAT_A_FULL (1 << 10)
66 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
67 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
68 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
69 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
70 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
71 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
72 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
73 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
74
75 #define mmc_omap7xx() (host->features & MMC_OMAP7XX)
76 #define mmc_omap15xx() (host->features & MMC_OMAP15XX)
77 #define mmc_omap16xx() (host->features & MMC_OMAP16XX)
78 #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
79 #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
80 #define mmc_omap2() (!mmc_omap1())
81
82 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
83 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
84 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
85
86 /*
87 * Command types
88 */
89 #define OMAP_MMC_CMDTYPE_BC 0
90 #define OMAP_MMC_CMDTYPE_BCR 1
91 #define OMAP_MMC_CMDTYPE_AC 2
92 #define OMAP_MMC_CMDTYPE_ADTC 3
93
94 #define DRIVER_NAME "mmci-omap"
95
96 /* Specifies how often in millisecs to poll for card status changes
97 * when the cover switch is open */
98 #define OMAP_MMC_COVER_POLL_DELAY 500
99
100 struct mmc_omap_host;
101
102 struct mmc_omap_slot {
103 int id;
104 unsigned int vdd;
105 u16 saved_con;
106 u16 bus_mode;
107 unsigned int fclk_freq;
108
109 struct tasklet_struct cover_tasklet;
110 struct timer_list cover_timer;
111 unsigned cover_open;
112
113 struct mmc_request *mrq;
114 struct mmc_omap_host *host;
115 struct mmc_host *mmc;
116 struct omap_mmc_slot_data *pdata;
117 };
118
119 struct mmc_omap_host {
120 int initialized;
121 struct mmc_request * mrq;
122 struct mmc_command * cmd;
123 struct mmc_data * data;
124 struct mmc_host * mmc;
125 struct device * dev;
126 unsigned char id; /* 16xx chips have 2 MMC blocks */
127 struct clk * iclk;
128 struct clk * fclk;
129 struct dma_chan *dma_rx;
130 u32 dma_rx_burst;
131 struct dma_chan *dma_tx;
132 u32 dma_tx_burst;
133 struct resource *mem_res;
134 void __iomem *virt_base;
135 unsigned int phys_base;
136 int irq;
137 unsigned char bus_mode;
138 unsigned int reg_shift;
139
140 struct work_struct cmd_abort_work;
141 unsigned abort:1;
142 struct timer_list cmd_abort_timer;
143
144 struct work_struct slot_release_work;
145 struct mmc_omap_slot *next_slot;
146 struct work_struct send_stop_work;
147 struct mmc_data *stop_data;
148
149 unsigned int sg_len;
150 int sg_idx;
151 u16 * buffer;
152 u32 buffer_bytes_left;
153 u32 total_bytes_left;
154
155 unsigned features;
156 unsigned use_dma:1;
157 unsigned brs_received:1, dma_done:1;
158 unsigned dma_in_use:1;
159 spinlock_t dma_lock;
160
161 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
162 struct mmc_omap_slot *current_slot;
163 spinlock_t slot_lock;
164 wait_queue_head_t slot_wq;
165 int nr_slots;
166
167 struct timer_list clk_timer;
168 spinlock_t clk_lock; /* for changing enabled state */
169 unsigned int fclk_enabled:1;
170 struct workqueue_struct *mmc_omap_wq;
171
172 struct omap_mmc_platform_data *pdata;
173 };
174
175
176 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
177 {
178 unsigned long tick_ns;
179
180 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
181 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
182 ndelay(8 * tick_ns);
183 }
184 }
185
186 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
187 {
188 unsigned long flags;
189
190 spin_lock_irqsave(&host->clk_lock, flags);
191 if (host->fclk_enabled != enable) {
192 host->fclk_enabled = enable;
193 if (enable)
194 clk_enable(host->fclk);
195 else
196 clk_disable(host->fclk);
197 }
198 spin_unlock_irqrestore(&host->clk_lock, flags);
199 }
200
201 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
202 {
203 struct mmc_omap_host *host = slot->host;
204 unsigned long flags;
205
206 if (claimed)
207 goto no_claim;
208 spin_lock_irqsave(&host->slot_lock, flags);
209 while (host->mmc != NULL) {
210 spin_unlock_irqrestore(&host->slot_lock, flags);
211 wait_event(host->slot_wq, host->mmc == NULL);
212 spin_lock_irqsave(&host->slot_lock, flags);
213 }
214 host->mmc = slot->mmc;
215 spin_unlock_irqrestore(&host->slot_lock, flags);
216 no_claim:
217 del_timer(&host->clk_timer);
218 if (host->current_slot != slot || !claimed)
219 mmc_omap_fclk_offdelay(host->current_slot);
220
221 if (host->current_slot != slot) {
222 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
223 if (host->pdata->switch_slot != NULL)
224 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
225 host->current_slot = slot;
226 }
227
228 if (claimed) {
229 mmc_omap_fclk_enable(host, 1);
230
231 /* Doing the dummy read here seems to work around some bug
232 * at least in OMAP24xx silicon where the command would not
233 * start after writing the CMD register. Sigh. */
234 OMAP_MMC_READ(host, CON);
235
236 OMAP_MMC_WRITE(host, CON, slot->saved_con);
237 } else
238 mmc_omap_fclk_enable(host, 0);
239 }
240
241 static void mmc_omap_start_request(struct mmc_omap_host *host,
242 struct mmc_request *req);
243
244 static void mmc_omap_slot_release_work(struct work_struct *work)
245 {
246 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
247 slot_release_work);
248 struct mmc_omap_slot *next_slot = host->next_slot;
249 struct mmc_request *rq;
250
251 host->next_slot = NULL;
252 mmc_omap_select_slot(next_slot, 1);
253
254 rq = next_slot->mrq;
255 next_slot->mrq = NULL;
256 mmc_omap_start_request(host, rq);
257 }
258
259 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
260 {
261 struct mmc_omap_host *host = slot->host;
262 unsigned long flags;
263 int i;
264
265 BUG_ON(slot == NULL || host->mmc == NULL);
266
267 if (clk_enabled)
268 /* Keeps clock running for at least 8 cycles on valid freq */
269 mod_timer(&host->clk_timer, jiffies + HZ/10);
270 else {
271 del_timer(&host->clk_timer);
272 mmc_omap_fclk_offdelay(slot);
273 mmc_omap_fclk_enable(host, 0);
274 }
275
276 spin_lock_irqsave(&host->slot_lock, flags);
277 /* Check for any pending requests */
278 for (i = 0; i < host->nr_slots; i++) {
279 struct mmc_omap_slot *new_slot;
280
281 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
282 continue;
283
284 BUG_ON(host->next_slot != NULL);
285 new_slot = host->slots[i];
286 /* The current slot should not have a request in queue */
287 BUG_ON(new_slot == host->current_slot);
288
289 host->next_slot = new_slot;
290 host->mmc = new_slot->mmc;
291 spin_unlock_irqrestore(&host->slot_lock, flags);
292 queue_work(host->mmc_omap_wq, &host->slot_release_work);
293 return;
294 }
295
296 host->mmc = NULL;
297 wake_up(&host->slot_wq);
298 spin_unlock_irqrestore(&host->slot_lock, flags);
299 }
300
301 static inline
302 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
303 {
304 if (slot->pdata->get_cover_state)
305 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
306 slot->id);
307 return 0;
308 }
309
310 static ssize_t
311 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
312 char *buf)
313 {
314 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
315 struct mmc_omap_slot *slot = mmc_priv(mmc);
316
317 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
318 "closed");
319 }
320
321 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
322
323 static ssize_t
324 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
325 char *buf)
326 {
327 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
328 struct mmc_omap_slot *slot = mmc_priv(mmc);
329
330 return sprintf(buf, "%s\n", slot->pdata->name);
331 }
332
333 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
334
335 static void
336 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
337 {
338 u32 cmdreg;
339 u32 resptype;
340 u32 cmdtype;
341
342 host->cmd = cmd;
343
344 resptype = 0;
345 cmdtype = 0;
346
347 /* Our hardware needs to know exact type */
348 switch (mmc_resp_type(cmd)) {
349 case MMC_RSP_NONE:
350 break;
351 case MMC_RSP_R1:
352 case MMC_RSP_R1B:
353 /* resp 1, 1b, 6, 7 */
354 resptype = 1;
355 break;
356 case MMC_RSP_R2:
357 resptype = 2;
358 break;
359 case MMC_RSP_R3:
360 resptype = 3;
361 break;
362 default:
363 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
364 break;
365 }
366
367 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
368 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
369 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
370 cmdtype = OMAP_MMC_CMDTYPE_BC;
371 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
372 cmdtype = OMAP_MMC_CMDTYPE_BCR;
373 } else {
374 cmdtype = OMAP_MMC_CMDTYPE_AC;
375 }
376
377 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
378
379 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
380 cmdreg |= 1 << 6;
381
382 if (cmd->flags & MMC_RSP_BUSY)
383 cmdreg |= 1 << 11;
384
385 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
386 cmdreg |= 1 << 15;
387
388 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
389
390 OMAP_MMC_WRITE(host, CTO, 200);
391 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
392 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
393 OMAP_MMC_WRITE(host, IE,
394 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
395 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
396 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
397 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
398 OMAP_MMC_STAT_END_OF_DATA);
399 OMAP_MMC_WRITE(host, CMD, cmdreg);
400 }
401
402 static void
403 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
404 int abort)
405 {
406 enum dma_data_direction dma_data_dir;
407 struct device *dev = mmc_dev(host->mmc);
408 struct dma_chan *c;
409
410 if (data->flags & MMC_DATA_WRITE) {
411 dma_data_dir = DMA_TO_DEVICE;
412 c = host->dma_tx;
413 } else {
414 dma_data_dir = DMA_FROM_DEVICE;
415 c = host->dma_rx;
416 }
417 if (c) {
418 if (data->error) {
419 dmaengine_terminate_all(c);
420 /* Claim nothing transferred on error... */
421 data->bytes_xfered = 0;
422 }
423 dev = c->device->dev;
424 }
425 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
426 }
427
428 static void mmc_omap_send_stop_work(struct work_struct *work)
429 {
430 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
431 send_stop_work);
432 struct mmc_omap_slot *slot = host->current_slot;
433 struct mmc_data *data = host->stop_data;
434 unsigned long tick_ns;
435
436 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
437 ndelay(8*tick_ns);
438
439 mmc_omap_start_command(host, data->stop);
440 }
441
442 static void
443 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
444 {
445 if (host->dma_in_use)
446 mmc_omap_release_dma(host, data, data->error);
447
448 host->data = NULL;
449 host->sg_len = 0;
450
451 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
452 * dozens of requests until the card finishes writing data.
453 * It'd be cheaper to just wait till an EOFB interrupt arrives...
454 */
455
456 if (!data->stop) {
457 struct mmc_host *mmc;
458
459 host->mrq = NULL;
460 mmc = host->mmc;
461 mmc_omap_release_slot(host->current_slot, 1);
462 mmc_request_done(mmc, data->mrq);
463 return;
464 }
465
466 host->stop_data = data;
467 queue_work(host->mmc_omap_wq, &host->send_stop_work);
468 }
469
470 static void
471 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
472 {
473 struct mmc_omap_slot *slot = host->current_slot;
474 unsigned int restarts, passes, timeout;
475 u16 stat = 0;
476
477 /* Sending abort takes 80 clocks. Have some extra and round up */
478 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
479 restarts = 0;
480 while (restarts < maxloops) {
481 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
482 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
483
484 passes = 0;
485 while (passes < timeout) {
486 stat = OMAP_MMC_READ(host, STAT);
487 if (stat & OMAP_MMC_STAT_END_OF_CMD)
488 goto out;
489 udelay(1);
490 passes++;
491 }
492
493 restarts++;
494 }
495 out:
496 OMAP_MMC_WRITE(host, STAT, stat);
497 }
498
499 static void
500 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
501 {
502 if (host->dma_in_use)
503 mmc_omap_release_dma(host, data, 1);
504
505 host->data = NULL;
506 host->sg_len = 0;
507
508 mmc_omap_send_abort(host, 10000);
509 }
510
511 static void
512 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
513 {
514 unsigned long flags;
515 int done;
516
517 if (!host->dma_in_use) {
518 mmc_omap_xfer_done(host, data);
519 return;
520 }
521 done = 0;
522 spin_lock_irqsave(&host->dma_lock, flags);
523 if (host->dma_done)
524 done = 1;
525 else
526 host->brs_received = 1;
527 spin_unlock_irqrestore(&host->dma_lock, flags);
528 if (done)
529 mmc_omap_xfer_done(host, data);
530 }
531
532 static void
533 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
534 {
535 unsigned long flags;
536 int done;
537
538 done = 0;
539 spin_lock_irqsave(&host->dma_lock, flags);
540 if (host->brs_received)
541 done = 1;
542 else
543 host->dma_done = 1;
544 spin_unlock_irqrestore(&host->dma_lock, flags);
545 if (done)
546 mmc_omap_xfer_done(host, data);
547 }
548
549 static void
550 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
551 {
552 host->cmd = NULL;
553
554 del_timer(&host->cmd_abort_timer);
555
556 if (cmd->flags & MMC_RSP_PRESENT) {
557 if (cmd->flags & MMC_RSP_136) {
558 /* response type 2 */
559 cmd->resp[3] =
560 OMAP_MMC_READ(host, RSP0) |
561 (OMAP_MMC_READ(host, RSP1) << 16);
562 cmd->resp[2] =
563 OMAP_MMC_READ(host, RSP2) |
564 (OMAP_MMC_READ(host, RSP3) << 16);
565 cmd->resp[1] =
566 OMAP_MMC_READ(host, RSP4) |
567 (OMAP_MMC_READ(host, RSP5) << 16);
568 cmd->resp[0] =
569 OMAP_MMC_READ(host, RSP6) |
570 (OMAP_MMC_READ(host, RSP7) << 16);
571 } else {
572 /* response types 1, 1b, 3, 4, 5, 6 */
573 cmd->resp[0] =
574 OMAP_MMC_READ(host, RSP6) |
575 (OMAP_MMC_READ(host, RSP7) << 16);
576 }
577 }
578
579 if (host->data == NULL || cmd->error) {
580 struct mmc_host *mmc;
581
582 if (host->data != NULL)
583 mmc_omap_abort_xfer(host, host->data);
584 host->mrq = NULL;
585 mmc = host->mmc;
586 mmc_omap_release_slot(host->current_slot, 1);
587 mmc_request_done(mmc, cmd->mrq);
588 }
589 }
590
591 /*
592 * Abort stuck command. Can occur when card is removed while it is being
593 * read.
594 */
595 static void mmc_omap_abort_command(struct work_struct *work)
596 {
597 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
598 cmd_abort_work);
599 BUG_ON(!host->cmd);
600
601 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
602 host->cmd->opcode);
603
604 if (host->cmd->error == 0)
605 host->cmd->error = -ETIMEDOUT;
606
607 if (host->data == NULL) {
608 struct mmc_command *cmd;
609 struct mmc_host *mmc;
610
611 cmd = host->cmd;
612 host->cmd = NULL;
613 mmc_omap_send_abort(host, 10000);
614
615 host->mrq = NULL;
616 mmc = host->mmc;
617 mmc_omap_release_slot(host->current_slot, 1);
618 mmc_request_done(mmc, cmd->mrq);
619 } else
620 mmc_omap_cmd_done(host, host->cmd);
621
622 host->abort = 0;
623 enable_irq(host->irq);
624 }
625
626 static void
627 mmc_omap_cmd_timer(unsigned long data)
628 {
629 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
630 unsigned long flags;
631
632 spin_lock_irqsave(&host->slot_lock, flags);
633 if (host->cmd != NULL && !host->abort) {
634 OMAP_MMC_WRITE(host, IE, 0);
635 disable_irq(host->irq);
636 host->abort = 1;
637 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
638 }
639 spin_unlock_irqrestore(&host->slot_lock, flags);
640 }
641
642 /* PIO only */
643 static void
644 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
645 {
646 struct scatterlist *sg;
647
648 sg = host->data->sg + host->sg_idx;
649 host->buffer_bytes_left = sg->length;
650 host->buffer = sg_virt(sg);
651 if (host->buffer_bytes_left > host->total_bytes_left)
652 host->buffer_bytes_left = host->total_bytes_left;
653 }
654
655 static void
656 mmc_omap_clk_timer(unsigned long data)
657 {
658 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
659
660 mmc_omap_fclk_enable(host, 0);
661 }
662
663 /* PIO only */
664 static void
665 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
666 {
667 int n, nwords;
668
669 if (host->buffer_bytes_left == 0) {
670 host->sg_idx++;
671 BUG_ON(host->sg_idx == host->sg_len);
672 mmc_omap_sg_to_buf(host);
673 }
674 n = 64;
675 if (n > host->buffer_bytes_left)
676 n = host->buffer_bytes_left;
677
678 nwords = n / 2;
679 nwords += n & 1; /* handle odd number of bytes to transfer */
680
681 host->buffer_bytes_left -= n;
682 host->total_bytes_left -= n;
683 host->data->bytes_xfered += n;
684
685 if (write) {
686 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
687 host->buffer, nwords);
688 } else {
689 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
690 host->buffer, nwords);
691 }
692
693 host->buffer += nwords;
694 }
695
696 #ifdef CONFIG_MMC_DEBUG
697 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
698 {
699 static const char *mmc_omap_status_bits[] = {
700 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
701 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
702 };
703 int i;
704 char res[64], *buf = res;
705
706 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
707
708 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
709 if (status & (1 << i))
710 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
711 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
712 }
713 #else
714 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
715 {
716 }
717 #endif
718
719
720 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
721 {
722 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
723 u16 status;
724 int end_command;
725 int end_transfer;
726 int transfer_error, cmd_error;
727
728 if (host->cmd == NULL && host->data == NULL) {
729 status = OMAP_MMC_READ(host, STAT);
730 dev_info(mmc_dev(host->slots[0]->mmc),
731 "Spurious IRQ 0x%04x\n", status);
732 if (status != 0) {
733 OMAP_MMC_WRITE(host, STAT, status);
734 OMAP_MMC_WRITE(host, IE, 0);
735 }
736 return IRQ_HANDLED;
737 }
738
739 end_command = 0;
740 end_transfer = 0;
741 transfer_error = 0;
742 cmd_error = 0;
743
744 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
745 int cmd;
746
747 OMAP_MMC_WRITE(host, STAT, status);
748 if (host->cmd != NULL)
749 cmd = host->cmd->opcode;
750 else
751 cmd = -1;
752 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
753 status, cmd);
754 mmc_omap_report_irq(host, status);
755
756 if (host->total_bytes_left) {
757 if ((status & OMAP_MMC_STAT_A_FULL) ||
758 (status & OMAP_MMC_STAT_END_OF_DATA))
759 mmc_omap_xfer_data(host, 0);
760 if (status & OMAP_MMC_STAT_A_EMPTY)
761 mmc_omap_xfer_data(host, 1);
762 }
763
764 if (status & OMAP_MMC_STAT_END_OF_DATA)
765 end_transfer = 1;
766
767 if (status & OMAP_MMC_STAT_DATA_TOUT) {
768 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
769 cmd);
770 if (host->data) {
771 host->data->error = -ETIMEDOUT;
772 transfer_error = 1;
773 }
774 }
775
776 if (status & OMAP_MMC_STAT_DATA_CRC) {
777 if (host->data) {
778 host->data->error = -EILSEQ;
779 dev_dbg(mmc_dev(host->mmc),
780 "data CRC error, bytes left %d\n",
781 host->total_bytes_left);
782 transfer_error = 1;
783 } else {
784 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
785 }
786 }
787
788 if (status & OMAP_MMC_STAT_CMD_TOUT) {
789 /* Timeouts are routine with some commands */
790 if (host->cmd) {
791 struct mmc_omap_slot *slot =
792 host->current_slot;
793 if (slot == NULL ||
794 !mmc_omap_cover_is_open(slot))
795 dev_err(mmc_dev(host->mmc),
796 "command timeout (CMD%d)\n",
797 cmd);
798 host->cmd->error = -ETIMEDOUT;
799 end_command = 1;
800 cmd_error = 1;
801 }
802 }
803
804 if (status & OMAP_MMC_STAT_CMD_CRC) {
805 if (host->cmd) {
806 dev_err(mmc_dev(host->mmc),
807 "command CRC error (CMD%d, arg 0x%08x)\n",
808 cmd, host->cmd->arg);
809 host->cmd->error = -EILSEQ;
810 end_command = 1;
811 cmd_error = 1;
812 } else
813 dev_err(mmc_dev(host->mmc),
814 "command CRC error without cmd?\n");
815 }
816
817 if (status & OMAP_MMC_STAT_CARD_ERR) {
818 dev_dbg(mmc_dev(host->mmc),
819 "ignoring card status error (CMD%d)\n",
820 cmd);
821 end_command = 1;
822 }
823
824 /*
825 * NOTE: On 1610 the END_OF_CMD may come too early when
826 * starting a write
827 */
828 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
829 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
830 end_command = 1;
831 }
832 }
833
834 if (cmd_error && host->data) {
835 del_timer(&host->cmd_abort_timer);
836 host->abort = 1;
837 OMAP_MMC_WRITE(host, IE, 0);
838 disable_irq_nosync(host->irq);
839 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
840 return IRQ_HANDLED;
841 }
842
843 if (end_command && host->cmd)
844 mmc_omap_cmd_done(host, host->cmd);
845 if (host->data != NULL) {
846 if (transfer_error)
847 mmc_omap_xfer_done(host, host->data);
848 else if (end_transfer)
849 mmc_omap_end_of_data(host, host->data);
850 }
851
852 return IRQ_HANDLED;
853 }
854
855 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
856 {
857 int cover_open;
858 struct mmc_omap_host *host = dev_get_drvdata(dev);
859 struct mmc_omap_slot *slot = host->slots[num];
860
861 BUG_ON(num >= host->nr_slots);
862
863 /* Other subsystems can call in here before we're initialised. */
864 if (host->nr_slots == 0 || !host->slots[num])
865 return;
866
867 cover_open = mmc_omap_cover_is_open(slot);
868 if (cover_open != slot->cover_open) {
869 slot->cover_open = cover_open;
870 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
871 }
872
873 tasklet_hi_schedule(&slot->cover_tasklet);
874 }
875
876 static void mmc_omap_cover_timer(unsigned long arg)
877 {
878 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
879 tasklet_schedule(&slot->cover_tasklet);
880 }
881
882 static void mmc_omap_cover_handler(unsigned long param)
883 {
884 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
885 int cover_open = mmc_omap_cover_is_open(slot);
886
887 mmc_detect_change(slot->mmc, 0);
888 if (!cover_open)
889 return;
890
891 /*
892 * If no card is inserted, we postpone polling until
893 * the cover has been closed.
894 */
895 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
896 return;
897
898 mod_timer(&slot->cover_timer,
899 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
900 }
901
902 static void mmc_omap_dma_callback(void *priv)
903 {
904 struct mmc_omap_host *host = priv;
905 struct mmc_data *data = host->data;
906
907 /* If we got to the end of DMA, assume everything went well */
908 data->bytes_xfered += data->blocks * data->blksz;
909
910 mmc_omap_dma_done(host, data);
911 }
912
913 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
914 {
915 u16 reg;
916
917 reg = OMAP_MMC_READ(host, SDIO);
918 reg &= ~(1 << 5);
919 OMAP_MMC_WRITE(host, SDIO, reg);
920 /* Set maximum timeout */
921 OMAP_MMC_WRITE(host, CTO, 0xff);
922 }
923
924 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
925 {
926 unsigned int timeout, cycle_ns;
927 u16 reg;
928
929 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
930 timeout = req->data->timeout_ns / cycle_ns;
931 timeout += req->data->timeout_clks;
932
933 /* Check if we need to use timeout multiplier register */
934 reg = OMAP_MMC_READ(host, SDIO);
935 if (timeout > 0xffff) {
936 reg |= (1 << 5);
937 timeout /= 1024;
938 } else
939 reg &= ~(1 << 5);
940 OMAP_MMC_WRITE(host, SDIO, reg);
941 OMAP_MMC_WRITE(host, DTO, timeout);
942 }
943
944 static void
945 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
946 {
947 struct mmc_data *data = req->data;
948 int i, use_dma, block_size;
949 unsigned sg_len;
950
951 host->data = data;
952 if (data == NULL) {
953 OMAP_MMC_WRITE(host, BLEN, 0);
954 OMAP_MMC_WRITE(host, NBLK, 0);
955 OMAP_MMC_WRITE(host, BUF, 0);
956 host->dma_in_use = 0;
957 set_cmd_timeout(host, req);
958 return;
959 }
960
961 block_size = data->blksz;
962
963 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
964 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
965 set_data_timeout(host, req);
966
967 /* cope with calling layer confusion; it issues "single
968 * block" writes using multi-block scatterlists.
969 */
970 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
971
972 /* Only do DMA for entire blocks */
973 use_dma = host->use_dma;
974 if (use_dma) {
975 for (i = 0; i < sg_len; i++) {
976 if ((data->sg[i].length % block_size) != 0) {
977 use_dma = 0;
978 break;
979 }
980 }
981 }
982
983 host->sg_idx = 0;
984 if (use_dma) {
985 enum dma_data_direction dma_data_dir;
986 struct dma_async_tx_descriptor *tx;
987 struct dma_chan *c;
988 u32 burst, *bp;
989 u16 buf;
990
991 /*
992 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
993 * and 24xx. Use 16 or 32 word frames when the
994 * blocksize is at least that large. Blocksize is
995 * usually 512 bytes; but not for some SD reads.
996 */
997 burst = mmc_omap15xx() ? 32 : 64;
998 if (burst > data->blksz)
999 burst = data->blksz;
1000
1001 burst >>= 1;
1002
1003 if (data->flags & MMC_DATA_WRITE) {
1004 c = host->dma_tx;
1005 bp = &host->dma_tx_burst;
1006 buf = 0x0f80 | (burst - 1) << 0;
1007 dma_data_dir = DMA_TO_DEVICE;
1008 } else {
1009 c = host->dma_rx;
1010 bp = &host->dma_rx_burst;
1011 buf = 0x800f | (burst - 1) << 8;
1012 dma_data_dir = DMA_FROM_DEVICE;
1013 }
1014
1015 if (!c)
1016 goto use_pio;
1017
1018 /* Only reconfigure if we have a different burst size */
1019 if (*bp != burst) {
1020 struct dma_slave_config cfg;
1021
1022 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1023 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1024 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1025 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1026 cfg.src_maxburst = burst;
1027 cfg.dst_maxburst = burst;
1028
1029 if (dmaengine_slave_config(c, &cfg))
1030 goto use_pio;
1031
1032 *bp = burst;
1033 }
1034
1035 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1036 dma_data_dir);
1037 if (host->sg_len == 0)
1038 goto use_pio;
1039
1040 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1041 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1042 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1043 if (!tx)
1044 goto use_pio;
1045
1046 OMAP_MMC_WRITE(host, BUF, buf);
1047
1048 tx->callback = mmc_omap_dma_callback;
1049 tx->callback_param = host;
1050 dmaengine_submit(tx);
1051 host->brs_received = 0;
1052 host->dma_done = 0;
1053 host->dma_in_use = 1;
1054 return;
1055 }
1056 use_pio:
1057
1058 /* Revert to PIO? */
1059 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1060 host->total_bytes_left = data->blocks * block_size;
1061 host->sg_len = sg_len;
1062 mmc_omap_sg_to_buf(host);
1063 host->dma_in_use = 0;
1064 }
1065
1066 static void mmc_omap_start_request(struct mmc_omap_host *host,
1067 struct mmc_request *req)
1068 {
1069 BUG_ON(host->mrq != NULL);
1070
1071 host->mrq = req;
1072
1073 /* only touch fifo AFTER the controller readies it */
1074 mmc_omap_prepare_data(host, req);
1075 mmc_omap_start_command(host, req->cmd);
1076 if (host->dma_in_use) {
1077 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1078 host->dma_tx : host->dma_rx;
1079
1080 dma_async_issue_pending(c);
1081 }
1082 }
1083
1084 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1085 {
1086 struct mmc_omap_slot *slot = mmc_priv(mmc);
1087 struct mmc_omap_host *host = slot->host;
1088 unsigned long flags;
1089
1090 spin_lock_irqsave(&host->slot_lock, flags);
1091 if (host->mmc != NULL) {
1092 BUG_ON(slot->mrq != NULL);
1093 slot->mrq = req;
1094 spin_unlock_irqrestore(&host->slot_lock, flags);
1095 return;
1096 } else
1097 host->mmc = mmc;
1098 spin_unlock_irqrestore(&host->slot_lock, flags);
1099 mmc_omap_select_slot(slot, 1);
1100 mmc_omap_start_request(host, req);
1101 }
1102
1103 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1104 int vdd)
1105 {
1106 struct mmc_omap_host *host;
1107
1108 host = slot->host;
1109
1110 if (slot->pdata->set_power != NULL)
1111 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1112 vdd);
1113 if (mmc_omap2()) {
1114 u16 w;
1115
1116 if (power_on) {
1117 w = OMAP_MMC_READ(host, CON);
1118 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1119 } else {
1120 w = OMAP_MMC_READ(host, CON);
1121 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1122 }
1123 }
1124 }
1125
1126 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1127 {
1128 struct mmc_omap_slot *slot = mmc_priv(mmc);
1129 struct mmc_omap_host *host = slot->host;
1130 int func_clk_rate = clk_get_rate(host->fclk);
1131 int dsor;
1132
1133 if (ios->clock == 0)
1134 return 0;
1135
1136 dsor = func_clk_rate / ios->clock;
1137 if (dsor < 1)
1138 dsor = 1;
1139
1140 if (func_clk_rate / dsor > ios->clock)
1141 dsor++;
1142
1143 if (dsor > 250)
1144 dsor = 250;
1145
1146 slot->fclk_freq = func_clk_rate / dsor;
1147
1148 if (ios->bus_width == MMC_BUS_WIDTH_4)
1149 dsor |= 1 << 15;
1150
1151 return dsor;
1152 }
1153
1154 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1155 {
1156 struct mmc_omap_slot *slot = mmc_priv(mmc);
1157 struct mmc_omap_host *host = slot->host;
1158 int i, dsor;
1159 int clk_enabled;
1160
1161 mmc_omap_select_slot(slot, 0);
1162
1163 dsor = mmc_omap_calc_divisor(mmc, ios);
1164
1165 if (ios->vdd != slot->vdd)
1166 slot->vdd = ios->vdd;
1167
1168 clk_enabled = 0;
1169 switch (ios->power_mode) {
1170 case MMC_POWER_OFF:
1171 mmc_omap_set_power(slot, 0, ios->vdd);
1172 break;
1173 case MMC_POWER_UP:
1174 /* Cannot touch dsor yet, just power up MMC */
1175 mmc_omap_set_power(slot, 1, ios->vdd);
1176 goto exit;
1177 case MMC_POWER_ON:
1178 mmc_omap_fclk_enable(host, 1);
1179 clk_enabled = 1;
1180 dsor |= 1 << 11;
1181 break;
1182 }
1183
1184 if (slot->bus_mode != ios->bus_mode) {
1185 if (slot->pdata->set_bus_mode != NULL)
1186 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1187 ios->bus_mode);
1188 slot->bus_mode = ios->bus_mode;
1189 }
1190
1191 /* On insanely high arm_per frequencies something sometimes
1192 * goes somehow out of sync, and the POW bit is not being set,
1193 * which results in the while loop below getting stuck.
1194 * Writing to the CON register twice seems to do the trick. */
1195 for (i = 0; i < 2; i++)
1196 OMAP_MMC_WRITE(host, CON, dsor);
1197 slot->saved_con = dsor;
1198 if (ios->power_mode == MMC_POWER_ON) {
1199 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1200 int usecs = 250;
1201
1202 /* Send clock cycles, poll completion */
1203 OMAP_MMC_WRITE(host, IE, 0);
1204 OMAP_MMC_WRITE(host, STAT, 0xffff);
1205 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1206 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1207 udelay(1);
1208 usecs--;
1209 }
1210 OMAP_MMC_WRITE(host, STAT, 1);
1211 }
1212
1213 exit:
1214 mmc_omap_release_slot(slot, clk_enabled);
1215 }
1216
1217 static const struct mmc_host_ops mmc_omap_ops = {
1218 .request = mmc_omap_request,
1219 .set_ios = mmc_omap_set_ios,
1220 };
1221
1222 static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1223 {
1224 struct mmc_omap_slot *slot = NULL;
1225 struct mmc_host *mmc;
1226 int r;
1227
1228 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1229 if (mmc == NULL)
1230 return -ENOMEM;
1231
1232 slot = mmc_priv(mmc);
1233 slot->host = host;
1234 slot->mmc = mmc;
1235 slot->id = id;
1236 slot->pdata = &host->pdata->slots[id];
1237
1238 host->slots[id] = slot;
1239
1240 mmc->caps = 0;
1241 if (host->pdata->slots[id].wires >= 4)
1242 mmc->caps |= MMC_CAP_4_BIT_DATA;
1243
1244 mmc->ops = &mmc_omap_ops;
1245 mmc->f_min = 400000;
1246
1247 if (mmc_omap2())
1248 mmc->f_max = 48000000;
1249 else
1250 mmc->f_max = 24000000;
1251 if (host->pdata->max_freq)
1252 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1253 mmc->ocr_avail = slot->pdata->ocr_mask;
1254
1255 /* Use scatterlist DMA to reduce per-transfer costs.
1256 * NOTE max_seg_size assumption that small blocks aren't
1257 * normally used (except e.g. for reading SD registers).
1258 */
1259 mmc->max_segs = 32;
1260 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1261 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1262 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1263 mmc->max_seg_size = mmc->max_req_size;
1264
1265 r = mmc_add_host(mmc);
1266 if (r < 0)
1267 goto err_remove_host;
1268
1269 if (slot->pdata->name != NULL) {
1270 r = device_create_file(&mmc->class_dev,
1271 &dev_attr_slot_name);
1272 if (r < 0)
1273 goto err_remove_host;
1274 }
1275
1276 if (slot->pdata->get_cover_state != NULL) {
1277 r = device_create_file(&mmc->class_dev,
1278 &dev_attr_cover_switch);
1279 if (r < 0)
1280 goto err_remove_slot_name;
1281
1282 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1283 (unsigned long)slot);
1284 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1285 (unsigned long)slot);
1286 tasklet_schedule(&slot->cover_tasklet);
1287 }
1288
1289 return 0;
1290
1291 err_remove_slot_name:
1292 if (slot->pdata->name != NULL)
1293 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1294 err_remove_host:
1295 mmc_remove_host(mmc);
1296 mmc_free_host(mmc);
1297 return r;
1298 }
1299
1300 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1301 {
1302 struct mmc_host *mmc = slot->mmc;
1303
1304 if (slot->pdata->name != NULL)
1305 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1306 if (slot->pdata->get_cover_state != NULL)
1307 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1308
1309 tasklet_kill(&slot->cover_tasklet);
1310 del_timer_sync(&slot->cover_timer);
1311 flush_workqueue(slot->host->mmc_omap_wq);
1312
1313 mmc_remove_host(mmc);
1314 mmc_free_host(mmc);
1315 }
1316
1317 static int mmc_omap_probe(struct platform_device *pdev)
1318 {
1319 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1320 struct mmc_omap_host *host = NULL;
1321 struct resource *res;
1322 dma_cap_mask_t mask;
1323 unsigned sig = 0;
1324 int i, ret = 0;
1325 int irq;
1326
1327 if (pdata == NULL) {
1328 dev_err(&pdev->dev, "platform data missing\n");
1329 return -ENXIO;
1330 }
1331 if (pdata->nr_slots == 0) {
1332 dev_err(&pdev->dev, "no slots\n");
1333 return -EPROBE_DEFER;
1334 }
1335
1336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1337 irq = platform_get_irq(pdev, 0);
1338 if (res == NULL || irq < 0)
1339 return -ENXIO;
1340
1341 res = request_mem_region(res->start, resource_size(res),
1342 pdev->name);
1343 if (res == NULL)
1344 return -EBUSY;
1345
1346 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1347 if (host == NULL) {
1348 ret = -ENOMEM;
1349 goto err_free_mem_region;
1350 }
1351
1352 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1353 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1354
1355 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1356 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1357 (unsigned long) host);
1358
1359 spin_lock_init(&host->clk_lock);
1360 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1361
1362 spin_lock_init(&host->dma_lock);
1363 spin_lock_init(&host->slot_lock);
1364 init_waitqueue_head(&host->slot_wq);
1365
1366 host->pdata = pdata;
1367 host->features = host->pdata->slots[0].features;
1368 host->dev = &pdev->dev;
1369 platform_set_drvdata(pdev, host);
1370
1371 host->id = pdev->id;
1372 host->mem_res = res;
1373 host->irq = irq;
1374 host->use_dma = 1;
1375 host->irq = irq;
1376 host->phys_base = host->mem_res->start;
1377 host->virt_base = ioremap(res->start, resource_size(res));
1378 if (!host->virt_base)
1379 goto err_ioremap;
1380
1381 host->iclk = clk_get(&pdev->dev, "ick");
1382 if (IS_ERR(host->iclk)) {
1383 ret = PTR_ERR(host->iclk);
1384 goto err_free_mmc_host;
1385 }
1386 clk_enable(host->iclk);
1387
1388 host->fclk = clk_get(&pdev->dev, "fck");
1389 if (IS_ERR(host->fclk)) {
1390 ret = PTR_ERR(host->fclk);
1391 goto err_free_iclk;
1392 }
1393
1394 dma_cap_zero(mask);
1395 dma_cap_set(DMA_SLAVE, mask);
1396
1397 host->dma_tx_burst = -1;
1398 host->dma_rx_burst = -1;
1399
1400 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1401 if (res)
1402 sig = res->start;
1403 host->dma_tx = dma_request_slave_channel_compat(mask,
1404 omap_dma_filter_fn, &sig, &pdev->dev, "tx");
1405 if (!host->dma_tx)
1406 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1407 sig);
1408
1409 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1410 if (res)
1411 sig = res->start;
1412 host->dma_rx = dma_request_slave_channel_compat(mask,
1413 omap_dma_filter_fn, &sig, &pdev->dev, "rx");
1414 if (!host->dma_rx)
1415 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1416 sig);
1417
1418 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1419 if (ret)
1420 goto err_free_dma;
1421
1422 if (pdata->init != NULL) {
1423 ret = pdata->init(&pdev->dev);
1424 if (ret < 0)
1425 goto err_free_irq;
1426 }
1427
1428 host->nr_slots = pdata->nr_slots;
1429 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1430
1431 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1432 if (!host->mmc_omap_wq)
1433 goto err_plat_cleanup;
1434
1435 for (i = 0; i < pdata->nr_slots; i++) {
1436 ret = mmc_omap_new_slot(host, i);
1437 if (ret < 0) {
1438 while (--i >= 0)
1439 mmc_omap_remove_slot(host->slots[i]);
1440
1441 goto err_destroy_wq;
1442 }
1443 }
1444
1445 return 0;
1446
1447 err_destroy_wq:
1448 destroy_workqueue(host->mmc_omap_wq);
1449 err_plat_cleanup:
1450 if (pdata->cleanup)
1451 pdata->cleanup(&pdev->dev);
1452 err_free_irq:
1453 free_irq(host->irq, host);
1454 err_free_dma:
1455 if (host->dma_tx)
1456 dma_release_channel(host->dma_tx);
1457 if (host->dma_rx)
1458 dma_release_channel(host->dma_rx);
1459 clk_put(host->fclk);
1460 err_free_iclk:
1461 clk_disable(host->iclk);
1462 clk_put(host->iclk);
1463 err_free_mmc_host:
1464 iounmap(host->virt_base);
1465 err_ioremap:
1466 kfree(host);
1467 err_free_mem_region:
1468 release_mem_region(res->start, resource_size(res));
1469 return ret;
1470 }
1471
1472 static int mmc_omap_remove(struct platform_device *pdev)
1473 {
1474 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1475 int i;
1476
1477 BUG_ON(host == NULL);
1478
1479 for (i = 0; i < host->nr_slots; i++)
1480 mmc_omap_remove_slot(host->slots[i]);
1481
1482 if (host->pdata->cleanup)
1483 host->pdata->cleanup(&pdev->dev);
1484
1485 mmc_omap_fclk_enable(host, 0);
1486 free_irq(host->irq, host);
1487 clk_put(host->fclk);
1488 clk_disable(host->iclk);
1489 clk_put(host->iclk);
1490
1491 if (host->dma_tx)
1492 dma_release_channel(host->dma_tx);
1493 if (host->dma_rx)
1494 dma_release_channel(host->dma_rx);
1495
1496 iounmap(host->virt_base);
1497 release_mem_region(pdev->resource[0].start,
1498 pdev->resource[0].end - pdev->resource[0].start + 1);
1499 destroy_workqueue(host->mmc_omap_wq);
1500
1501 kfree(host);
1502
1503 return 0;
1504 }
1505
1506 #if IS_BUILTIN(CONFIG_OF)
1507 static const struct of_device_id mmc_omap_match[] = {
1508 { .compatible = "ti,omap2420-mmc", },
1509 { },
1510 };
1511 #endif
1512
1513 static struct platform_driver mmc_omap_driver = {
1514 .probe = mmc_omap_probe,
1515 .remove = mmc_omap_remove,
1516 .driver = {
1517 .name = DRIVER_NAME,
1518 .owner = THIS_MODULE,
1519 .of_match_table = of_match_ptr(mmc_omap_match),
1520 },
1521 };
1522
1523 module_platform_driver(mmc_omap_driver);
1524 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1525 MODULE_LICENSE("GPL");
1526 MODULE_ALIAS("platform:" DRIVER_NAME);
1527 MODULE_AUTHOR("Juha Yrjölä");
Linux with added FPC-III support