drivers/mmc/host/sdhci-pci-o2micro.c

   1 /*
   2  * Copyright (C) 2013 BayHub Technology Ltd.
   3  *
   4  * Authors: Peter Guo <peter.guo@bayhubtech.com>
   5  *          Adam Lee <adam.lee@canonical.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/pci.h>
  19
  20 #include "sdhci.h"
  21 #include "sdhci-pci.h"
  22 #include "sdhci-pci-o2micro.h"
  23
  24 void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
  25 {
  26         u32 scratch_32;
  27         int ret;
  28         /* Improve write performance for SD3.0 */
  29         ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
  30         if (ret)
  31                 return;
  32         scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
  33         pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
  34
  35         /* Enable Link abnormal reset generating Reset */
  36         ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
  37         if (ret)
  38                 return;
  39         scratch_32 &= ~((1 << 19) | (1 << 11));
  40         scratch_32 |= (1 << 10);
  41         pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
  42
  43         /* set card power over current protection */
  44         ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
  45         if (ret)
  46                 return;
  47         scratch_32 |= (1 << 4);
  48         pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
  49
  50         /* adjust the output delay for SD mode */
  51         pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
  52
  53         /* Set the output voltage setting of Aux 1.2v LDO */
  54         ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
  55         if (ret)
  56                 return;
  57         scratch_32 &= ~(3 << 12);
  58         pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
  59
  60         /* Set Max power supply capability of SD host */
  61         ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
  62         if (ret)
  63                 return;
  64         scratch_32 &= ~(0x01FE);
  65         scratch_32 |= 0x00CC;
  66         pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
  67         /* Set DLL Tuning Window */
  68         ret = pci_read_config_dword(chip->pdev,
  69                                     O2_SD_TUNING_CTRL, &scratch_32);
  70         if (ret)
  71                 return;
  72         scratch_32 &= ~(0x000000FF);
  73         scratch_32 |= 0x00000066;
  74         pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
  75
  76         /* Set UHS2 T_EIDLE */
  77         ret = pci_read_config_dword(chip->pdev,
  78                                     O2_SD_UHS2_L1_CTRL, &scratch_32);
  79         if (ret)
  80                 return;
  81         scratch_32 &= ~(0x000000FC);
  82         scratch_32 |= 0x00000084;
  83         pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
  84
  85         /* Set UHS2 Termination */
  86         ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
  87         if (ret)
  88                 return;
  89         scratch_32 &= ~((1 << 21) | (1 << 30));
  90
  91         /* Set RTD3 function disabled */
  92         scratch_32 |= ((1 << 29) | (1 << 28));
  93         pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
  94
  95         /* Set L1 Entrance Timer */
  96         ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
  97         if (ret)
  98                 return;
  99         scratch_32 &= ~(0xf0000000);
 100         scratch_32 |= 0x30000000;
 101         pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
 102
 103         ret = pci_read_config_dword(chip->pdev,
 104                                     O2_SD_MISC_CTRL4, &scratch_32);
 105         if (ret)
 106                 return;
 107         scratch_32 &= ~(0x000f0000);
 108         scratch_32 |= 0x00080000;
 109         pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
 110 }
 111 EXPORT_SYMBOL_GPL(sdhci_pci_o2_fujin2_pci_init);
 112
 113 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
 114 {
 115         struct sdhci_pci_chip *chip;
 116         struct sdhci_host *host;
 117         u32 reg;
 118
 119         chip = slot->chip;
 120         host = slot->host;
 121         switch (chip->pdev->device) {
 122         case PCI_DEVICE_ID_O2_SDS0:
 123         case PCI_DEVICE_ID_O2_SEABIRD0:
 124         case PCI_DEVICE_ID_O2_SEABIRD1:
 125         case PCI_DEVICE_ID_O2_SDS1:
 126         case PCI_DEVICE_ID_O2_FUJIN2:
 127                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
 128                 if (reg & 0x1)
 129                         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 130
 131                 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
 132                         break;
 133                 /* set dll watch dog timer */
 134                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
 135                 reg |= (1 << 12);
 136                 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
 137
 138                 break;
 139         default:
 140                 break;
 141         }
 142
 143         return 0;
 144 }
 145 EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe_slot);
 146
 147 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 148 {
 149         int ret;
 150         u8 scratch;
 151         u32 scratch_32;
 152
 153         switch (chip->pdev->device) {
 154         case PCI_DEVICE_ID_O2_8220:
 155         case PCI_DEVICE_ID_O2_8221:
 156         case PCI_DEVICE_ID_O2_8320:
 157         case PCI_DEVICE_ID_O2_8321:
 158                 /* This extra setup is required due to broken ADMA. */
 159                 ret = pci_read_config_byte(chip->pdev,
 160                                 O2_SD_LOCK_WP, &scratch);
 161                 if (ret)
 162                         return ret;
 163                 scratch &= 0x7f;
 164                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 165
 166                 /* Set Multi 3 to VCC3V# */
 167                 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
 168
 169                 /* Disable CLK_REQ# support after media DET */
 170                 ret = pci_read_config_byte(chip->pdev,
 171                                 O2_SD_CLKREQ, &scratch);
 172                 if (ret)
 173                         return ret;
 174                 scratch |= 0x20;
 175                 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
 176
 177                 /* Choose capabilities, enable SDMA.  We have to write 0x01
 178                  * to the capabilities register first to unlock it.
 179                  */
 180                 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
 181                 if (ret)
 182                         return ret;
 183                 scratch |= 0x01;
 184                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
 185                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
 186
 187                 /* Disable ADMA1/2 */
 188                 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
 189                 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
 190
 191                 /* Disable the infinite transfer mode */
 192                 ret = pci_read_config_byte(chip->pdev,
 193                                 O2_SD_INF_MOD, &scratch);
 194                 if (ret)
 195                         return ret;
 196                 scratch |= 0x08;
 197                 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
 198
 199                 /* Lock WP */
 200                 ret = pci_read_config_byte(chip->pdev,
 201                                 O2_SD_LOCK_WP, &scratch);
 202                 if (ret)
 203                         return ret;
 204                 scratch |= 0x80;
 205                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 206                 break;
 207         case PCI_DEVICE_ID_O2_SDS0:
 208         case PCI_DEVICE_ID_O2_SDS1:
 209         case PCI_DEVICE_ID_O2_FUJIN2:
 210                 /* UnLock WP */
 211                 ret = pci_read_config_byte(chip->pdev,
 212                                 O2_SD_LOCK_WP, &scratch);
 213                 if (ret)
 214                         return ret;
 215
 216                 scratch &= 0x7f;
 217                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 218
 219                 /* Set timeout CLK */
 220                 ret = pci_read_config_dword(chip->pdev,
 221                                             O2_SD_CLK_SETTING, &scratch_32);
 222                 if (ret)
 223                         return ret;
 224
 225                 scratch_32 &= ~(0xFF00);
 226                 scratch_32 |= 0x07E0C800;
 227                 pci_write_config_dword(chip->pdev,
 228                                        O2_SD_CLK_SETTING, scratch_32);
 229
 230                 ret = pci_read_config_dword(chip->pdev,
 231                                             O2_SD_CLKREQ, &scratch_32);
 232                 if (ret)
 233                         return ret;
 234                 scratch_32 |= 0x3;
 235                 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
 236
 237                 ret = pci_read_config_dword(chip->pdev,
 238                                             O2_SD_PLL_SETTING, &scratch_32);
 239                 if (ret)
 240                         return ret;
 241
 242                 scratch_32 &= ~(0x1F3F070E);
 243                 scratch_32 |= 0x18270106;
 244                 pci_write_config_dword(chip->pdev,
 245                                        O2_SD_PLL_SETTING, scratch_32);
 246
 247                 /* Disable UHS1 funciton */
 248                 ret = pci_read_config_dword(chip->pdev,
 249                                             O2_SD_CAP_REG2, &scratch_32);
 250                 if (ret)
 251                         return ret;
 252                 scratch_32 &= ~(0xE0);
 253                 pci_write_config_dword(chip->pdev,
 254                                        O2_SD_CAP_REG2, scratch_32);
 255
 256                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
 257                         sdhci_pci_o2_fujin2_pci_init(chip);
 258
 259                 /* Lock WP */
 260                 ret = pci_read_config_byte(chip->pdev,
 261                                            O2_SD_LOCK_WP, &scratch);
 262                 if (ret)
 263                         return ret;
 264                 scratch |= 0x80;
 265                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 266                 break;
 267         case PCI_DEVICE_ID_O2_SEABIRD0:
 268         case PCI_DEVICE_ID_O2_SEABIRD1:
 269                 /* UnLock WP */
 270                 ret = pci_read_config_byte(chip->pdev,
 271                                 O2_SD_LOCK_WP, &scratch);
 272                 if (ret)
 273                         return ret;
 274
 275                 scratch &= 0x7f;
 276                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 277
 278                 ret = pci_read_config_dword(chip->pdev,
 279                                             O2_SD_FUNC_REG0, &scratch_32);
 280
 281                 if ((scratch_32 & 0xff000000) == 0x01000000) {
 282                         scratch_32 &= 0x0000FFFF;
 283                         scratch_32 |= 0x1F340000;
 284
 285                         pci_write_config_dword(chip->pdev,
 286                                                O2_SD_PLL_SETTING, scratch_32);
 287                 } else {
 288                         scratch_32 &= 0x0000FFFF;
 289                         scratch_32 |= 0x2c280000;
 290
 291                         pci_write_config_dword(chip->pdev,
 292                                                O2_SD_PLL_SETTING, scratch_32);
 293
 294                         ret = pci_read_config_dword(chip->pdev,
 295                                                     O2_SD_FUNC_REG4,
 296                                                     &scratch_32);
 297                         scratch_32 |= (1 << 22);
 298                         pci_write_config_dword(chip->pdev,
 299                                                O2_SD_FUNC_REG4, scratch_32);
 300                 }
 301
 302                 /* Lock WP */
 303                 ret = pci_read_config_byte(chip->pdev,
 304                                            O2_SD_LOCK_WP, &scratch);
 305                 if (ret)
 306                         return ret;
 307                 scratch |= 0x80;
 308                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 309                 break;
 310         }
 311
 312         return 0;
 313 }
 314 EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe);
 315
 316 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
 317 {
 318         sdhci_pci_o2_probe(chip);
 319         return 0;
 320 }
 321 EXPORT_SYMBOL_GPL(sdhci_pci_o2_resume);