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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / mtd / nand / atmel_nand.c
blobc36e9b84487cd36b55d96efd1d17c6db9494c0fc
1 /*
2 * Copyright © 2003 Rick Bronson
3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
6 *
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
9 *
10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 *
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
20 *
21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
30 #include <linux/dma-mapping.h>
31 #include <linux/slab.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/platform_device.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/of_mtd.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/partitions.h>
42
43 #include <linux/delay.h>
44 #include <linux/dmaengine.h>
45 #include <linux/gpio.h>
46 #include <linux/interrupt.h>
47 #include <linux/io.h>
48 #include <linux/platform_data/atmel.h>
49
50 static int use_dma = 1;
51 module_param(use_dma, int, 0);
52
53 static int on_flash_bbt = 0;
54 module_param(on_flash_bbt, int, 0);
55
56 /* Register access macros */
57 #define ecc_readl(add, reg) \
58 __raw_readl(add + ATMEL_ECC_##reg)
59 #define ecc_writel(add, reg, value) \
60 __raw_writel((value), add + ATMEL_ECC_##reg)
61
62 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
63 #include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
64
65 /* oob layout for large page size
66 * bad block info is on bytes 0 and 1
67 * the bytes have to be consecutives to avoid
68 * several NAND_CMD_RNDOUT during read
69 */
70 static struct nand_ecclayout atmel_oobinfo_large = {
71 .eccbytes = 4,
72 .eccpos = {60, 61, 62, 63},
73 .oobfree = {
74 {2, 58}
75 },
76 };
77
78 /* oob layout for small page size
79 * bad block info is on bytes 4 and 5
80 * the bytes have to be consecutives to avoid
81 * several NAND_CMD_RNDOUT during read
82 */
83 static struct nand_ecclayout atmel_oobinfo_small = {
84 .eccbytes = 4,
85 .eccpos = {0, 1, 2, 3},
86 .oobfree = {
87 {6, 10}
88 },
89 };
90
91 struct atmel_nfc {
92 void __iomem *base_cmd_regs;
93 void __iomem *hsmc_regs;
94 void __iomem *sram_bank0;
95 dma_addr_t sram_bank0_phys;
96 bool use_nfc_sram;
97 bool write_by_sram;
98
99 bool is_initialized;
100 struct completion comp_nfc;
101
102 /* Point to the sram bank which include readed data via NFC */
103 void __iomem *data_in_sram;
104 bool will_write_sram;
105 };
106 static struct atmel_nfc nand_nfc;
107
108 struct atmel_nand_host {
109 struct nand_chip nand_chip;
110 struct mtd_info mtd;
111 void __iomem *io_base;
112 dma_addr_t io_phys;
113 struct atmel_nand_data board;
114 struct device *dev;
115 void __iomem *ecc;
116
117 struct completion comp;
118 struct dma_chan *dma_chan;
119
120 struct atmel_nfc *nfc;
121
122 bool has_pmecc;
123 u8 pmecc_corr_cap;
124 u16 pmecc_sector_size;
125 u32 pmecc_lookup_table_offset;
126 u32 pmecc_lookup_table_offset_512;
127 u32 pmecc_lookup_table_offset_1024;
128
129 int pmecc_bytes_per_sector;
130 int pmecc_sector_number;
131 int pmecc_degree; /* Degree of remainders */
132 int pmecc_cw_len; /* Length of codeword */
133
134 void __iomem *pmerrloc_base;
135 void __iomem *pmecc_rom_base;
136
137 /* lookup table for alpha_to and index_of */
138 void __iomem *pmecc_alpha_to;
139 void __iomem *pmecc_index_of;
140
141 /* data for pmecc computation */
142 int16_t *pmecc_partial_syn;
143 int16_t *pmecc_si;
144 int16_t *pmecc_smu; /* Sigma table */
145 int16_t *pmecc_lmu; /* polynomal order */
146 int *pmecc_mu;
147 int *pmecc_dmu;
148 int *pmecc_delta;
149 };
150
151 static struct nand_ecclayout atmel_pmecc_oobinfo;
152
153 /*
154 * Enable NAND.
155 */
156 static void atmel_nand_enable(struct atmel_nand_host *host)
157 {
158 if (gpio_is_valid(host->board.enable_pin))
159 gpio_set_value(host->board.enable_pin, 0);
160 }
161
162 /*
163 * Disable NAND.
164 */
165 static void atmel_nand_disable(struct atmel_nand_host *host)
166 {
167 if (gpio_is_valid(host->board.enable_pin))
168 gpio_set_value(host->board.enable_pin, 1);
169 }
170
171 /*
172 * Hardware specific access to control-lines
173 */
174 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
175 {
176 struct nand_chip *nand_chip = mtd->priv;
177 struct atmel_nand_host *host = nand_chip->priv;
178
179 if (ctrl & NAND_CTRL_CHANGE) {
180 if (ctrl & NAND_NCE)
181 atmel_nand_enable(host);
182 else
183 atmel_nand_disable(host);
184 }
185 if (cmd == NAND_CMD_NONE)
186 return;
187
188 if (ctrl & NAND_CLE)
189 writeb(cmd, host->io_base + (1 << host->board.cle));
190 else
191 writeb(cmd, host->io_base + (1 << host->board.ale));
192 }
193
194 /*
195 * Read the Device Ready pin.
196 */
197 static int atmel_nand_device_ready(struct mtd_info *mtd)
198 {
199 struct nand_chip *nand_chip = mtd->priv;
200 struct atmel_nand_host *host = nand_chip->priv;
201
202 return gpio_get_value(host->board.rdy_pin) ^
203 !!host->board.rdy_pin_active_low;
204 }
205
206 /* Set up for hardware ready pin and enable pin. */
207 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
208 {
209 struct nand_chip *chip = mtd->priv;
210 struct atmel_nand_host *host = chip->priv;
211 int res = 0;
212
213 if (gpio_is_valid(host->board.rdy_pin)) {
214 res = devm_gpio_request(host->dev,
215 host->board.rdy_pin, "nand_rdy");
216 if (res < 0) {
217 dev_err(host->dev,
218 "can't request rdy gpio %d\n",
219 host->board.rdy_pin);
220 return res;
221 }
222
223 res = gpio_direction_input(host->board.rdy_pin);
224 if (res < 0) {
225 dev_err(host->dev,
226 "can't request input direction rdy gpio %d\n",
227 host->board.rdy_pin);
228 return res;
229 }
230
231 chip->dev_ready = atmel_nand_device_ready;
232 }
233
234 if (gpio_is_valid(host->board.enable_pin)) {
235 res = devm_gpio_request(host->dev,
236 host->board.enable_pin, "nand_enable");
237 if (res < 0) {
238 dev_err(host->dev,
239 "can't request enable gpio %d\n",
240 host->board.enable_pin);
241 return res;
242 }
243
244 res = gpio_direction_output(host->board.enable_pin, 1);
245 if (res < 0) {
246 dev_err(host->dev,
247 "can't request output direction enable gpio %d\n",
248 host->board.enable_pin);
249 return res;
250 }
251 }
252
253 return res;
254 }
255
256 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
257 {
258 int i;
259 u32 *t = trg;
260 const __iomem u32 *s = src;
261
262 for (i = 0; i < (size >> 2); i++)
263 *t++ = readl_relaxed(s++);
264 }
265
266 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
267 {
268 int i;
269 u32 __iomem *t = trg;
270 const u32 *s = src;
271
272 for (i = 0; i < (size >> 2); i++)
273 writel_relaxed(*s++, t++);
274 }
275
276 /*
277 * Minimal-overhead PIO for data access.
278 */
279 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
280 {
281 struct nand_chip *nand_chip = mtd->priv;
282 struct atmel_nand_host *host = nand_chip->priv;
283
284 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
285 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
286 host->nfc->data_in_sram += len;
287 } else {
288 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
289 }
290 }
291
292 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
293 {
294 struct nand_chip *nand_chip = mtd->priv;
295 struct atmel_nand_host *host = nand_chip->priv;
296
297 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
298 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
299 host->nfc->data_in_sram += len;
300 } else {
301 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
302 }
303 }
304
305 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
306 {
307 struct nand_chip *nand_chip = mtd->priv;
308
309 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
310 }
311
312 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
313 {
314 struct nand_chip *nand_chip = mtd->priv;
315
316 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
317 }
318
319 static void dma_complete_func(void *completion)
320 {
321 complete(completion);
322 }
323
324 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
325 {
326 /* NFC only has two banks. Must be 0 or 1 */
327 if (bank > 1)
328 return -EINVAL;
329
330 if (bank) {
331 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
332 if (host->mtd.writesize > 2048)
333 return -EINVAL;
334 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
335 } else {
336 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
337 }
338
339 return 0;
340 }
341
342 static uint nfc_get_sram_off(struct atmel_nand_host *host)
343 {
344 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
345 return NFC_SRAM_BANK1_OFFSET;
346 else
347 return 0;
348 }
349
350 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
351 {
352 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
353 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
354 else
355 return host->nfc->sram_bank0_phys;
356 }
357
358 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
359 int is_read)
360 {
361 struct dma_device *dma_dev;
362 enum dma_ctrl_flags flags;
363 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
364 struct dma_async_tx_descriptor *tx = NULL;
365 dma_cookie_t cookie;
366 struct nand_chip *chip = mtd->priv;
367 struct atmel_nand_host *host = chip->priv;
368 void *p = buf;
369 int err = -EIO;
370 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
371 struct atmel_nfc *nfc = host->nfc;
372
373 if (buf >= high_memory)
374 goto err_buf;
375
376 dma_dev = host->dma_chan->device;
377
378 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
379
380 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
381 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
382 dev_err(host->dev, "Failed to dma_map_single\n");
383 goto err_buf;
384 }
385
386 if (is_read) {
387 if (nfc && nfc->data_in_sram)
388 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
389 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
390 else
391 dma_src_addr = host->io_phys;
392
393 dma_dst_addr = phys_addr;
394 } else {
395 dma_src_addr = phys_addr;
396
397 if (nfc && nfc->write_by_sram)
398 dma_dst_addr = nfc_sram_phys(host);
399 else
400 dma_dst_addr = host->io_phys;
401 }
402
403 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
404 dma_src_addr, len, flags);
405 if (!tx) {
406 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
407 goto err_dma;
408 }
409
410 init_completion(&host->comp);
411 tx->callback = dma_complete_func;
412 tx->callback_param = &host->comp;
413
414 cookie = tx->tx_submit(tx);
415 if (dma_submit_error(cookie)) {
416 dev_err(host->dev, "Failed to do DMA tx_submit\n");
417 goto err_dma;
418 }
419
420 dma_async_issue_pending(host->dma_chan);
421 wait_for_completion(&host->comp);
422
423 if (is_read && nfc && nfc->data_in_sram)
424 /* After read data from SRAM, need to increase the position */
425 nfc->data_in_sram += len;
426
427 err = 0;
428
429 err_dma:
430 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
431 err_buf:
432 if (err != 0)
433 dev_warn(host->dev, "Fall back to CPU I/O\n");
434 return err;
435 }
436
437 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
438 {
439 struct nand_chip *chip = mtd->priv;
440 struct atmel_nand_host *host = chip->priv;
441
442 if (use_dma && len > mtd->oobsize)
443 /* only use DMA for bigger than oob size: better performances */
444 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
445 return;
446
447 if (host->board.bus_width_16)
448 atmel_read_buf16(mtd, buf, len);
449 else
450 atmel_read_buf8(mtd, buf, len);
451 }
452
453 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
454 {
455 struct nand_chip *chip = mtd->priv;
456 struct atmel_nand_host *host = chip->priv;
457
458 if (use_dma && len > mtd->oobsize)
459 /* only use DMA for bigger than oob size: better performances */
460 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
461 return;
462
463 if (host->board.bus_width_16)
464 atmel_write_buf16(mtd, buf, len);
465 else
466 atmel_write_buf8(mtd, buf, len);
467 }
468
469 /*
470 * Return number of ecc bytes per sector according to sector size and
471 * correction capability
472 *
473 * Following table shows what at91 PMECC supported:
474 * Correction Capability Sector_512_bytes Sector_1024_bytes
475 * ===================== ================ =================
476 * 2-bits 4-bytes 4-bytes
477 * 4-bits 7-bytes 7-bytes
478 * 8-bits 13-bytes 14-bytes
479 * 12-bits 20-bytes 21-bytes
480 * 24-bits 39-bytes 42-bytes
481 */
482 static int pmecc_get_ecc_bytes(int cap, int sector_size)
483 {
484 int m = 12 + sector_size / 512;
485 return (m * cap + 7) / 8;
486 }
487
488 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
489 int oobsize, int ecc_len)
490 {
491 int i;
492
493 layout->eccbytes = ecc_len;
494
495 /* ECC will occupy the last ecc_len bytes continuously */
496 for (i = 0; i < ecc_len; i++)
497 layout->eccpos[i] = oobsize - ecc_len + i;
498
499 layout->oobfree[0].offset = 2;
500 layout->oobfree[0].length =
501 oobsize - ecc_len - layout->oobfree[0].offset;
502 }
503
504 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
505 {
506 int table_size;
507
508 table_size = host->pmecc_sector_size == 512 ?
509 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
510
511 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
512 table_size * sizeof(int16_t);
513 }
514
515 static int pmecc_data_alloc(struct atmel_nand_host *host)
516 {
517 const int cap = host->pmecc_corr_cap;
518 int size;
519
520 size = (2 * cap + 1) * sizeof(int16_t);
521 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
522 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
523 host->pmecc_lmu = devm_kzalloc(host->dev,
524 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
525 host->pmecc_smu = devm_kzalloc(host->dev,
526 (cap + 2) * size, GFP_KERNEL);
527
528 size = (cap + 1) * sizeof(int);
529 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
530 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
531 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
532
533 if (!host->pmecc_partial_syn ||
534 !host->pmecc_si ||
535 !host->pmecc_lmu ||
536 !host->pmecc_smu ||
537 !host->pmecc_mu ||
538 !host->pmecc_dmu ||
539 !host->pmecc_delta)
540 return -ENOMEM;
541
542 return 0;
543 }
544
545 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
546 {
547 struct nand_chip *nand_chip = mtd->priv;
548 struct atmel_nand_host *host = nand_chip->priv;
549 int i;
550 uint32_t value;
551
552 /* Fill odd syndromes */
553 for (i = 0; i < host->pmecc_corr_cap; i++) {
554 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
555 if (i & 1)
556 value >>= 16;
557 value &= 0xffff;
558 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
559 }
560 }
561
562 static void pmecc_substitute(struct mtd_info *mtd)
563 {
564 struct nand_chip *nand_chip = mtd->priv;
565 struct atmel_nand_host *host = nand_chip->priv;
566 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
567 int16_t __iomem *index_of = host->pmecc_index_of;
568 int16_t *partial_syn = host->pmecc_partial_syn;
569 const int cap = host->pmecc_corr_cap;
570 int16_t *si;
571 int i, j;
572
573 /* si[] is a table that holds the current syndrome value,
574 * an element of that table belongs to the field
575 */
576 si = host->pmecc_si;
577
578 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
579
580 /* Computation 2t syndromes based on S(x) */
581 /* Odd syndromes */
582 for (i = 1; i < 2 * cap; i += 2) {
583 for (j = 0; j < host->pmecc_degree; j++) {
584 if (partial_syn[i] & ((unsigned short)0x1 << j))
585 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
586 }
587 }
588 /* Even syndrome = (Odd syndrome) ** 2 */
589 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
590 if (si[j] == 0) {
591 si[i] = 0;
592 } else {
593 int16_t tmp;
594
595 tmp = readw_relaxed(index_of + si[j]);
596 tmp = (tmp * 2) % host->pmecc_cw_len;
597 si[i] = readw_relaxed(alpha_to + tmp);
598 }
599 }
600
601 return;
602 }
603
604 static void pmecc_get_sigma(struct mtd_info *mtd)
605 {
606 struct nand_chip *nand_chip = mtd->priv;
607 struct atmel_nand_host *host = nand_chip->priv;
608
609 int16_t *lmu = host->pmecc_lmu;
610 int16_t *si = host->pmecc_si;
611 int *mu = host->pmecc_mu;
612 int *dmu = host->pmecc_dmu; /* Discrepancy */
613 int *delta = host->pmecc_delta; /* Delta order */
614 int cw_len = host->pmecc_cw_len;
615 const int16_t cap = host->pmecc_corr_cap;
616 const int num = 2 * cap + 1;
617 int16_t __iomem *index_of = host->pmecc_index_of;
618 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
619 int i, j, k;
620 uint32_t dmu_0_count, tmp;
621 int16_t *smu = host->pmecc_smu;
622
623 /* index of largest delta */
624 int ro;
625 int largest;
626 int diff;
627
628 dmu_0_count = 0;
629
630 /* First Row */
631
632 /* Mu */
633 mu[0] = -1;
634
635 memset(smu, 0, sizeof(int16_t) * num);
636 smu[0] = 1;
637
638 /* discrepancy set to 1 */
639 dmu[0] = 1;
640 /* polynom order set to 0 */
641 lmu[0] = 0;
642 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
643
644 /* Second Row */
645
646 /* Mu */
647 mu[1] = 0;
648 /* Sigma(x) set to 1 */
649 memset(&smu[num], 0, sizeof(int16_t) * num);
650 smu[num] = 1;
651
652 /* discrepancy set to S1 */
653 dmu[1] = si[1];
654
655 /* polynom order set to 0 */
656 lmu[1] = 0;
657
658 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
659
660 /* Init the Sigma(x) last row */
661 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
662
663 for (i = 1; i <= cap; i++) {
664 mu[i + 1] = i << 1;
665 /* Begin Computing Sigma (Mu+1) and L(mu) */
666 /* check if discrepancy is set to 0 */
667 if (dmu[i] == 0) {
668 dmu_0_count++;
669
670 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
671 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
672 tmp += 2;
673 else
674 tmp += 1;
675
676 if (dmu_0_count == tmp) {
677 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
678 smu[(cap + 1) * num + j] =
679 smu[i * num + j];
680
681 lmu[cap + 1] = lmu[i];
682 return;
683 }
684
685 /* copy polynom */
686 for (j = 0; j <= lmu[i] >> 1; j++)
687 smu[(i + 1) * num + j] = smu[i * num + j];
688
689 /* copy previous polynom order to the next */
690 lmu[i + 1] = lmu[i];
691 } else {
692 ro = 0;
693 largest = -1;
694 /* find largest delta with dmu != 0 */
695 for (j = 0; j < i; j++) {
696 if ((dmu[j]) && (delta[j] > largest)) {
697 largest = delta[j];
698 ro = j;
699 }
700 }
701
702 /* compute difference */
703 diff = (mu[i] - mu[ro]);
704
705 /* Compute degree of the new smu polynomial */
706 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
707 lmu[i + 1] = lmu[i];
708 else
709 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
710
711 /* Init smu[i+1] with 0 */
712 for (k = 0; k < num; k++)
713 smu[(i + 1) * num + k] = 0;
714
715 /* Compute smu[i+1] */
716 for (k = 0; k <= lmu[ro] >> 1; k++) {
717 int16_t a, b, c;
718
719 if (!(smu[ro * num + k] && dmu[i]))
720 continue;
721 a = readw_relaxed(index_of + dmu[i]);
722 b = readw_relaxed(index_of + dmu[ro]);
723 c = readw_relaxed(index_of + smu[ro * num + k]);
724 tmp = a + (cw_len - b) + c;
725 a = readw_relaxed(alpha_to + tmp % cw_len);
726 smu[(i + 1) * num + (k + diff)] = a;
727 }
728
729 for (k = 0; k <= lmu[i] >> 1; k++)
730 smu[(i + 1) * num + k] ^= smu[i * num + k];
731 }
732
733 /* End Computing Sigma (Mu+1) and L(mu) */
734 /* In either case compute delta */
735 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
736
737 /* Do not compute discrepancy for the last iteration */
738 if (i >= cap)
739 continue;
740
741 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
742 tmp = 2 * (i - 1);
743 if (k == 0) {
744 dmu[i + 1] = si[tmp + 3];
745 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
746 int16_t a, b, c;
747 a = readw_relaxed(index_of +
748 smu[(i + 1) * num + k]);
749 b = si[2 * (i - 1) + 3 - k];
750 c = readw_relaxed(index_of + b);
751 tmp = a + c;
752 tmp %= cw_len;
753 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
754 dmu[i + 1];
755 }
756 }
757 }
758
759 return;
760 }
761
762 static int pmecc_err_location(struct mtd_info *mtd)
763 {
764 struct nand_chip *nand_chip = mtd->priv;
765 struct atmel_nand_host *host = nand_chip->priv;
766 unsigned long end_time;
767 const int cap = host->pmecc_corr_cap;
768 const int num = 2 * cap + 1;
769 int sector_size = host->pmecc_sector_size;
770 int err_nbr = 0; /* number of error */
771 int roots_nbr; /* number of roots */
772 int i;
773 uint32_t val;
774 int16_t *smu = host->pmecc_smu;
775
776 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
777
778 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
779 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
780 smu[(cap + 1) * num + i]);
781 err_nbr++;
782 }
783
784 val = (err_nbr - 1) << 16;
785 if (sector_size == 1024)
786 val |= 1;
787
788 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
789 pmerrloc_writel(host->pmerrloc_base, ELEN,
790 sector_size * 8 + host->pmecc_degree * cap);
791
792 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
793 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
794 & PMERRLOC_CALC_DONE)) {
795 if (unlikely(time_after(jiffies, end_time))) {
796 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
797 return -1;
798 }
799 cpu_relax();
800 }
801
802 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
803 & PMERRLOC_ERR_NUM_MASK) >> 8;
804 /* Number of roots == degree of smu hence <= cap */
805 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
806 return err_nbr - 1;
807
808 /* Number of roots does not match the degree of smu
809 * unable to correct error */
810 return -1;
811 }
812
813 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
814 int sector_num, int extra_bytes, int err_nbr)
815 {
816 struct nand_chip *nand_chip = mtd->priv;
817 struct atmel_nand_host *host = nand_chip->priv;
818 int i = 0;
819 int byte_pos, bit_pos, sector_size, pos;
820 uint32_t tmp;
821 uint8_t err_byte;
822
823 sector_size = host->pmecc_sector_size;
824
825 while (err_nbr) {
826 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
827 byte_pos = tmp / 8;
828 bit_pos = tmp % 8;
829
830 if (byte_pos >= (sector_size + extra_bytes))
831 BUG(); /* should never happen */
832
833 if (byte_pos < sector_size) {
834 err_byte = *(buf + byte_pos);
835 *(buf + byte_pos) ^= (1 << bit_pos);
836
837 pos = sector_num * host->pmecc_sector_size + byte_pos;
838 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
839 pos, bit_pos, err_byte, *(buf + byte_pos));
840 } else {
841 /* Bit flip in OOB area */
842 tmp = sector_num * host->pmecc_bytes_per_sector
843 + (byte_pos - sector_size);
844 err_byte = ecc[tmp];
845 ecc[tmp] ^= (1 << bit_pos);
846
847 pos = tmp + nand_chip->ecc.layout->eccpos[0];
848 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
849 pos, bit_pos, err_byte, ecc[tmp]);
850 }
851
852 i++;
853 err_nbr--;
854 }
855
856 return;
857 }
858
859 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
860 u8 *ecc)
861 {
862 struct nand_chip *nand_chip = mtd->priv;
863 struct atmel_nand_host *host = nand_chip->priv;
864 int i, err_nbr, eccbytes;
865 uint8_t *buf_pos;
866 int total_err = 0;
867
868 eccbytes = nand_chip->ecc.bytes;
869 for (i = 0; i < eccbytes; i++)
870 if (ecc[i] != 0xff)
871 goto normal_check;
872 /* Erased page, return OK */
873 return 0;
874
875 normal_check:
876 for (i = 0; i < host->pmecc_sector_number; i++) {
877 err_nbr = 0;
878 if (pmecc_stat & 0x1) {
879 buf_pos = buf + i * host->pmecc_sector_size;
880
881 pmecc_gen_syndrome(mtd, i);
882 pmecc_substitute(mtd);
883 pmecc_get_sigma(mtd);
884
885 err_nbr = pmecc_err_location(mtd);
886 if (err_nbr == -1) {
887 dev_err(host->dev, "PMECC: Too many errors\n");
888 mtd->ecc_stats.failed++;
889 return -EIO;
890 } else {
891 pmecc_correct_data(mtd, buf_pos, ecc, i,
892 host->pmecc_bytes_per_sector, err_nbr);
893 mtd->ecc_stats.corrected += err_nbr;
894 total_err += err_nbr;
895 }
896 }
897 pmecc_stat >>= 1;
898 }
899
900 return total_err;
901 }
902
903 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
904 {
905 u32 val;
906
907 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
908 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
909 return;
910 }
911
912 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
913 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
914 val = pmecc_readl_relaxed(host->ecc, CFG);
915
916 if (ecc_op == NAND_ECC_READ)
917 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
918 | PMECC_CFG_AUTO_ENABLE);
919 else
920 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
921 & ~PMECC_CFG_AUTO_ENABLE);
922
923 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
924 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
925 }
926
927 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
928 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
929 {
930 struct atmel_nand_host *host = chip->priv;
931 int eccsize = chip->ecc.size;
932 uint8_t *oob = chip->oob_poi;
933 uint32_t *eccpos = chip->ecc.layout->eccpos;
934 uint32_t stat;
935 unsigned long end_time;
936 int bitflips = 0;
937
938 if (!host->nfc || !host->nfc->use_nfc_sram)
939 pmecc_enable(host, NAND_ECC_READ);
940
941 chip->read_buf(mtd, buf, eccsize);
942 chip->read_buf(mtd, oob, mtd->oobsize);
943
944 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
945 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
946 if (unlikely(time_after(jiffies, end_time))) {
947 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
948 return -EIO;
949 }
950 cpu_relax();
951 }
952
953 stat = pmecc_readl_relaxed(host->ecc, ISR);
954 if (stat != 0) {
955 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
956 if (bitflips < 0)
957 /* uncorrectable errors */
958 return 0;
959 }
960
961 return bitflips;
962 }
963
964 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
965 struct nand_chip *chip, const uint8_t *buf, int oob_required)
966 {
967 struct atmel_nand_host *host = chip->priv;
968 uint32_t *eccpos = chip->ecc.layout->eccpos;
969 int i, j;
970 unsigned long end_time;
971
972 if (!host->nfc || !host->nfc->write_by_sram) {
973 pmecc_enable(host, NAND_ECC_WRITE);
974 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
975 }
976
977 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
978 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
979 if (unlikely(time_after(jiffies, end_time))) {
980 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
981 return -EIO;
982 }
983 cpu_relax();
984 }
985
986 for (i = 0; i < host->pmecc_sector_number; i++) {
987 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
988 int pos;
989
990 pos = i * host->pmecc_bytes_per_sector + j;
991 chip->oob_poi[eccpos[pos]] =
992 pmecc_readb_ecc_relaxed(host->ecc, i, j);
993 }
994 }
995 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
996
997 return 0;
998 }
999
1000 static void atmel_pmecc_core_init(struct mtd_info *mtd)
1001 {
1002 struct nand_chip *nand_chip = mtd->priv;
1003 struct atmel_nand_host *host = nand_chip->priv;
1004 uint32_t val = 0;
1005 struct nand_ecclayout *ecc_layout;
1006
1007 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1008 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1009
1010 switch (host->pmecc_corr_cap) {
1011 case 2:
1012 val = PMECC_CFG_BCH_ERR2;
1013 break;
1014 case 4:
1015 val = PMECC_CFG_BCH_ERR4;
1016 break;
1017 case 8:
1018 val = PMECC_CFG_BCH_ERR8;
1019 break;
1020 case 12:
1021 val = PMECC_CFG_BCH_ERR12;
1022 break;
1023 case 24:
1024 val = PMECC_CFG_BCH_ERR24;
1025 break;
1026 }
1027
1028 if (host->pmecc_sector_size == 512)
1029 val |= PMECC_CFG_SECTOR512;
1030 else if (host->pmecc_sector_size == 1024)
1031 val |= PMECC_CFG_SECTOR1024;
1032
1033 switch (host->pmecc_sector_number) {
1034 case 1:
1035 val |= PMECC_CFG_PAGE_1SECTOR;
1036 break;
1037 case 2:
1038 val |= PMECC_CFG_PAGE_2SECTORS;
1039 break;
1040 case 4:
1041 val |= PMECC_CFG_PAGE_4SECTORS;
1042 break;
1043 case 8:
1044 val |= PMECC_CFG_PAGE_8SECTORS;
1045 break;
1046 }
1047
1048 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1049 | PMECC_CFG_AUTO_DISABLE);
1050 pmecc_writel(host->ecc, CFG, val);
1051
1052 ecc_layout = nand_chip->ecc.layout;
1053 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1054 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1055 pmecc_writel(host->ecc, EADDR,
1056 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1057 /* See datasheet about PMECC Clock Control Register */
1058 pmecc_writel(host->ecc, CLK, 2);
1059 pmecc_writel(host->ecc, IDR, 0xff);
1060 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1061 }
1062
1063 /*
1064 * Get minimum ecc requirements from NAND.
1065 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1066 * will set them according to minimum ecc requirement. Otherwise, use the
1067 * value in DTS file.
1068 * return 0 if success. otherwise return error code.
1069 */
1070 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1071 int *cap, int *sector_size)
1072 {
1073 /* Get minimum ECC requirements */
1074 if (host->nand_chip.ecc_strength_ds) {
1075 *cap = host->nand_chip.ecc_strength_ds;
1076 *sector_size = host->nand_chip.ecc_step_ds;
1077 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1078 *cap, *sector_size);
1079 } else {
1080 *cap = 2;
1081 *sector_size = 512;
1082 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1083 }
1084
1085 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1086 if (host->pmecc_corr_cap == 0) {
1087 /* use the most fitable ecc bits (the near bigger one ) */
1088 if (*cap <= 2)
1089 host->pmecc_corr_cap = 2;
1090 else if (*cap <= 4)
1091 host->pmecc_corr_cap = 4;
1092 else if (*cap <= 8)
1093 host->pmecc_corr_cap = 8;
1094 else if (*cap <= 12)
1095 host->pmecc_corr_cap = 12;
1096 else if (*cap <= 24)
1097 host->pmecc_corr_cap = 24;
1098 else
1099 return -EINVAL;
1100 }
1101 if (host->pmecc_sector_size == 0) {
1102 /* use the most fitable sector size (the near smaller one ) */
1103 if (*sector_size >= 1024)
1104 host->pmecc_sector_size = 1024;
1105 else if (*sector_size >= 512)
1106 host->pmecc_sector_size = 512;
1107 else
1108 return -EINVAL;
1109 }
1110 return 0;
1111 }
1112
1113 static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1114 struct atmel_nand_host *host)
1115 {
1116 struct mtd_info *mtd = &host->mtd;
1117 struct nand_chip *nand_chip = &host->nand_chip;
1118 struct resource *regs, *regs_pmerr, *regs_rom;
1119 int cap, sector_size, err_no;
1120
1121 err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1122 if (err_no) {
1123 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1124 return err_no;
1125 }
1126
1127 if (cap > host->pmecc_corr_cap ||
1128 sector_size != host->pmecc_sector_size)
1129 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1130
1131 cap = host->pmecc_corr_cap;
1132 sector_size = host->pmecc_sector_size;
1133 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1134 host->pmecc_lookup_table_offset_512 :
1135 host->pmecc_lookup_table_offset_1024;
1136
1137 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1138 cap, sector_size);
1139
1140 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1141 if (!regs) {
1142 dev_warn(host->dev,
1143 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1144 nand_chip->ecc.mode = NAND_ECC_SOFT;
1145 return 0;
1146 }
1147
1148 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1149 if (IS_ERR(host->ecc)) {
1150 dev_err(host->dev, "ioremap failed\n");
1151 err_no = PTR_ERR(host->ecc);
1152 goto err;
1153 }
1154
1155 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1156 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1157 if (IS_ERR(host->pmerrloc_base)) {
1158 dev_err(host->dev,
1159 "Can not get I/O resource for PMECC ERRLOC controller!\n");
1160 err_no = PTR_ERR(host->pmerrloc_base);
1161 goto err;
1162 }
1163
1164 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1165 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom);
1166 if (IS_ERR(host->pmecc_rom_base)) {
1167 dev_err(host->dev, "Can not get I/O resource for ROM!\n");
1168 err_no = PTR_ERR(host->pmecc_rom_base);
1169 goto err;
1170 }
1171
1172 /* ECC is calculated for the whole page (1 step) */
1173 nand_chip->ecc.size = mtd->writesize;
1174
1175 /* set ECC page size and oob layout */
1176 switch (mtd->writesize) {
1177 case 2048:
1178 host->pmecc_degree = (sector_size == 512) ?
1179 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1180 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1181 host->pmecc_sector_number = mtd->writesize / sector_size;
1182 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
1183 cap, sector_size);
1184 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1185 host->pmecc_index_of = host->pmecc_rom_base +
1186 host->pmecc_lookup_table_offset;
1187
1188 nand_chip->ecc.steps = 1;
1189 nand_chip->ecc.strength = cap;
1190 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
1191 host->pmecc_sector_number;
1192 if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
1193 dev_err(host->dev, "No room for ECC bytes\n");
1194 err_no = -EINVAL;
1195 goto err;
1196 }
1197 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1198 mtd->oobsize,
1199 nand_chip->ecc.bytes);
1200 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1201 break;
1202 case 512:
1203 case 1024:
1204 case 4096:
1205 /* TODO */
1206 dev_warn(host->dev,
1207 "Unsupported page size for PMECC, use Software ECC\n");
1208 default:
1209 /* page size not handled by HW ECC */
1210 /* switching back to soft ECC */
1211 nand_chip->ecc.mode = NAND_ECC_SOFT;
1212 return 0;
1213 }
1214
1215 /* Allocate data for PMECC computation */
1216 err_no = pmecc_data_alloc(host);
1217 if (err_no) {
1218 dev_err(host->dev,
1219 "Cannot allocate memory for PMECC computation!\n");
1220 goto err;
1221 }
1222
1223 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1224 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1225
1226 atmel_pmecc_core_init(mtd);
1227
1228 return 0;
1229
1230 err:
1231 return err_no;
1232 }
1233
1234 /*
1235 * Calculate HW ECC
1236 *
1237 * function called after a write
1238 *
1239 * mtd: MTD block structure
1240 * dat: raw data (unused)
1241 * ecc_code: buffer for ECC
1242 */
1243 static int atmel_nand_calculate(struct mtd_info *mtd,
1244 const u_char *dat, unsigned char *ecc_code)
1245 {
1246 struct nand_chip *nand_chip = mtd->priv;
1247 struct atmel_nand_host *host = nand_chip->priv;
1248 unsigned int ecc_value;
1249
1250 /* get the first 2 ECC bytes */
1251 ecc_value = ecc_readl(host->ecc, PR);
1252
1253 ecc_code[0] = ecc_value & 0xFF;
1254 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1255
1256 /* get the last 2 ECC bytes */
1257 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1258
1259 ecc_code[2] = ecc_value & 0xFF;
1260 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1261
1262 return 0;
1263 }
1264
1265 /*
1266 * HW ECC read page function
1267 *
1268 * mtd: mtd info structure
1269 * chip: nand chip info structure
1270 * buf: buffer to store read data
1271 * oob_required: caller expects OOB data read to chip->oob_poi
1272 */
1273 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1274 uint8_t *buf, int oob_required, int page)
1275 {
1276 int eccsize = chip->ecc.size;
1277 int eccbytes = chip->ecc.bytes;
1278 uint32_t *eccpos = chip->ecc.layout->eccpos;
1279 uint8_t *p = buf;
1280 uint8_t *oob = chip->oob_poi;
1281 uint8_t *ecc_pos;
1282 int stat;
1283 unsigned int max_bitflips = 0;
1284
1285 /*
1286 * Errata: ALE is incorrectly wired up to the ECC controller
1287 * on the AP7000, so it will include the address cycles in the
1288 * ECC calculation.
1289 *
1290 * Workaround: Reset the parity registers before reading the
1291 * actual data.
1292 */
1293 struct atmel_nand_host *host = chip->priv;
1294 if (host->board.need_reset_workaround)
1295 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1296
1297 /* read the page */
1298 chip->read_buf(mtd, p, eccsize);
1299
1300 /* move to ECC position if needed */
1301 if (eccpos[0] != 0) {
1302 /* This only works on large pages
1303 * because the ECC controller waits for
1304 * NAND_CMD_RNDOUTSTART after the
1305 * NAND_CMD_RNDOUT.
1306 * anyway, for small pages, the eccpos[0] == 0
1307 */
1308 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1309 mtd->writesize + eccpos[0], -1);
1310 }
1311
1312 /* the ECC controller needs to read the ECC just after the data */
1313 ecc_pos = oob + eccpos[0];
1314 chip->read_buf(mtd, ecc_pos, eccbytes);
1315
1316 /* check if there's an error */
1317 stat = chip->ecc.correct(mtd, p, oob, NULL);
1318
1319 if (stat < 0) {
1320 mtd->ecc_stats.failed++;
1321 } else {
1322 mtd->ecc_stats.corrected += stat;
1323 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1324 }
1325
1326 /* get back to oob start (end of page) */
1327 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1328
1329 /* read the oob */
1330 chip->read_buf(mtd, oob, mtd->oobsize);
1331
1332 return max_bitflips;
1333 }
1334
1335 /*
1336 * HW ECC Correction
1337 *
1338 * function called after a read
1339 *
1340 * mtd: MTD block structure
1341 * dat: raw data read from the chip
1342 * read_ecc: ECC from the chip (unused)
1343 * isnull: unused
1344 *
1345 * Detect and correct a 1 bit error for a page
1346 */
1347 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1348 u_char *read_ecc, u_char *isnull)
1349 {
1350 struct nand_chip *nand_chip = mtd->priv;
1351 struct atmel_nand_host *host = nand_chip->priv;
1352 unsigned int ecc_status;
1353 unsigned int ecc_word, ecc_bit;
1354
1355 /* get the status from the Status Register */
1356 ecc_status = ecc_readl(host->ecc, SR);
1357
1358 /* if there's no error */
1359 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1360 return 0;
1361
1362 /* get error bit offset (4 bits) */
1363 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1364 /* get word address (12 bits) */
1365 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1366 ecc_word >>= 4;
1367
1368 /* if there are multiple errors */
1369 if (ecc_status & ATMEL_ECC_MULERR) {
1370 /* check if it is a freshly erased block
1371 * (filled with 0xff) */
1372 if ((ecc_bit == ATMEL_ECC_BITADDR)
1373 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1374 /* the block has just been erased, return OK */
1375 return 0;
1376 }
1377 /* it doesn't seems to be a freshly
1378 * erased block.
1379 * We can't correct so many errors */
1380 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1381 " Unable to correct.\n");
1382 return -EIO;
1383 }
1384
1385 /* if there's a single bit error : we can correct it */
1386 if (ecc_status & ATMEL_ECC_ECCERR) {
1387 /* there's nothing much to do here.
1388 * the bit error is on the ECC itself.
1389 */
1390 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1391 " Nothing to correct\n");
1392 return 0;
1393 }
1394
1395 dev_dbg(host->dev, "atmel_nand : one bit error on data."
1396 " (word offset in the page :"
1397 " 0x%x bit offset : 0x%x)\n",
1398 ecc_word, ecc_bit);
1399 /* correct the error */
1400 if (nand_chip->options & NAND_BUSWIDTH_16) {
1401 /* 16 bits words */
1402 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1403 } else {
1404 /* 8 bits words */
1405 dat[ecc_word] ^= (1 << ecc_bit);
1406 }
1407 dev_dbg(host->dev, "atmel_nand : error corrected\n");
1408 return 1;
1409 }
1410
1411 /*
1412 * Enable HW ECC : unused on most chips
1413 */
1414 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1415 {
1416 struct nand_chip *nand_chip = mtd->priv;
1417 struct atmel_nand_host *host = nand_chip->priv;
1418
1419 if (host->board.need_reset_workaround)
1420 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1421 }
1422
1423 static int atmel_of_init_port(struct atmel_nand_host *host,
1424 struct device_node *np)
1425 {
1426 u32 val;
1427 u32 offset[2];
1428 int ecc_mode;
1429 struct atmel_nand_data *board = &host->board;
1430 enum of_gpio_flags flags = 0;
1431
1432 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1433 if (val >= 32) {
1434 dev_err(host->dev, "invalid addr-offset %u\n", val);
1435 return -EINVAL;
1436 }
1437 board->ale = val;
1438 }
1439
1440 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1441 if (val >= 32) {
1442 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1443 return -EINVAL;
1444 }
1445 board->cle = val;
1446 }
1447
1448 ecc_mode = of_get_nand_ecc_mode(np);
1449
1450 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1451
1452 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1453
1454 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1455
1456 if (of_get_nand_bus_width(np) == 16)
1457 board->bus_width_16 = 1;
1458
1459 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1460 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1461
1462 board->enable_pin = of_get_gpio(np, 1);
1463 board->det_pin = of_get_gpio(np, 2);
1464
1465 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1466
1467 /* load the nfc driver if there is */
1468 of_platform_populate(np, NULL, NULL, host->dev);
1469
1470 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1471 return 0; /* Not using PMECC */
1472
1473 /* use PMECC, get correction capability, sector size and lookup
1474 * table offset.
1475 * If correction bits and sector size are not specified, then find
1476 * them from NAND ONFI parameters.
1477 */
1478 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1479 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1480 (val != 24)) {
1481 dev_err(host->dev,
1482 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1483 val);
1484 return -EINVAL;
1485 }
1486 host->pmecc_corr_cap = (u8)val;
1487 }
1488
1489 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1490 if ((val != 512) && (val != 1024)) {
1491 dev_err(host->dev,
1492 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1493 val);
1494 return -EINVAL;
1495 }
1496 host->pmecc_sector_size = (u16)val;
1497 }
1498
1499 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1500 offset, 2) != 0) {
1501 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1502 return -EINVAL;
1503 }
1504 if (!offset[0] && !offset[1]) {
1505 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1506 return -EINVAL;
1507 }
1508 host->pmecc_lookup_table_offset_512 = offset[0];
1509 host->pmecc_lookup_table_offset_1024 = offset[1];
1510
1511 return 0;
1512 }
1513
1514 static int atmel_hw_nand_init_params(struct platform_device *pdev,
1515 struct atmel_nand_host *host)
1516 {
1517 struct mtd_info *mtd = &host->mtd;
1518 struct nand_chip *nand_chip = &host->nand_chip;
1519 struct resource *regs;
1520
1521 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1522 if (!regs) {
1523 dev_err(host->dev,
1524 "Can't get I/O resource regs, use software ECC\n");
1525 nand_chip->ecc.mode = NAND_ECC_SOFT;
1526 return 0;
1527 }
1528
1529 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1530 if (IS_ERR(host->ecc)) {
1531 dev_err(host->dev, "ioremap failed\n");
1532 return PTR_ERR(host->ecc);
1533 }
1534
1535 /* ECC is calculated for the whole page (1 step) */
1536 nand_chip->ecc.size = mtd->writesize;
1537
1538 /* set ECC page size and oob layout */
1539 switch (mtd->writesize) {
1540 case 512:
1541 nand_chip->ecc.layout = &atmel_oobinfo_small;
1542 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1543 break;
1544 case 1024:
1545 nand_chip->ecc.layout = &atmel_oobinfo_large;
1546 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1547 break;
1548 case 2048:
1549 nand_chip->ecc.layout = &atmel_oobinfo_large;
1550 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1551 break;
1552 case 4096:
1553 nand_chip->ecc.layout = &atmel_oobinfo_large;
1554 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1555 break;
1556 default:
1557 /* page size not handled by HW ECC */
1558 /* switching back to soft ECC */
1559 nand_chip->ecc.mode = NAND_ECC_SOFT;
1560 return 0;
1561 }
1562
1563 /* set up for HW ECC */
1564 nand_chip->ecc.calculate = atmel_nand_calculate;
1565 nand_chip->ecc.correct = atmel_nand_correct;
1566 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1567 nand_chip->ecc.read_page = atmel_nand_read_page;
1568 nand_chip->ecc.bytes = 4;
1569 nand_chip->ecc.strength = 1;
1570
1571 return 0;
1572 }
1573
1574 /* SMC interrupt service routine */
1575 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1576 {
1577 struct atmel_nand_host *host = dev_id;
1578 u32 status, mask, pending;
1579 irqreturn_t ret = IRQ_HANDLED;
1580
1581 status = nfc_readl(host->nfc->hsmc_regs, SR);
1582 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1583 pending = status & mask;
1584
1585 if (pending & NFC_SR_XFR_DONE) {
1586 complete(&host->nfc->comp_nfc);
1587 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1588 } else if (pending & NFC_SR_RB_EDGE) {
1589 complete(&host->nfc->comp_nfc);
1590 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1591 } else if (pending & NFC_SR_CMD_DONE) {
1592 complete(&host->nfc->comp_nfc);
1593 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1594 } else {
1595 ret = IRQ_NONE;
1596 }
1597
1598 return ret;
1599 }
1600
1601 /* NFC(Nand Flash Controller) related functions */
1602 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1603 {
1604 unsigned long timeout;
1605 init_completion(&host->nfc->comp_nfc);
1606
1607 /* Enable interrupt that need to wait for */
1608 nfc_writel(host->nfc->hsmc_regs, IER, flag);
1609
1610 timeout = wait_for_completion_timeout(&host->nfc->comp_nfc,
1611 msecs_to_jiffies(NFC_TIME_OUT_MS));
1612 if (timeout)
1613 return 0;
1614
1615 /* Time out to wait for the interrupt */
1616 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1617 return -ETIMEDOUT;
1618 }
1619
1620 static int nfc_send_command(struct atmel_nand_host *host,
1621 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1622 {
1623 unsigned long timeout;
1624 dev_dbg(host->dev,
1625 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1626 cmd, addr, cycle0);
1627
1628 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1629 while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs)
1630 & NFCADDR_CMD_NFCBUSY) {
1631 if (time_after(jiffies, timeout)) {
1632 dev_err(host->dev,
1633 "Time out to wait CMD_NFCBUSY ready!\n");
1634 return -ETIMEDOUT;
1635 }
1636 }
1637 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1638 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1639 return nfc_wait_interrupt(host, NFC_SR_CMD_DONE);
1640 }
1641
1642 static int nfc_device_ready(struct mtd_info *mtd)
1643 {
1644 struct nand_chip *nand_chip = mtd->priv;
1645 struct atmel_nand_host *host = nand_chip->priv;
1646 if (!nfc_wait_interrupt(host, NFC_SR_RB_EDGE))
1647 return 1;
1648 return 0;
1649 }
1650
1651 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1652 {
1653 struct nand_chip *nand_chip = mtd->priv;
1654 struct atmel_nand_host *host = nand_chip->priv;
1655
1656 if (chip == -1)
1657 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1658 else
1659 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1660 }
1661
1662 static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr,
1663 unsigned int *addr1234, unsigned int *cycle0)
1664 {
1665 struct nand_chip *chip = mtd->priv;
1666
1667 int acycle = 0;
1668 unsigned char addr_bytes[8];
1669 int index = 0, bit_shift;
1670
1671 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1672
1673 *cycle0 = 0;
1674 *addr1234 = 0;
1675
1676 if (column != -1) {
1677 if (chip->options & NAND_BUSWIDTH_16)
1678 column >>= 1;
1679 addr_bytes[acycle++] = column & 0xff;
1680 if (mtd->writesize > 512)
1681 addr_bytes[acycle++] = (column >> 8) & 0xff;
1682 }
1683
1684 if (page_addr != -1) {
1685 addr_bytes[acycle++] = page_addr & 0xff;
1686 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1687 if (chip->chipsize > (128 << 20))
1688 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1689 }
1690
1691 if (acycle > 4)
1692 *cycle0 = addr_bytes[index++];
1693
1694 for (bit_shift = 0; index < acycle; bit_shift += 8)
1695 *addr1234 += addr_bytes[index++] << bit_shift;
1696
1697 /* return acycle in cmd register */
1698 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1699 }
1700
1701 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1702 int column, int page_addr)
1703 {
1704 struct nand_chip *chip = mtd->priv;
1705 struct atmel_nand_host *host = chip->priv;
1706 unsigned long timeout;
1707 unsigned int nfc_addr_cmd = 0;
1708
1709 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1710
1711 /* Set default settings: no cmd2, no addr cycle. read from nand */
1712 unsigned int cmd2 = 0;
1713 unsigned int vcmd2 = 0;
1714 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1715 int csid = NFCADDR_CMD_CSID_3;
1716 int dataen = NFCADDR_CMD_DATADIS;
1717 int nfcwr = NFCADDR_CMD_NFCRD;
1718 unsigned int addr1234 = 0;
1719 unsigned int cycle0 = 0;
1720 bool do_addr = true;
1721 host->nfc->data_in_sram = NULL;
1722
1723 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1724 __func__, command, column, page_addr);
1725
1726 switch (command) {
1727 case NAND_CMD_RESET:
1728 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1729 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1730 udelay(chip->chip_delay);
1731
1732 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1733 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1734 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1735 if (time_after(jiffies, timeout)) {
1736 dev_err(host->dev,
1737 "Time out to wait status ready!\n");
1738 break;
1739 }
1740 }
1741 return;
1742 case NAND_CMD_STATUS:
1743 do_addr = false;
1744 break;
1745 case NAND_CMD_PARAM:
1746 case NAND_CMD_READID:
1747 do_addr = false;
1748 acycle = NFCADDR_CMD_ACYCLE_1;
1749 if (column != -1)
1750 addr1234 = column;
1751 break;
1752 case NAND_CMD_RNDOUT:
1753 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1754 vcmd2 = NFCADDR_CMD_VCMD2;
1755 break;
1756 case NAND_CMD_READ0:
1757 case NAND_CMD_READOOB:
1758 if (command == NAND_CMD_READOOB) {
1759 column += mtd->writesize;
1760 command = NAND_CMD_READ0; /* only READ0 is valid */
1761 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1762 }
1763 if (host->nfc->use_nfc_sram) {
1764 /* Enable Data transfer to sram */
1765 dataen = NFCADDR_CMD_DATAEN;
1766
1767 /* Need enable PMECC now, since NFC will transfer
1768 * data in bus after sending nfc read command.
1769 */
1770 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1771 pmecc_enable(host, NAND_ECC_READ);
1772 }
1773
1774 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1775 vcmd2 = NFCADDR_CMD_VCMD2;
1776 break;
1777 /* For prgramming command, the cmd need set to write enable */
1778 case NAND_CMD_PAGEPROG:
1779 case NAND_CMD_SEQIN:
1780 case NAND_CMD_RNDIN:
1781 nfcwr = NFCADDR_CMD_NFCWR;
1782 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1783 dataen = NFCADDR_CMD_DATAEN;
1784 break;
1785 default:
1786 break;
1787 }
1788
1789 if (do_addr)
1790 acycle = nfc_make_addr(mtd, column, page_addr, &addr1234,
1791 &cycle0);
1792
1793 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1794 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1795
1796 if (dataen == NFCADDR_CMD_DATAEN)
1797 if (nfc_wait_interrupt(host, NFC_SR_XFR_DONE))
1798 dev_err(host->dev, "something wrong, No XFR_DONE interrupt comes.\n");
1799
1800 /*
1801 * Program and erase have their own busy handlers status, sequential
1802 * in, and deplete1 need no delay.
1803 */
1804 switch (command) {
1805 case NAND_CMD_CACHEDPROG:
1806 case NAND_CMD_PAGEPROG:
1807 case NAND_CMD_ERASE1:
1808 case NAND_CMD_ERASE2:
1809 case NAND_CMD_RNDIN:
1810 case NAND_CMD_STATUS:
1811 case NAND_CMD_RNDOUT:
1812 case NAND_CMD_SEQIN:
1813 case NAND_CMD_READID:
1814 return;
1815
1816 case NAND_CMD_READ0:
1817 if (dataen == NFCADDR_CMD_DATAEN) {
1818 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1819 nfc_get_sram_off(host);
1820 return;
1821 }
1822 /* fall through */
1823 default:
1824 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1825 }
1826 }
1827
1828 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1829 uint32_t offset, int data_len, const uint8_t *buf,
1830 int oob_required, int page, int cached, int raw)
1831 {
1832 int cfg, len;
1833 int status = 0;
1834 struct atmel_nand_host *host = chip->priv;
1835 void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1836
1837 /* Subpage write is not supported */
1838 if (offset || (data_len < mtd->writesize))
1839 return -EINVAL;
1840
1841 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1842 len = mtd->writesize;
1843
1844 if (unlikely(raw)) {
1845 len += mtd->oobsize;
1846 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1847 } else
1848 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1849
1850 /* Copy page data to sram that will write to nand via NFC */
1851 if (use_dma) {
1852 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1853 /* Fall back to use cpu copy */
1854 memcpy32_toio(sram, buf, len);
1855 } else {
1856 memcpy32_toio(sram, buf, len);
1857 }
1858
1859 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1860 /*
1861 * When use NFC sram, need set up PMECC before send
1862 * NAND_CMD_SEQIN command. Since when the nand command
1863 * is sent, nfc will do transfer from sram and nand.
1864 */
1865 pmecc_enable(host, NAND_ECC_WRITE);
1866
1867 host->nfc->will_write_sram = true;
1868 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1869 host->nfc->will_write_sram = false;
1870
1871 if (likely(!raw))
1872 /* Need to write ecc into oob */
1873 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1874
1875 if (status < 0)
1876 return status;
1877
1878 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1879 status = chip->waitfunc(mtd, chip);
1880
1881 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1882 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
1883
1884 if (status & NAND_STATUS_FAIL)
1885 return -EIO;
1886
1887 return 0;
1888 }
1889
1890 static int nfc_sram_init(struct mtd_info *mtd)
1891 {
1892 struct nand_chip *chip = mtd->priv;
1893 struct atmel_nand_host *host = chip->priv;
1894 int res = 0;
1895
1896 /* Initialize the NFC CFG register */
1897 unsigned int cfg_nfc = 0;
1898
1899 /* set page size and oob layout */
1900 switch (mtd->writesize) {
1901 case 512:
1902 cfg_nfc = NFC_CFG_PAGESIZE_512;
1903 break;
1904 case 1024:
1905 cfg_nfc = NFC_CFG_PAGESIZE_1024;
1906 break;
1907 case 2048:
1908 cfg_nfc = NFC_CFG_PAGESIZE_2048;
1909 break;
1910 case 4096:
1911 cfg_nfc = NFC_CFG_PAGESIZE_4096;
1912 break;
1913 case 8192:
1914 cfg_nfc = NFC_CFG_PAGESIZE_8192;
1915 break;
1916 default:
1917 dev_err(host->dev, "Unsupported page size for NFC.\n");
1918 res = -ENXIO;
1919 return res;
1920 }
1921
1922 /* oob bytes size = (NFCSPARESIZE + 1) * 4
1923 * Max support spare size is 512 bytes. */
1924 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
1925 & NFC_CFG_NFC_SPARESIZE);
1926 /* default set a max timeout */
1927 cfg_nfc |= NFC_CFG_RSPARE |
1928 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
1929
1930 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
1931
1932 host->nfc->will_write_sram = false;
1933 nfc_set_sram_bank(host, 0);
1934
1935 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
1936 if (host->nfc->write_by_sram) {
1937 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
1938 chip->ecc.mode == NAND_ECC_NONE)
1939 chip->write_page = nfc_sram_write_page;
1940 else
1941 host->nfc->write_by_sram = false;
1942 }
1943
1944 dev_info(host->dev, "Using NFC Sram read %s\n",
1945 host->nfc->write_by_sram ? "and write" : "");
1946 return 0;
1947 }
1948
1949 static struct platform_driver atmel_nand_nfc_driver;
1950 /*
1951 * Probe for the NAND device.
1952 */
1953 static int atmel_nand_probe(struct platform_device *pdev)
1954 {
1955 struct atmel_nand_host *host;
1956 struct mtd_info *mtd;
1957 struct nand_chip *nand_chip;
1958 struct resource *mem;
1959 struct mtd_part_parser_data ppdata = {};
1960 int res, irq;
1961
1962 /* Allocate memory for the device structure (and zero it) */
1963 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1964 if (!host)
1965 return -ENOMEM;
1966
1967 res = platform_driver_register(&atmel_nand_nfc_driver);
1968 if (res)
1969 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
1970
1971 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1972 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
1973 if (IS_ERR(host->io_base)) {
1974 dev_err(&pdev->dev, "atmel_nand: ioremap resource failed\n");
1975 res = PTR_ERR(host->io_base);
1976 goto err_nand_ioremap;
1977 }
1978 host->io_phys = (dma_addr_t)mem->start;
1979
1980 mtd = &host->mtd;
1981 nand_chip = &host->nand_chip;
1982 host->dev = &pdev->dev;
1983 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
1984 /* Only when CONFIG_OF is enabled of_node can be parsed */
1985 res = atmel_of_init_port(host, pdev->dev.of_node);
1986 if (res)
1987 goto err_nand_ioremap;
1988 } else {
1989 memcpy(&host->board, dev_get_platdata(&pdev->dev),
1990 sizeof(struct atmel_nand_data));
1991 }
1992
1993 nand_chip->priv = host; /* link the private data structures */
1994 mtd->priv = nand_chip;
1995 mtd->owner = THIS_MODULE;
1996
1997 /* Set address of NAND IO lines */
1998 nand_chip->IO_ADDR_R = host->io_base;
1999 nand_chip->IO_ADDR_W = host->io_base;
2000
2001 if (nand_nfc.is_initialized) {
2002 /* NFC driver is probed and initialized */
2003 host->nfc = &nand_nfc;
2004
2005 nand_chip->select_chip = nfc_select_chip;
2006 nand_chip->dev_ready = nfc_device_ready;
2007 nand_chip->cmdfunc = nfc_nand_command;
2008
2009 /* Initialize the interrupt for NFC */
2010 irq = platform_get_irq(pdev, 0);
2011 if (irq < 0) {
2012 dev_err(host->dev, "Cannot get HSMC irq!\n");
2013 res = irq;
2014 goto err_nand_ioremap;
2015 }
2016
2017 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2018 0, "hsmc", host);
2019 if (res) {
2020 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2021 irq);
2022 goto err_nand_ioremap;
2023 }
2024 } else {
2025 res = atmel_nand_set_enable_ready_pins(mtd);
2026 if (res)
2027 goto err_nand_ioremap;
2028
2029 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2030 }
2031
2032 nand_chip->ecc.mode = host->board.ecc_mode;
2033 nand_chip->chip_delay = 20; /* 20us command delay time */
2034
2035 if (host->board.bus_width_16) /* 16-bit bus width */
2036 nand_chip->options |= NAND_BUSWIDTH_16;
2037
2038 nand_chip->read_buf = atmel_read_buf;
2039 nand_chip->write_buf = atmel_write_buf;
2040
2041 platform_set_drvdata(pdev, host);
2042 atmel_nand_enable(host);
2043
2044 if (gpio_is_valid(host->board.det_pin)) {
2045 res = devm_gpio_request(&pdev->dev,
2046 host->board.det_pin, "nand_det");
2047 if (res < 0) {
2048 dev_err(&pdev->dev,
2049 "can't request det gpio %d\n",
2050 host->board.det_pin);
2051 goto err_no_card;
2052 }
2053
2054 res = gpio_direction_input(host->board.det_pin);
2055 if (res < 0) {
2056 dev_err(&pdev->dev,
2057 "can't request input direction det gpio %d\n",
2058 host->board.det_pin);
2059 goto err_no_card;
2060 }
2061
2062 if (gpio_get_value(host->board.det_pin)) {
2063 dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2064 res = -ENXIO;
2065 goto err_no_card;
2066 }
2067 }
2068
2069 if (host->board.on_flash_bbt || on_flash_bbt) {
2070 dev_info(&pdev->dev, "Use On Flash BBT\n");
2071 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2072 }
2073
2074 if (!host->board.has_dma)
2075 use_dma = 0;
2076
2077 if (use_dma) {
2078 dma_cap_mask_t mask;
2079
2080 dma_cap_zero(mask);
2081 dma_cap_set(DMA_MEMCPY, mask);
2082 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2083 if (!host->dma_chan) {
2084 dev_err(host->dev, "Failed to request DMA channel\n");
2085 use_dma = 0;
2086 }
2087 }
2088 if (use_dma)
2089 dev_info(host->dev, "Using %s for DMA transfers.\n",
2090 dma_chan_name(host->dma_chan));
2091 else
2092 dev_info(host->dev, "No DMA support for NAND access.\n");
2093
2094 /* first scan to find the device and get the page size */
2095 if (nand_scan_ident(mtd, 1, NULL)) {
2096 res = -ENXIO;
2097 goto err_scan_ident;
2098 }
2099
2100 if (nand_chip->ecc.mode == NAND_ECC_HW) {
2101 if (host->has_pmecc)
2102 res = atmel_pmecc_nand_init_params(pdev, host);
2103 else
2104 res = atmel_hw_nand_init_params(pdev, host);
2105
2106 if (res != 0)
2107 goto err_hw_ecc;
2108 }
2109
2110 /* initialize the nfc configuration register */
2111 if (host->nfc && host->nfc->use_nfc_sram) {
2112 res = nfc_sram_init(mtd);
2113 if (res) {
2114 host->nfc->use_nfc_sram = false;
2115 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2116 }
2117 }
2118
2119 /* second phase scan */
2120 if (nand_scan_tail(mtd)) {
2121 res = -ENXIO;
2122 goto err_scan_tail;
2123 }
2124
2125 mtd->name = "atmel_nand";
2126 ppdata.of_node = pdev->dev.of_node;
2127 res = mtd_device_parse_register(mtd, NULL, &ppdata,
2128 host->board.parts, host->board.num_parts);
2129 if (!res)
2130 return res;
2131
2132 err_scan_tail:
2133 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2134 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2135 err_hw_ecc:
2136 err_scan_ident:
2137 err_no_card:
2138 atmel_nand_disable(host);
2139 if (host->dma_chan)
2140 dma_release_channel(host->dma_chan);
2141 err_nand_ioremap:
2142 return res;
2143 }
2144
2145 /*
2146 * Remove a NAND device.
2147 */
2148 static int atmel_nand_remove(struct platform_device *pdev)
2149 {
2150 struct atmel_nand_host *host = platform_get_drvdata(pdev);
2151 struct mtd_info *mtd = &host->mtd;
2152
2153 nand_release(mtd);
2154
2155 atmel_nand_disable(host);
2156
2157 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2158 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2159 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2160 PMERRLOC_DISABLE);
2161 }
2162
2163 if (host->dma_chan)
2164 dma_release_channel(host->dma_chan);
2165
2166 platform_driver_unregister(&atmel_nand_nfc_driver);
2167
2168 return 0;
2169 }
2170
2171 static const struct of_device_id atmel_nand_dt_ids[] = {
2172 { .compatible = "atmel,at91rm9200-nand" },
2173 { /* sentinel */ }
2174 };
2175
2176 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2177
2178 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2179 {
2180 struct atmel_nfc *nfc = &nand_nfc;
2181 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2182
2183 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2184 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2185 if (IS_ERR(nfc->base_cmd_regs))
2186 return PTR_ERR(nfc->base_cmd_regs);
2187
2188 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2189 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2190 if (IS_ERR(nfc->hsmc_regs))
2191 return PTR_ERR(nfc->hsmc_regs);
2192
2193 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2194 if (nfc_sram) {
2195 nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
2196 if (IS_ERR(nfc->sram_bank0)) {
2197 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2198 PTR_ERR(nfc->sram_bank0));
2199 } else {
2200 nfc->use_nfc_sram = true;
2201 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2202
2203 if (pdev->dev.of_node)
2204 nfc->write_by_sram = of_property_read_bool(
2205 pdev->dev.of_node,
2206 "atmel,write-by-sram");
2207 }
2208 }
2209
2210 nfc->is_initialized = true;
2211 dev_info(&pdev->dev, "NFC is probed.\n");
2212 return 0;
2213 }
2214
2215 static const struct of_device_id atmel_nand_nfc_match[] = {
2216 { .compatible = "atmel,sama5d3-nfc" },
2217 { /* sentinel */ }
2218 };
2219 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2220
2221 static struct platform_driver atmel_nand_nfc_driver = {
2222 .driver = {
2223 .name = "atmel_nand_nfc",
2224 .owner = THIS_MODULE,
2225 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2226 },
2227 .probe = atmel_nand_nfc_probe,
2228 };
2229
2230 static struct platform_driver atmel_nand_driver = {
2231 .probe = atmel_nand_probe,
2232 .remove = atmel_nand_remove,
2233 .driver = {
2234 .name = "atmel_nand",
2235 .owner = THIS_MODULE,
2236 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2237 },
2238 };
2239
2240 module_platform_driver(atmel_nand_driver);
2241
2242 MODULE_LICENSE("GPL");
2243 MODULE_AUTHOR("Rick Bronson");
2244 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2245 MODULE_ALIAS("platform:atmel_nand");
Linux with added FPC-III support