?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / can / mcp251x.c
blobcdb9808d12dbc9883250ccceb5ac156be6a4c84d
1 /*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see <http://www.gnu.org/licenses/>.
32 *
33 *
34 *
35 * Your platform definition file should specify something like:
36 *
37 * static struct mcp251x_platform_data mcp251x_info = {
38 * .oscillator_frequency = 8000000,
39 * };
40 *
41 * static struct spi_board_info spi_board_info[] = {
42 * {
43 * .modalias = "mcp2510",
44 * // or "mcp2515" depending on your controller
45 * .platform_data = &mcp251x_info,
46 * .irq = IRQ_EINT13,
47 * .max_speed_hz = 2*1000*1000,
48 * .chip_select = 2,
49 * },
50 * };
51 *
52 * Please see mcp251x.h for a description of the fields in
53 * struct mcp251x_platform_data.
54 *
55 */
56
57 #include <linux/can/core.h>
58 #include <linux/can/dev.h>
59 #include <linux/can/led.h>
60 #include <linux/can/platform/mcp251x.h>
61 #include <linux/clk.h>
62 #include <linux/completion.h>
63 #include <linux/delay.h>
64 #include <linux/device.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/freezer.h>
67 #include <linux/interrupt.h>
68 #include <linux/io.h>
69 #include <linux/kernel.h>
70 #include <linux/module.h>
71 #include <linux/netdevice.h>
72 #include <linux/of.h>
73 #include <linux/of_device.h>
74 #include <linux/platform_device.h>
75 #include <linux/slab.h>
76 #include <linux/spi/spi.h>
77 #include <linux/uaccess.h>
78 #include <linux/regulator/consumer.h>
79
80 /* SPI interface instruction set */
81 #define INSTRUCTION_WRITE 0x02
82 #define INSTRUCTION_READ 0x03
83 #define INSTRUCTION_BIT_MODIFY 0x05
84 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
85 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
86 #define INSTRUCTION_RESET 0xC0
87 #define RTS_TXB0 0x01
88 #define RTS_TXB1 0x02
89 #define RTS_TXB2 0x04
90 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
91
92
93 /* MPC251x registers */
94 #define CANSTAT 0x0e
95 #define CANCTRL 0x0f
96 # define CANCTRL_REQOP_MASK 0xe0
97 # define CANCTRL_REQOP_CONF 0x80
98 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
99 # define CANCTRL_REQOP_LOOPBACK 0x40
100 # define CANCTRL_REQOP_SLEEP 0x20
101 # define CANCTRL_REQOP_NORMAL 0x00
102 # define CANCTRL_OSM 0x08
103 # define CANCTRL_ABAT 0x10
104 #define TEC 0x1c
105 #define REC 0x1d
106 #define CNF1 0x2a
107 # define CNF1_SJW_SHIFT 6
108 #define CNF2 0x29
109 # define CNF2_BTLMODE 0x80
110 # define CNF2_SAM 0x40
111 # define CNF2_PS1_SHIFT 3
112 #define CNF3 0x28
113 # define CNF3_SOF 0x08
114 # define CNF3_WAKFIL 0x04
115 # define CNF3_PHSEG2_MASK 0x07
116 #define CANINTE 0x2b
117 # define CANINTE_MERRE 0x80
118 # define CANINTE_WAKIE 0x40
119 # define CANINTE_ERRIE 0x20
120 # define CANINTE_TX2IE 0x10
121 # define CANINTE_TX1IE 0x08
122 # define CANINTE_TX0IE 0x04
123 # define CANINTE_RX1IE 0x02
124 # define CANINTE_RX0IE 0x01
125 #define CANINTF 0x2c
126 # define CANINTF_MERRF 0x80
127 # define CANINTF_WAKIF 0x40
128 # define CANINTF_ERRIF 0x20
129 # define CANINTF_TX2IF 0x10
130 # define CANINTF_TX1IF 0x08
131 # define CANINTF_TX0IF 0x04
132 # define CANINTF_RX1IF 0x02
133 # define CANINTF_RX0IF 0x01
134 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
135 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
136 # define CANINTF_ERR (CANINTF_ERRIF)
137 #define EFLG 0x2d
138 # define EFLG_EWARN 0x01
139 # define EFLG_RXWAR 0x02
140 # define EFLG_TXWAR 0x04
141 # define EFLG_RXEP 0x08
142 # define EFLG_TXEP 0x10
143 # define EFLG_TXBO 0x20
144 # define EFLG_RX0OVR 0x40
145 # define EFLG_RX1OVR 0x80
146 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
147 # define TXBCTRL_ABTF 0x40
148 # define TXBCTRL_MLOA 0x20
149 # define TXBCTRL_TXERR 0x10
150 # define TXBCTRL_TXREQ 0x08
151 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
152 # define SIDH_SHIFT 3
153 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
154 # define SIDL_SID_MASK 7
155 # define SIDL_SID_SHIFT 5
156 # define SIDL_EXIDE_SHIFT 3
157 # define SIDL_EID_SHIFT 16
158 # define SIDL_EID_MASK 3
159 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
160 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
161 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
162 # define DLC_RTR_SHIFT 6
163 #define TXBCTRL_OFF 0
164 #define TXBSIDH_OFF 1
165 #define TXBSIDL_OFF 2
166 #define TXBEID8_OFF 3
167 #define TXBEID0_OFF 4
168 #define TXBDLC_OFF 5
169 #define TXBDAT_OFF 6
170 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
171 # define RXBCTRL_BUKT 0x04
172 # define RXBCTRL_RXM0 0x20
173 # define RXBCTRL_RXM1 0x40
174 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
175 # define RXBSIDH_SHIFT 3
176 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
177 # define RXBSIDL_IDE 0x08
178 # define RXBSIDL_SRR 0x10
179 # define RXBSIDL_EID 3
180 # define RXBSIDL_SHIFT 5
181 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
182 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
183 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
184 # define RXBDLC_LEN_MASK 0x0f
185 # define RXBDLC_RTR 0x40
186 #define RXBCTRL_OFF 0
187 #define RXBSIDH_OFF 1
188 #define RXBSIDL_OFF 2
189 #define RXBEID8_OFF 3
190 #define RXBEID0_OFF 4
191 #define RXBDLC_OFF 5
192 #define RXBDAT_OFF 6
193 #define RXFSIDH(n) ((n) * 4)
194 #define RXFSIDL(n) ((n) * 4 + 1)
195 #define RXFEID8(n) ((n) * 4 + 2)
196 #define RXFEID0(n) ((n) * 4 + 3)
197 #define RXMSIDH(n) ((n) * 4 + 0x20)
198 #define RXMSIDL(n) ((n) * 4 + 0x21)
199 #define RXMEID8(n) ((n) * 4 + 0x22)
200 #define RXMEID0(n) ((n) * 4 + 0x23)
201
202 #define GET_BYTE(val, byte) \
203 (((val) >> ((byte) * 8)) & 0xff)
204 #define SET_BYTE(val, byte) \
205 (((val) & 0xff) << ((byte) * 8))
206
207 /*
208 * Buffer size required for the largest SPI transfer (i.e., reading a
209 * frame)
210 */
211 #define CAN_FRAME_MAX_DATA_LEN 8
212 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
213 #define CAN_FRAME_MAX_BITS 128
214
215 #define TX_ECHO_SKB_MAX 1
216
217 #define DEVICE_NAME "mcp251x"
218
219 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
220 module_param(mcp251x_enable_dma, int, S_IRUGO);
221 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
222
223 static const struct can_bittiming_const mcp251x_bittiming_const = {
224 .name = DEVICE_NAME,
225 .tseg1_min = 3,
226 .tseg1_max = 16,
227 .tseg2_min = 2,
228 .tseg2_max = 8,
229 .sjw_max = 4,
230 .brp_min = 1,
231 .brp_max = 64,
232 .brp_inc = 1,
233 };
234
235 enum mcp251x_model {
236 CAN_MCP251X_MCP2510 = 0x2510,
237 CAN_MCP251X_MCP2515 = 0x2515,
238 };
239
240 struct mcp251x_priv {
241 struct can_priv can;
242 struct net_device *net;
243 struct spi_device *spi;
244 enum mcp251x_model model;
245
246 struct mutex mcp_lock; /* SPI device lock */
247
248 u8 *spi_tx_buf;
249 u8 *spi_rx_buf;
250 dma_addr_t spi_tx_dma;
251 dma_addr_t spi_rx_dma;
252
253 struct sk_buff *tx_skb;
254 int tx_len;
255
256 struct workqueue_struct *wq;
257 struct work_struct tx_work;
258 struct work_struct restart_work;
259
260 int force_quit;
261 int after_suspend;
262 #define AFTER_SUSPEND_UP 1
263 #define AFTER_SUSPEND_DOWN 2
264 #define AFTER_SUSPEND_POWER 4
265 #define AFTER_SUSPEND_RESTART 8
266 int restart_tx;
267 struct regulator *power;
268 struct regulator *transceiver;
269 struct clk *clk;
270 };
271
272 #define MCP251X_IS(_model) \
273 static inline int mcp251x_is_##_model(struct spi_device *spi) \
274 { \
275 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
276 return priv->model == CAN_MCP251X_MCP##_model; \
277 }
278
279 MCP251X_IS(2510);
280 MCP251X_IS(2515);
281
282 static void mcp251x_clean(struct net_device *net)
283 {
284 struct mcp251x_priv *priv = netdev_priv(net);
285
286 if (priv->tx_skb || priv->tx_len)
287 net->stats.tx_errors++;
288 if (priv->tx_skb)
289 dev_kfree_skb(priv->tx_skb);
290 if (priv->tx_len)
291 can_free_echo_skb(priv->net, 0);
292 priv->tx_skb = NULL;
293 priv->tx_len = 0;
294 }
295
296 /*
297 * Note about handling of error return of mcp251x_spi_trans: accessing
298 * registers via SPI is not really different conceptually than using
299 * normal I/O assembler instructions, although it's much more
300 * complicated from a practical POV. So it's not advisable to always
301 * check the return value of this function. Imagine that every
302 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
303 * error();", it would be a great mess (well there are some situation
304 * when exception handling C++ like could be useful after all). So we
305 * just check that transfers are OK at the beginning of our
306 * conversation with the chip and to avoid doing really nasty things
307 * (like injecting bogus packets in the network stack).
308 */
309 static int mcp251x_spi_trans(struct spi_device *spi, int len)
310 {
311 struct mcp251x_priv *priv = spi_get_drvdata(spi);
312 struct spi_transfer t = {
313 .tx_buf = priv->spi_tx_buf,
314 .rx_buf = priv->spi_rx_buf,
315 .len = len,
316 .cs_change = 0,
317 };
318 struct spi_message m;
319 int ret;
320
321 spi_message_init(&m);
322
323 if (mcp251x_enable_dma) {
324 t.tx_dma = priv->spi_tx_dma;
325 t.rx_dma = priv->spi_rx_dma;
326 m.is_dma_mapped = 1;
327 }
328
329 spi_message_add_tail(&t, &m);
330
331 ret = spi_sync(spi, &m);
332 if (ret)
333 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
334 return ret;
335 }
336
337 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
338 {
339 struct mcp251x_priv *priv = spi_get_drvdata(spi);
340 u8 val = 0;
341
342 priv->spi_tx_buf[0] = INSTRUCTION_READ;
343 priv->spi_tx_buf[1] = reg;
344
345 mcp251x_spi_trans(spi, 3);
346 val = priv->spi_rx_buf[2];
347
348 return val;
349 }
350
351 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
352 uint8_t *v1, uint8_t *v2)
353 {
354 struct mcp251x_priv *priv = spi_get_drvdata(spi);
355
356 priv->spi_tx_buf[0] = INSTRUCTION_READ;
357 priv->spi_tx_buf[1] = reg;
358
359 mcp251x_spi_trans(spi, 4);
360
361 *v1 = priv->spi_rx_buf[2];
362 *v2 = priv->spi_rx_buf[3];
363 }
364
365 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
366 {
367 struct mcp251x_priv *priv = spi_get_drvdata(spi);
368
369 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
370 priv->spi_tx_buf[1] = reg;
371 priv->spi_tx_buf[2] = val;
372
373 mcp251x_spi_trans(spi, 3);
374 }
375
376 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
377 u8 mask, uint8_t val)
378 {
379 struct mcp251x_priv *priv = spi_get_drvdata(spi);
380
381 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
382 priv->spi_tx_buf[1] = reg;
383 priv->spi_tx_buf[2] = mask;
384 priv->spi_tx_buf[3] = val;
385
386 mcp251x_spi_trans(spi, 4);
387 }
388
389 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
390 int len, int tx_buf_idx)
391 {
392 struct mcp251x_priv *priv = spi_get_drvdata(spi);
393
394 if (mcp251x_is_2510(spi)) {
395 int i;
396
397 for (i = 1; i < TXBDAT_OFF + len; i++)
398 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
399 buf[i]);
400 } else {
401 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
402 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
403 }
404 }
405
406 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
407 int tx_buf_idx)
408 {
409 struct mcp251x_priv *priv = spi_get_drvdata(spi);
410 u32 sid, eid, exide, rtr;
411 u8 buf[SPI_TRANSFER_BUF_LEN];
412
413 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
414 if (exide)
415 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
416 else
417 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
418 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
419 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
420
421 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
422 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
423 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
424 (exide << SIDL_EXIDE_SHIFT) |
425 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
426 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
427 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
428 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
429 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
430 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
431
432 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
433 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
434 mcp251x_spi_trans(priv->spi, 1);
435 }
436
437 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
438 int buf_idx)
439 {
440 struct mcp251x_priv *priv = spi_get_drvdata(spi);
441
442 if (mcp251x_is_2510(spi)) {
443 int i, len;
444
445 for (i = 1; i < RXBDAT_OFF; i++)
446 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
447
448 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
449 for (; i < (RXBDAT_OFF + len); i++)
450 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
451 } else {
452 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
453 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
454 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
455 }
456 }
457
458 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
459 {
460 struct mcp251x_priv *priv = spi_get_drvdata(spi);
461 struct sk_buff *skb;
462 struct can_frame *frame;
463 u8 buf[SPI_TRANSFER_BUF_LEN];
464
465 skb = alloc_can_skb(priv->net, &frame);
466 if (!skb) {
467 dev_err(&spi->dev, "cannot allocate RX skb\n");
468 priv->net->stats.rx_dropped++;
469 return;
470 }
471
472 mcp251x_hw_rx_frame(spi, buf, buf_idx);
473 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
474 /* Extended ID format */
475 frame->can_id = CAN_EFF_FLAG;
476 frame->can_id |=
477 /* Extended ID part */
478 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
479 SET_BYTE(buf[RXBEID8_OFF], 1) |
480 SET_BYTE(buf[RXBEID0_OFF], 0) |
481 /* Standard ID part */
482 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
483 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
484 /* Remote transmission request */
485 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
486 frame->can_id |= CAN_RTR_FLAG;
487 } else {
488 /* Standard ID format */
489 frame->can_id =
490 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
491 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
492 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
493 frame->can_id |= CAN_RTR_FLAG;
494 }
495 /* Data length */
496 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
497 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
498
499 priv->net->stats.rx_packets++;
500 priv->net->stats.rx_bytes += frame->can_dlc;
501
502 can_led_event(priv->net, CAN_LED_EVENT_RX);
503
504 netif_rx_ni(skb);
505 }
506
507 static void mcp251x_hw_sleep(struct spi_device *spi)
508 {
509 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
510 }
511
512 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
513 struct net_device *net)
514 {
515 struct mcp251x_priv *priv = netdev_priv(net);
516 struct spi_device *spi = priv->spi;
517
518 if (priv->tx_skb || priv->tx_len) {
519 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
520 return NETDEV_TX_BUSY;
521 }
522
523 if (can_dropped_invalid_skb(net, skb))
524 return NETDEV_TX_OK;
525
526 netif_stop_queue(net);
527 priv->tx_skb = skb;
528 queue_work(priv->wq, &priv->tx_work);
529
530 return NETDEV_TX_OK;
531 }
532
533 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
534 {
535 struct mcp251x_priv *priv = netdev_priv(net);
536
537 switch (mode) {
538 case CAN_MODE_START:
539 mcp251x_clean(net);
540 /* We have to delay work since SPI I/O may sleep */
541 priv->can.state = CAN_STATE_ERROR_ACTIVE;
542 priv->restart_tx = 1;
543 if (priv->can.restart_ms == 0)
544 priv->after_suspend = AFTER_SUSPEND_RESTART;
545 queue_work(priv->wq, &priv->restart_work);
546 break;
547 default:
548 return -EOPNOTSUPP;
549 }
550
551 return 0;
552 }
553
554 static int mcp251x_set_normal_mode(struct spi_device *spi)
555 {
556 struct mcp251x_priv *priv = spi_get_drvdata(spi);
557 unsigned long timeout;
558
559 /* Enable interrupts */
560 mcp251x_write_reg(spi, CANINTE,
561 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
562 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
563
564 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
565 /* Put device into loopback mode */
566 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
567 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
568 /* Put device into listen-only mode */
569 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
570 } else {
571 /* Put device into normal mode */
572 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
573
574 /* Wait for the device to enter normal mode */
575 timeout = jiffies + HZ;
576 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
577 schedule();
578 if (time_after(jiffies, timeout)) {
579 dev_err(&spi->dev, "MCP251x didn't"
580 " enter in normal mode\n");
581 return -EBUSY;
582 }
583 }
584 }
585 priv->can.state = CAN_STATE_ERROR_ACTIVE;
586 return 0;
587 }
588
589 static int mcp251x_do_set_bittiming(struct net_device *net)
590 {
591 struct mcp251x_priv *priv = netdev_priv(net);
592 struct can_bittiming *bt = &priv->can.bittiming;
593 struct spi_device *spi = priv->spi;
594
595 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
596 (bt->brp - 1));
597 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
598 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
599 CNF2_SAM : 0) |
600 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
601 (bt->prop_seg - 1));
602 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
603 (bt->phase_seg2 - 1));
604 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
605 mcp251x_read_reg(spi, CNF1),
606 mcp251x_read_reg(spi, CNF2),
607 mcp251x_read_reg(spi, CNF3));
608
609 return 0;
610 }
611
612 static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
613 struct spi_device *spi)
614 {
615 mcp251x_do_set_bittiming(net);
616
617 mcp251x_write_reg(spi, RXBCTRL(0),
618 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
619 mcp251x_write_reg(spi, RXBCTRL(1),
620 RXBCTRL_RXM0 | RXBCTRL_RXM1);
621 return 0;
622 }
623
624 static int mcp251x_hw_reset(struct spi_device *spi)
625 {
626 struct mcp251x_priv *priv = spi_get_drvdata(spi);
627 int ret;
628 unsigned long timeout;
629
630 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
631 ret = spi_write(spi, priv->spi_tx_buf, 1);
632 if (ret) {
633 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
634 return -EIO;
635 }
636
637 /* Wait for reset to finish */
638 timeout = jiffies + HZ;
639 mdelay(10);
640 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
641 != CANCTRL_REQOP_CONF) {
642 schedule();
643 if (time_after(jiffies, timeout)) {
644 dev_err(&spi->dev, "MCP251x didn't"
645 " enter in conf mode after reset\n");
646 return -EBUSY;
647 }
648 }
649 return 0;
650 }
651
652 static int mcp251x_hw_probe(struct spi_device *spi)
653 {
654 int st1, st2;
655
656 mcp251x_hw_reset(spi);
657
658 /*
659 * Please note that these are "magic values" based on after
660 * reset defaults taken from data sheet which allows us to see
661 * if we really have a chip on the bus (we avoid common all
662 * zeroes or all ones situations)
663 */
664 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
665 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
666
667 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
668
669 /* Check for power up default values */
670 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
671 }
672
673 static int mcp251x_power_enable(struct regulator *reg, int enable)
674 {
675 if (IS_ERR(reg))
676 return 0;
677
678 if (enable)
679 return regulator_enable(reg);
680 else
681 return regulator_disable(reg);
682 }
683
684 static void mcp251x_open_clean(struct net_device *net)
685 {
686 struct mcp251x_priv *priv = netdev_priv(net);
687 struct spi_device *spi = priv->spi;
688
689 free_irq(spi->irq, priv);
690 mcp251x_hw_sleep(spi);
691 mcp251x_power_enable(priv->transceiver, 0);
692 close_candev(net);
693 }
694
695 static int mcp251x_stop(struct net_device *net)
696 {
697 struct mcp251x_priv *priv = netdev_priv(net);
698 struct spi_device *spi = priv->spi;
699
700 close_candev(net);
701
702 priv->force_quit = 1;
703 free_irq(spi->irq, priv);
704 destroy_workqueue(priv->wq);
705 priv->wq = NULL;
706
707 mutex_lock(&priv->mcp_lock);
708
709 /* Disable and clear pending interrupts */
710 mcp251x_write_reg(spi, CANINTE, 0x00);
711 mcp251x_write_reg(spi, CANINTF, 0x00);
712
713 mcp251x_write_reg(spi, TXBCTRL(0), 0);
714 mcp251x_clean(net);
715
716 mcp251x_hw_sleep(spi);
717
718 mcp251x_power_enable(priv->transceiver, 0);
719
720 priv->can.state = CAN_STATE_STOPPED;
721
722 mutex_unlock(&priv->mcp_lock);
723
724 can_led_event(net, CAN_LED_EVENT_STOP);
725
726 return 0;
727 }
728
729 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
730 {
731 struct sk_buff *skb;
732 struct can_frame *frame;
733
734 skb = alloc_can_err_skb(net, &frame);
735 if (skb) {
736 frame->can_id |= can_id;
737 frame->data[1] = data1;
738 netif_rx_ni(skb);
739 } else {
740 netdev_err(net, "cannot allocate error skb\n");
741 }
742 }
743
744 static void mcp251x_tx_work_handler(struct work_struct *ws)
745 {
746 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
747 tx_work);
748 struct spi_device *spi = priv->spi;
749 struct net_device *net = priv->net;
750 struct can_frame *frame;
751
752 mutex_lock(&priv->mcp_lock);
753 if (priv->tx_skb) {
754 if (priv->can.state == CAN_STATE_BUS_OFF) {
755 mcp251x_clean(net);
756 } else {
757 frame = (struct can_frame *)priv->tx_skb->data;
758
759 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
760 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
761 mcp251x_hw_tx(spi, frame, 0);
762 priv->tx_len = 1 + frame->can_dlc;
763 can_put_echo_skb(priv->tx_skb, net, 0);
764 priv->tx_skb = NULL;
765 }
766 }
767 mutex_unlock(&priv->mcp_lock);
768 }
769
770 static void mcp251x_restart_work_handler(struct work_struct *ws)
771 {
772 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
773 restart_work);
774 struct spi_device *spi = priv->spi;
775 struct net_device *net = priv->net;
776
777 mutex_lock(&priv->mcp_lock);
778 if (priv->after_suspend) {
779 mdelay(10);
780 mcp251x_hw_reset(spi);
781 mcp251x_setup(net, priv, spi);
782 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
783 mcp251x_set_normal_mode(spi);
784 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
785 netif_device_attach(net);
786 mcp251x_clean(net);
787 mcp251x_set_normal_mode(spi);
788 netif_wake_queue(net);
789 } else {
790 mcp251x_hw_sleep(spi);
791 }
792 priv->after_suspend = 0;
793 priv->force_quit = 0;
794 }
795
796 if (priv->restart_tx) {
797 priv->restart_tx = 0;
798 mcp251x_write_reg(spi, TXBCTRL(0), 0);
799 mcp251x_clean(net);
800 netif_wake_queue(net);
801 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
802 }
803 mutex_unlock(&priv->mcp_lock);
804 }
805
806 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
807 {
808 struct mcp251x_priv *priv = dev_id;
809 struct spi_device *spi = priv->spi;
810 struct net_device *net = priv->net;
811
812 mutex_lock(&priv->mcp_lock);
813 while (!priv->force_quit) {
814 enum can_state new_state;
815 u8 intf, eflag;
816 u8 clear_intf = 0;
817 int can_id = 0, data1 = 0;
818
819 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
820
821 /* mask out flags we don't care about */
822 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
823
824 /* receive buffer 0 */
825 if (intf & CANINTF_RX0IF) {
826 mcp251x_hw_rx(spi, 0);
827 /*
828 * Free one buffer ASAP
829 * (The MCP2515 does this automatically.)
830 */
831 if (mcp251x_is_2510(spi))
832 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
833 }
834
835 /* receive buffer 1 */
836 if (intf & CANINTF_RX1IF) {
837 mcp251x_hw_rx(spi, 1);
838 /* the MCP2515 does this automatically */
839 if (mcp251x_is_2510(spi))
840 clear_intf |= CANINTF_RX1IF;
841 }
842
843 /* any error or tx interrupt we need to clear? */
844 if (intf & (CANINTF_ERR | CANINTF_TX))
845 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
846 if (clear_intf)
847 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
848
849 if (eflag)
850 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
851
852 /* Update can state */
853 if (eflag & EFLG_TXBO) {
854 new_state = CAN_STATE_BUS_OFF;
855 can_id |= CAN_ERR_BUSOFF;
856 } else if (eflag & EFLG_TXEP) {
857 new_state = CAN_STATE_ERROR_PASSIVE;
858 can_id |= CAN_ERR_CRTL;
859 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
860 } else if (eflag & EFLG_RXEP) {
861 new_state = CAN_STATE_ERROR_PASSIVE;
862 can_id |= CAN_ERR_CRTL;
863 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
864 } else if (eflag & EFLG_TXWAR) {
865 new_state = CAN_STATE_ERROR_WARNING;
866 can_id |= CAN_ERR_CRTL;
867 data1 |= CAN_ERR_CRTL_TX_WARNING;
868 } else if (eflag & EFLG_RXWAR) {
869 new_state = CAN_STATE_ERROR_WARNING;
870 can_id |= CAN_ERR_CRTL;
871 data1 |= CAN_ERR_CRTL_RX_WARNING;
872 } else {
873 new_state = CAN_STATE_ERROR_ACTIVE;
874 }
875
876 /* Update can state statistics */
877 switch (priv->can.state) {
878 case CAN_STATE_ERROR_ACTIVE:
879 if (new_state >= CAN_STATE_ERROR_WARNING &&
880 new_state <= CAN_STATE_BUS_OFF)
881 priv->can.can_stats.error_warning++;
882 case CAN_STATE_ERROR_WARNING: /* fallthrough */
883 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
884 new_state <= CAN_STATE_BUS_OFF)
885 priv->can.can_stats.error_passive++;
886 break;
887 default:
888 break;
889 }
890 priv->can.state = new_state;
891
892 if (intf & CANINTF_ERRIF) {
893 /* Handle overflow counters */
894 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
895 if (eflag & EFLG_RX0OVR) {
896 net->stats.rx_over_errors++;
897 net->stats.rx_errors++;
898 }
899 if (eflag & EFLG_RX1OVR) {
900 net->stats.rx_over_errors++;
901 net->stats.rx_errors++;
902 }
903 can_id |= CAN_ERR_CRTL;
904 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
905 }
906 mcp251x_error_skb(net, can_id, data1);
907 }
908
909 if (priv->can.state == CAN_STATE_BUS_OFF) {
910 if (priv->can.restart_ms == 0) {
911 priv->force_quit = 1;
912 can_bus_off(net);
913 mcp251x_hw_sleep(spi);
914 break;
915 }
916 }
917
918 if (intf == 0)
919 break;
920
921 if (intf & CANINTF_TX) {
922 net->stats.tx_packets++;
923 net->stats.tx_bytes += priv->tx_len - 1;
924 can_led_event(net, CAN_LED_EVENT_TX);
925 if (priv->tx_len) {
926 can_get_echo_skb(net, 0);
927 priv->tx_len = 0;
928 }
929 netif_wake_queue(net);
930 }
931
932 }
933 mutex_unlock(&priv->mcp_lock);
934 return IRQ_HANDLED;
935 }
936
937 static int mcp251x_open(struct net_device *net)
938 {
939 struct mcp251x_priv *priv = netdev_priv(net);
940 struct spi_device *spi = priv->spi;
941 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING;
942 int ret;
943
944 ret = open_candev(net);
945 if (ret) {
946 dev_err(&spi->dev, "unable to set initial baudrate!\n");
947 return ret;
948 }
949
950 mutex_lock(&priv->mcp_lock);
951 mcp251x_power_enable(priv->transceiver, 1);
952
953 priv->force_quit = 0;
954 priv->tx_skb = NULL;
955 priv->tx_len = 0;
956
957 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
958 flags, DEVICE_NAME, priv);
959 if (ret) {
960 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
961 mcp251x_power_enable(priv->transceiver, 0);
962 close_candev(net);
963 goto open_unlock;
964 }
965
966 priv->wq = create_freezable_workqueue("mcp251x_wq");
967 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
968 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
969
970 ret = mcp251x_hw_reset(spi);
971 if (ret) {
972 mcp251x_open_clean(net);
973 goto open_unlock;
974 }
975 ret = mcp251x_setup(net, priv, spi);
976 if (ret) {
977 mcp251x_open_clean(net);
978 goto open_unlock;
979 }
980 ret = mcp251x_set_normal_mode(spi);
981 if (ret) {
982 mcp251x_open_clean(net);
983 goto open_unlock;
984 }
985
986 can_led_event(net, CAN_LED_EVENT_OPEN);
987
988 netif_wake_queue(net);
989
990 open_unlock:
991 mutex_unlock(&priv->mcp_lock);
992 return ret;
993 }
994
995 static const struct net_device_ops mcp251x_netdev_ops = {
996 .ndo_open = mcp251x_open,
997 .ndo_stop = mcp251x_stop,
998 .ndo_start_xmit = mcp251x_hard_start_xmit,
999 };
1000
1001 static const struct of_device_id mcp251x_of_match[] = {
1002 {
1003 .compatible = "microchip,mcp2510",
1004 .data = (void *)CAN_MCP251X_MCP2510,
1005 },
1006 {
1007 .compatible = "microchip,mcp2515",
1008 .data = (void *)CAN_MCP251X_MCP2515,
1009 },
1010 { }
1011 };
1012 MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1013
1014 static const struct spi_device_id mcp251x_id_table[] = {
1015 {
1016 .name = "mcp2510",
1017 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1018 },
1019 {
1020 .name = "mcp2515",
1021 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1022 },
1023 { }
1024 };
1025 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1026
1027 static int mcp251x_can_probe(struct spi_device *spi)
1028 {
1029 const struct of_device_id *of_id = of_match_device(mcp251x_of_match,
1030 &spi->dev);
1031 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
1032 struct net_device *net;
1033 struct mcp251x_priv *priv;
1034 int freq, ret = -ENODEV;
1035 struct clk *clk;
1036
1037 clk = devm_clk_get(&spi->dev, NULL);
1038 if (IS_ERR(clk)) {
1039 if (pdata)
1040 freq = pdata->oscillator_frequency;
1041 else
1042 return PTR_ERR(clk);
1043 } else {
1044 freq = clk_get_rate(clk);
1045 }
1046
1047 /* Sanity check */
1048 if (freq < 1000000 || freq > 25000000)
1049 return -ERANGE;
1050
1051 /* Allocate can/net device */
1052 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1053 if (!net)
1054 return -ENOMEM;
1055
1056 if (!IS_ERR(clk)) {
1057 ret = clk_prepare_enable(clk);
1058 if (ret)
1059 goto out_free;
1060 }
1061
1062 net->netdev_ops = &mcp251x_netdev_ops;
1063 net->flags |= IFF_ECHO;
1064
1065 priv = netdev_priv(net);
1066 priv->can.bittiming_const = &mcp251x_bittiming_const;
1067 priv->can.do_set_mode = mcp251x_do_set_mode;
1068 priv->can.clock.freq = freq / 2;
1069 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1070 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1071 if (of_id)
1072 priv->model = (enum mcp251x_model)of_id->data;
1073 else
1074 priv->model = spi_get_device_id(spi)->driver_data;
1075 priv->net = net;
1076 priv->clk = clk;
1077
1078 priv->power = devm_regulator_get(&spi->dev, "vdd");
1079 priv->transceiver = devm_regulator_get(&spi->dev, "xceiver");
1080 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1081 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1082 ret = -EPROBE_DEFER;
1083 goto out_clk;
1084 }
1085
1086 ret = mcp251x_power_enable(priv->power, 1);
1087 if (ret)
1088 goto out_clk;
1089
1090 spi_set_drvdata(spi, priv);
1091
1092 priv->spi = spi;
1093 mutex_init(&priv->mcp_lock);
1094
1095 /* If requested, allocate DMA buffers */
1096 if (mcp251x_enable_dma) {
1097 spi->dev.coherent_dma_mask = ~0;
1098
1099 /*
1100 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1101 * that much and share it between Tx and Rx DMA buffers.
1102 */
1103 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
1104 PAGE_SIZE,
1105 &priv->spi_tx_dma,
1106 GFP_DMA);
1107
1108 if (priv->spi_tx_buf) {
1109 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1110 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1111 (PAGE_SIZE / 2));
1112 } else {
1113 /* Fall back to non-DMA */
1114 mcp251x_enable_dma = 0;
1115 }
1116 }
1117
1118 /* Allocate non-DMA buffers */
1119 if (!mcp251x_enable_dma) {
1120 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1121 GFP_KERNEL);
1122 if (!priv->spi_tx_buf) {
1123 ret = -ENOMEM;
1124 goto error_probe;
1125 }
1126 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1127 GFP_KERNEL);
1128 if (!priv->spi_rx_buf) {
1129 ret = -ENOMEM;
1130 goto error_probe;
1131 }
1132 }
1133
1134 SET_NETDEV_DEV(net, &spi->dev);
1135
1136 /* Configure the SPI bus */
1137 spi->mode = spi->mode ? : SPI_MODE_0;
1138 if (mcp251x_is_2510(spi))
1139 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1140 else
1141 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1142 spi->bits_per_word = 8;
1143 spi_setup(spi);
1144
1145 /* Here is OK to not lock the MCP, no one knows about it yet */
1146 if (!mcp251x_hw_probe(spi)) {
1147 ret = -ENODEV;
1148 goto error_probe;
1149 }
1150 mcp251x_hw_sleep(spi);
1151
1152 ret = register_candev(net);
1153 if (ret)
1154 goto error_probe;
1155
1156 devm_can_led_init(net);
1157
1158 dev_info(&spi->dev, "probed\n");
1159
1160 return ret;
1161
1162 error_probe:
1163 if (mcp251x_enable_dma)
1164 dma_free_coherent(&spi->dev, PAGE_SIZE,
1165 priv->spi_tx_buf, priv->spi_tx_dma);
1166 mcp251x_power_enable(priv->power, 0);
1167
1168 out_clk:
1169 if (!IS_ERR(clk))
1170 clk_disable_unprepare(clk);
1171
1172 out_free:
1173 free_candev(net);
1174
1175 return ret;
1176 }
1177
1178 static int mcp251x_can_remove(struct spi_device *spi)
1179 {
1180 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1181 struct net_device *net = priv->net;
1182
1183 unregister_candev(net);
1184
1185 if (mcp251x_enable_dma) {
1186 dma_free_coherent(&spi->dev, PAGE_SIZE,
1187 priv->spi_tx_buf, priv->spi_tx_dma);
1188 }
1189
1190 mcp251x_power_enable(priv->power, 0);
1191
1192 if (!IS_ERR(priv->clk))
1193 clk_disable_unprepare(priv->clk);
1194
1195 free_candev(net);
1196
1197 return 0;
1198 }
1199
1200 #ifdef CONFIG_PM_SLEEP
1201
1202 static int mcp251x_can_suspend(struct device *dev)
1203 {
1204 struct spi_device *spi = to_spi_device(dev);
1205 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1206 struct net_device *net = priv->net;
1207
1208 priv->force_quit = 1;
1209 disable_irq(spi->irq);
1210 /*
1211 * Note: at this point neither IST nor workqueues are running.
1212 * open/stop cannot be called anyway so locking is not needed
1213 */
1214 if (netif_running(net)) {
1215 netif_device_detach(net);
1216
1217 mcp251x_hw_sleep(spi);
1218 mcp251x_power_enable(priv->transceiver, 0);
1219 priv->after_suspend = AFTER_SUSPEND_UP;
1220 } else {
1221 priv->after_suspend = AFTER_SUSPEND_DOWN;
1222 }
1223
1224 if (!IS_ERR(priv->power)) {
1225 regulator_disable(priv->power);
1226 priv->after_suspend |= AFTER_SUSPEND_POWER;
1227 }
1228
1229 return 0;
1230 }
1231
1232 static int mcp251x_can_resume(struct device *dev)
1233 {
1234 struct spi_device *spi = to_spi_device(dev);
1235 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1236
1237 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1238 mcp251x_power_enable(priv->power, 1);
1239 queue_work(priv->wq, &priv->restart_work);
1240 } else {
1241 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1242 mcp251x_power_enable(priv->transceiver, 1);
1243 queue_work(priv->wq, &priv->restart_work);
1244 } else {
1245 priv->after_suspend = 0;
1246 }
1247 }
1248 priv->force_quit = 0;
1249 enable_irq(spi->irq);
1250 return 0;
1251 }
1252 #endif
1253
1254 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1255 mcp251x_can_resume);
1256
1257 static struct spi_driver mcp251x_can_driver = {
1258 .driver = {
1259 .name = DEVICE_NAME,
1260 .owner = THIS_MODULE,
1261 .of_match_table = mcp251x_of_match,
1262 .pm = &mcp251x_can_pm_ops,
1263 },
1264 .id_table = mcp251x_id_table,
1265 .probe = mcp251x_can_probe,
1266 .remove = mcp251x_can_remove,
1267 };
1268 module_spi_driver(mcp251x_can_driver);
1269
1270 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1271 "Christian Pellegrin <chripell@evolware.org>");
1272 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1273 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support