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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / ethernet / cadence / macb.c
blob3190d38e16fbd5d59a8cbc0cca7378a500572402
1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
33 #include <linux/pinctrl/consumer.h>
34
35 #include "macb.h"
36
37 #define MACB_RX_BUFFER_SIZE 128
38 #define RX_BUFFER_MULTIPLE 64 /* bytes */
39 #define RX_RING_SIZE 512 /* must be power of 2 */
40 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
41
42 #define TX_RING_SIZE 128 /* must be power of 2 */
43 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
44
45 /* level of occupied TX descriptors under which we wake up TX process */
46 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
47
48 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 | MACB_BIT(ISR_ROVR))
50 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
51 | MACB_BIT(ISR_RLE) \
52 | MACB_BIT(TXERR))
53 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54
55 /*
56 * Graceful stop timeouts in us. We should allow up to
57 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
58 */
59 #define MACB_HALT_TIMEOUT 1230
60
61 /* Ring buffer accessors */
62 static unsigned int macb_tx_ring_wrap(unsigned int index)
63 {
64 return index & (TX_RING_SIZE - 1);
65 }
66
67 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
68 {
69 return &bp->tx_ring[macb_tx_ring_wrap(index)];
70 }
71
72 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
73 {
74 return &bp->tx_skb[macb_tx_ring_wrap(index)];
75 }
76
77 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
78 {
79 dma_addr_t offset;
80
81 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
82
83 return bp->tx_ring_dma + offset;
84 }
85
86 static unsigned int macb_rx_ring_wrap(unsigned int index)
87 {
88 return index & (RX_RING_SIZE - 1);
89 }
90
91 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
92 {
93 return &bp->rx_ring[macb_rx_ring_wrap(index)];
94 }
95
96 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
97 {
98 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
99 }
100
101 void macb_set_hwaddr(struct macb *bp)
102 {
103 u32 bottom;
104 u16 top;
105
106 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
107 macb_or_gem_writel(bp, SA1B, bottom);
108 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
109 macb_or_gem_writel(bp, SA1T, top);
110
111 /* Clear unused address register sets */
112 macb_or_gem_writel(bp, SA2B, 0);
113 macb_or_gem_writel(bp, SA2T, 0);
114 macb_or_gem_writel(bp, SA3B, 0);
115 macb_or_gem_writel(bp, SA3T, 0);
116 macb_or_gem_writel(bp, SA4B, 0);
117 macb_or_gem_writel(bp, SA4T, 0);
118 }
119 EXPORT_SYMBOL_GPL(macb_set_hwaddr);
120
121 void macb_get_hwaddr(struct macb *bp)
122 {
123 struct macb_platform_data *pdata;
124 u32 bottom;
125 u16 top;
126 u8 addr[6];
127 int i;
128
129 pdata = dev_get_platdata(&bp->pdev->dev);
130
131 /* Check all 4 address register for vaild address */
132 for (i = 0; i < 4; i++) {
133 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
134 top = macb_or_gem_readl(bp, SA1T + i * 8);
135
136 if (pdata && pdata->rev_eth_addr) {
137 addr[5] = bottom & 0xff;
138 addr[4] = (bottom >> 8) & 0xff;
139 addr[3] = (bottom >> 16) & 0xff;
140 addr[2] = (bottom >> 24) & 0xff;
141 addr[1] = top & 0xff;
142 addr[0] = (top & 0xff00) >> 8;
143 } else {
144 addr[0] = bottom & 0xff;
145 addr[1] = (bottom >> 8) & 0xff;
146 addr[2] = (bottom >> 16) & 0xff;
147 addr[3] = (bottom >> 24) & 0xff;
148 addr[4] = top & 0xff;
149 addr[5] = (top >> 8) & 0xff;
150 }
151
152 if (is_valid_ether_addr(addr)) {
153 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
154 return;
155 }
156 }
157
158 netdev_info(bp->dev, "invalid hw address, using random\n");
159 eth_hw_addr_random(bp->dev);
160 }
161 EXPORT_SYMBOL_GPL(macb_get_hwaddr);
162
163 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
164 {
165 struct macb *bp = bus->priv;
166 int value;
167
168 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
169 | MACB_BF(RW, MACB_MAN_READ)
170 | MACB_BF(PHYA, mii_id)
171 | MACB_BF(REGA, regnum)
172 | MACB_BF(CODE, MACB_MAN_CODE)));
173
174 /* wait for end of transfer */
175 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
176 cpu_relax();
177
178 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
179
180 return value;
181 }
182
183 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
184 u16 value)
185 {
186 struct macb *bp = bus->priv;
187
188 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
189 | MACB_BF(RW, MACB_MAN_WRITE)
190 | MACB_BF(PHYA, mii_id)
191 | MACB_BF(REGA, regnum)
192 | MACB_BF(CODE, MACB_MAN_CODE)
193 | MACB_BF(DATA, value)));
194
195 /* wait for end of transfer */
196 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
197 cpu_relax();
198
199 return 0;
200 }
201
202 static int macb_mdio_reset(struct mii_bus *bus)
203 {
204 return 0;
205 }
206
207 /**
208 * macb_set_tx_clk() - Set a clock to a new frequency
209 * @clk Pointer to the clock to change
210 * @rate New frequency in Hz
211 * @dev Pointer to the struct net_device
212 */
213 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
214 {
215 long ferr, rate, rate_rounded;
216
217 switch (speed) {
218 case SPEED_10:
219 rate = 2500000;
220 break;
221 case SPEED_100:
222 rate = 25000000;
223 break;
224 case SPEED_1000:
225 rate = 125000000;
226 break;
227 default:
228 return;
229 }
230
231 rate_rounded = clk_round_rate(clk, rate);
232 if (rate_rounded < 0)
233 return;
234
235 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
236 * is not satisfied.
237 */
238 ferr = abs(rate_rounded - rate);
239 ferr = DIV_ROUND_UP(ferr, rate / 100000);
240 if (ferr > 5)
241 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
242 rate);
243
244 if (clk_set_rate(clk, rate_rounded))
245 netdev_err(dev, "adjusting tx_clk failed.\n");
246 }
247
248 static void macb_handle_link_change(struct net_device *dev)
249 {
250 struct macb *bp = netdev_priv(dev);
251 struct phy_device *phydev = bp->phy_dev;
252 unsigned long flags;
253
254 int status_change = 0;
255
256 spin_lock_irqsave(&bp->lock, flags);
257
258 if (phydev->link) {
259 if ((bp->speed != phydev->speed) ||
260 (bp->duplex != phydev->duplex)) {
261 u32 reg;
262
263 reg = macb_readl(bp, NCFGR);
264 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
265 if (macb_is_gem(bp))
266 reg &= ~GEM_BIT(GBE);
267
268 if (phydev->duplex)
269 reg |= MACB_BIT(FD);
270 if (phydev->speed == SPEED_100)
271 reg |= MACB_BIT(SPD);
272 if (phydev->speed == SPEED_1000)
273 reg |= GEM_BIT(GBE);
274
275 macb_or_gem_writel(bp, NCFGR, reg);
276
277 bp->speed = phydev->speed;
278 bp->duplex = phydev->duplex;
279 status_change = 1;
280 }
281 }
282
283 if (phydev->link != bp->link) {
284 if (!phydev->link) {
285 bp->speed = 0;
286 bp->duplex = -1;
287 }
288 bp->link = phydev->link;
289
290 status_change = 1;
291 }
292
293 spin_unlock_irqrestore(&bp->lock, flags);
294
295 if (!IS_ERR(bp->tx_clk))
296 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
297
298 if (status_change) {
299 if (phydev->link) {
300 netif_carrier_on(dev);
301 netdev_info(dev, "link up (%d/%s)\n",
302 phydev->speed,
303 phydev->duplex == DUPLEX_FULL ?
304 "Full" : "Half");
305 } else {
306 netif_carrier_off(dev);
307 netdev_info(dev, "link down\n");
308 }
309 }
310 }
311
312 /* based on au1000_eth. c*/
313 static int macb_mii_probe(struct net_device *dev)
314 {
315 struct macb *bp = netdev_priv(dev);
316 struct macb_platform_data *pdata;
317 struct phy_device *phydev;
318 int phy_irq;
319 int ret;
320
321 phydev = phy_find_first(bp->mii_bus);
322 if (!phydev) {
323 netdev_err(dev, "no PHY found\n");
324 return -ENXIO;
325 }
326
327 pdata = dev_get_platdata(&bp->pdev->dev);
328 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
329 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
330 if (!ret) {
331 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
332 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
333 }
334 }
335
336 /* attach the mac to the phy */
337 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
338 bp->phy_interface);
339 if (ret) {
340 netdev_err(dev, "Could not attach to PHY\n");
341 return ret;
342 }
343
344 /* mask with MAC supported features */
345 if (macb_is_gem(bp))
346 phydev->supported &= PHY_GBIT_FEATURES;
347 else
348 phydev->supported &= PHY_BASIC_FEATURES;
349
350 phydev->advertising = phydev->supported;
351
352 bp->link = 0;
353 bp->speed = 0;
354 bp->duplex = -1;
355 bp->phy_dev = phydev;
356
357 return 0;
358 }
359
360 int macb_mii_init(struct macb *bp)
361 {
362 struct macb_platform_data *pdata;
363 struct device_node *np;
364 int err = -ENXIO, i;
365
366 /* Enable management port */
367 macb_writel(bp, NCR, MACB_BIT(MPE));
368
369 bp->mii_bus = mdiobus_alloc();
370 if (bp->mii_bus == NULL) {
371 err = -ENOMEM;
372 goto err_out;
373 }
374
375 bp->mii_bus->name = "MACB_mii_bus";
376 bp->mii_bus->read = &macb_mdio_read;
377 bp->mii_bus->write = &macb_mdio_write;
378 bp->mii_bus->reset = &macb_mdio_reset;
379 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
380 bp->pdev->name, bp->pdev->id);
381 bp->mii_bus->priv = bp;
382 bp->mii_bus->parent = &bp->dev->dev;
383 pdata = dev_get_platdata(&bp->pdev->dev);
384
385 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
386 if (!bp->mii_bus->irq) {
387 err = -ENOMEM;
388 goto err_out_free_mdiobus;
389 }
390
391 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
392
393 np = bp->pdev->dev.of_node;
394 if (np) {
395 /* try dt phy registration */
396 err = of_mdiobus_register(bp->mii_bus, np);
397
398 /* fallback to standard phy registration if no phy were
399 found during dt phy registration */
400 if (!err && !phy_find_first(bp->mii_bus)) {
401 for (i = 0; i < PHY_MAX_ADDR; i++) {
402 struct phy_device *phydev;
403
404 phydev = mdiobus_scan(bp->mii_bus, i);
405 if (IS_ERR(phydev)) {
406 err = PTR_ERR(phydev);
407 break;
408 }
409 }
410
411 if (err)
412 goto err_out_unregister_bus;
413 }
414 } else {
415 for (i = 0; i < PHY_MAX_ADDR; i++)
416 bp->mii_bus->irq[i] = PHY_POLL;
417
418 if (pdata)
419 bp->mii_bus->phy_mask = pdata->phy_mask;
420
421 err = mdiobus_register(bp->mii_bus);
422 }
423
424 if (err)
425 goto err_out_free_mdio_irq;
426
427 err = macb_mii_probe(bp->dev);
428 if (err)
429 goto err_out_unregister_bus;
430
431 return 0;
432
433 err_out_unregister_bus:
434 mdiobus_unregister(bp->mii_bus);
435 err_out_free_mdio_irq:
436 kfree(bp->mii_bus->irq);
437 err_out_free_mdiobus:
438 mdiobus_free(bp->mii_bus);
439 err_out:
440 return err;
441 }
442 EXPORT_SYMBOL_GPL(macb_mii_init);
443
444 static void macb_update_stats(struct macb *bp)
445 {
446 u32 __iomem *reg = bp->regs + MACB_PFR;
447 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
448 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
449
450 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
451
452 for(; p < end; p++, reg++)
453 *p += __raw_readl(reg);
454 }
455
456 static int macb_halt_tx(struct macb *bp)
457 {
458 unsigned long halt_time, timeout;
459 u32 status;
460
461 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
462
463 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
464 do {
465 halt_time = jiffies;
466 status = macb_readl(bp, TSR);
467 if (!(status & MACB_BIT(TGO)))
468 return 0;
469
470 usleep_range(10, 250);
471 } while (time_before(halt_time, timeout));
472
473 return -ETIMEDOUT;
474 }
475
476 static void macb_tx_error_task(struct work_struct *work)
477 {
478 struct macb *bp = container_of(work, struct macb, tx_error_task);
479 struct macb_tx_skb *tx_skb;
480 struct sk_buff *skb;
481 unsigned int tail;
482
483 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
484 bp->tx_tail, bp->tx_head);
485
486 /* Make sure nobody is trying to queue up new packets */
487 netif_stop_queue(bp->dev);
488
489 /*
490 * Stop transmission now
491 * (in case we have just queued new packets)
492 */
493 if (macb_halt_tx(bp))
494 /* Just complain for now, reinitializing TX path can be good */
495 netdev_err(bp->dev, "BUG: halt tx timed out\n");
496
497 /* No need for the lock here as nobody will interrupt us anymore */
498
499 /*
500 * Treat frames in TX queue including the ones that caused the error.
501 * Free transmit buffers in upper layer.
502 */
503 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
504 struct macb_dma_desc *desc;
505 u32 ctrl;
506
507 desc = macb_tx_desc(bp, tail);
508 ctrl = desc->ctrl;
509 tx_skb = macb_tx_skb(bp, tail);
510 skb = tx_skb->skb;
511
512 if (ctrl & MACB_BIT(TX_USED)) {
513 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
514 macb_tx_ring_wrap(tail), skb->data);
515 bp->stats.tx_packets++;
516 bp->stats.tx_bytes += skb->len;
517 } else {
518 /*
519 * "Buffers exhausted mid-frame" errors may only happen
520 * if the driver is buggy, so complain loudly about those.
521 * Statistics are updated by hardware.
522 */
523 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
524 netdev_err(bp->dev,
525 "BUG: TX buffers exhausted mid-frame\n");
526
527 desc->ctrl = ctrl | MACB_BIT(TX_USED);
528 }
529
530 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
531 DMA_TO_DEVICE);
532 tx_skb->skb = NULL;
533 dev_kfree_skb(skb);
534 }
535
536 /* Make descriptor updates visible to hardware */
537 wmb();
538
539 /* Reinitialize the TX desc queue */
540 macb_writel(bp, TBQP, bp->tx_ring_dma);
541 /* Make TX ring reflect state of hardware */
542 bp->tx_head = bp->tx_tail = 0;
543
544 /* Now we are ready to start transmission again */
545 netif_wake_queue(bp->dev);
546
547 /* Housework before enabling TX IRQ */
548 macb_writel(bp, TSR, macb_readl(bp, TSR));
549 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
550 }
551
552 static void macb_tx_interrupt(struct macb *bp)
553 {
554 unsigned int tail;
555 unsigned int head;
556 u32 status;
557
558 status = macb_readl(bp, TSR);
559 macb_writel(bp, TSR, status);
560
561 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
562 macb_writel(bp, ISR, MACB_BIT(TCOMP));
563
564 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
565 (unsigned long)status);
566
567 head = bp->tx_head;
568 for (tail = bp->tx_tail; tail != head; tail++) {
569 struct macb_tx_skb *tx_skb;
570 struct sk_buff *skb;
571 struct macb_dma_desc *desc;
572 u32 ctrl;
573
574 desc = macb_tx_desc(bp, tail);
575
576 /* Make hw descriptor updates visible to CPU */
577 rmb();
578
579 ctrl = desc->ctrl;
580
581 if (!(ctrl & MACB_BIT(TX_USED)))
582 break;
583
584 tx_skb = macb_tx_skb(bp, tail);
585 skb = tx_skb->skb;
586
587 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
588 macb_tx_ring_wrap(tail), skb->data);
589 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
590 DMA_TO_DEVICE);
591 bp->stats.tx_packets++;
592 bp->stats.tx_bytes += skb->len;
593 tx_skb->skb = NULL;
594 dev_kfree_skb_irq(skb);
595 }
596
597 bp->tx_tail = tail;
598 if (netif_queue_stopped(bp->dev)
599 && CIRC_CNT(bp->tx_head, bp->tx_tail,
600 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
601 netif_wake_queue(bp->dev);
602 }
603
604 static void gem_rx_refill(struct macb *bp)
605 {
606 unsigned int entry;
607 struct sk_buff *skb;
608 struct macb_dma_desc *desc;
609 dma_addr_t paddr;
610
611 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
612 u32 addr, ctrl;
613
614 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
615 desc = &bp->rx_ring[entry];
616
617 /* Make hw descriptor updates visible to CPU */
618 rmb();
619
620 addr = desc->addr;
621 ctrl = desc->ctrl;
622 bp->rx_prepared_head++;
623
624 if ((addr & MACB_BIT(RX_USED)))
625 continue;
626
627 if (bp->rx_skbuff[entry] == NULL) {
628 /* allocate sk_buff for this free entry in ring */
629 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
630 if (unlikely(skb == NULL)) {
631 netdev_err(bp->dev,
632 "Unable to allocate sk_buff\n");
633 break;
634 }
635 bp->rx_skbuff[entry] = skb;
636
637 /* now fill corresponding descriptor entry */
638 paddr = dma_map_single(&bp->pdev->dev, skb->data,
639 bp->rx_buffer_size, DMA_FROM_DEVICE);
640
641 if (entry == RX_RING_SIZE - 1)
642 paddr |= MACB_BIT(RX_WRAP);
643 bp->rx_ring[entry].addr = paddr;
644 bp->rx_ring[entry].ctrl = 0;
645
646 /* properly align Ethernet header */
647 skb_reserve(skb, NET_IP_ALIGN);
648 }
649 }
650
651 /* Make descriptor updates visible to hardware */
652 wmb();
653
654 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
655 bp->rx_prepared_head, bp->rx_tail);
656 }
657
658 /* Mark DMA descriptors from begin up to and not including end as unused */
659 static void discard_partial_frame(struct macb *bp, unsigned int begin,
660 unsigned int end)
661 {
662 unsigned int frag;
663
664 for (frag = begin; frag != end; frag++) {
665 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
666 desc->addr &= ~MACB_BIT(RX_USED);
667 }
668
669 /* Make descriptor updates visible to hardware */
670 wmb();
671
672 /*
673 * When this happens, the hardware stats registers for
674 * whatever caused this is updated, so we don't have to record
675 * anything.
676 */
677 }
678
679 static int gem_rx(struct macb *bp, int budget)
680 {
681 unsigned int len;
682 unsigned int entry;
683 struct sk_buff *skb;
684 struct macb_dma_desc *desc;
685 int count = 0;
686
687 while (count < budget) {
688 u32 addr, ctrl;
689
690 entry = macb_rx_ring_wrap(bp->rx_tail);
691 desc = &bp->rx_ring[entry];
692
693 /* Make hw descriptor updates visible to CPU */
694 rmb();
695
696 addr = desc->addr;
697 ctrl = desc->ctrl;
698
699 if (!(addr & MACB_BIT(RX_USED)))
700 break;
701
702 desc->addr &= ~MACB_BIT(RX_USED);
703 bp->rx_tail++;
704 count++;
705
706 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
707 netdev_err(bp->dev,
708 "not whole frame pointed by descriptor\n");
709 bp->stats.rx_dropped++;
710 break;
711 }
712 skb = bp->rx_skbuff[entry];
713 if (unlikely(!skb)) {
714 netdev_err(bp->dev,
715 "inconsistent Rx descriptor chain\n");
716 bp->stats.rx_dropped++;
717 break;
718 }
719 /* now everything is ready for receiving packet */
720 bp->rx_skbuff[entry] = NULL;
721 len = MACB_BFEXT(RX_FRMLEN, ctrl);
722
723 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
724
725 skb_put(skb, len);
726 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
727 dma_unmap_single(&bp->pdev->dev, addr,
728 len, DMA_FROM_DEVICE);
729
730 skb->protocol = eth_type_trans(skb, bp->dev);
731 skb_checksum_none_assert(skb);
732
733 bp->stats.rx_packets++;
734 bp->stats.rx_bytes += skb->len;
735
736 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
737 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
738 skb->len, skb->csum);
739 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
740 skb->mac_header, 16, true);
741 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
742 skb->data, 32, true);
743 #endif
744
745 netif_receive_skb(skb);
746 }
747
748 gem_rx_refill(bp);
749
750 return count;
751 }
752
753 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
754 unsigned int last_frag)
755 {
756 unsigned int len;
757 unsigned int frag;
758 unsigned int offset;
759 struct sk_buff *skb;
760 struct macb_dma_desc *desc;
761
762 desc = macb_rx_desc(bp, last_frag);
763 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
764
765 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
766 macb_rx_ring_wrap(first_frag),
767 macb_rx_ring_wrap(last_frag), len);
768
769 /*
770 * The ethernet header starts NET_IP_ALIGN bytes into the
771 * first buffer. Since the header is 14 bytes, this makes the
772 * payload word-aligned.
773 *
774 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
775 * the two padding bytes into the skb so that we avoid hitting
776 * the slowpath in memcpy(), and pull them off afterwards.
777 */
778 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
779 if (!skb) {
780 bp->stats.rx_dropped++;
781 for (frag = first_frag; ; frag++) {
782 desc = macb_rx_desc(bp, frag);
783 desc->addr &= ~MACB_BIT(RX_USED);
784 if (frag == last_frag)
785 break;
786 }
787
788 /* Make descriptor updates visible to hardware */
789 wmb();
790
791 return 1;
792 }
793
794 offset = 0;
795 len += NET_IP_ALIGN;
796 skb_checksum_none_assert(skb);
797 skb_put(skb, len);
798
799 for (frag = first_frag; ; frag++) {
800 unsigned int frag_len = bp->rx_buffer_size;
801
802 if (offset + frag_len > len) {
803 BUG_ON(frag != last_frag);
804 frag_len = len - offset;
805 }
806 skb_copy_to_linear_data_offset(skb, offset,
807 macb_rx_buffer(bp, frag), frag_len);
808 offset += bp->rx_buffer_size;
809 desc = macb_rx_desc(bp, frag);
810 desc->addr &= ~MACB_BIT(RX_USED);
811
812 if (frag == last_frag)
813 break;
814 }
815
816 /* Make descriptor updates visible to hardware */
817 wmb();
818
819 __skb_pull(skb, NET_IP_ALIGN);
820 skb->protocol = eth_type_trans(skb, bp->dev);
821
822 bp->stats.rx_packets++;
823 bp->stats.rx_bytes += skb->len;
824 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
825 skb->len, skb->csum);
826 netif_receive_skb(skb);
827
828 return 0;
829 }
830
831 static int macb_rx(struct macb *bp, int budget)
832 {
833 int received = 0;
834 unsigned int tail;
835 int first_frag = -1;
836
837 for (tail = bp->rx_tail; budget > 0; tail++) {
838 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
839 u32 addr, ctrl;
840
841 /* Make hw descriptor updates visible to CPU */
842 rmb();
843
844 addr = desc->addr;
845 ctrl = desc->ctrl;
846
847 if (!(addr & MACB_BIT(RX_USED)))
848 break;
849
850 if (ctrl & MACB_BIT(RX_SOF)) {
851 if (first_frag != -1)
852 discard_partial_frame(bp, first_frag, tail);
853 first_frag = tail;
854 }
855
856 if (ctrl & MACB_BIT(RX_EOF)) {
857 int dropped;
858 BUG_ON(first_frag == -1);
859
860 dropped = macb_rx_frame(bp, first_frag, tail);
861 first_frag = -1;
862 if (!dropped) {
863 received++;
864 budget--;
865 }
866 }
867 }
868
869 if (first_frag != -1)
870 bp->rx_tail = first_frag;
871 else
872 bp->rx_tail = tail;
873
874 return received;
875 }
876
877 static int macb_poll(struct napi_struct *napi, int budget)
878 {
879 struct macb *bp = container_of(napi, struct macb, napi);
880 int work_done;
881 u32 status;
882
883 status = macb_readl(bp, RSR);
884 macb_writel(bp, RSR, status);
885
886 work_done = 0;
887
888 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
889 (unsigned long)status, budget);
890
891 work_done = bp->macbgem_ops.mog_rx(bp, budget);
892 if (work_done < budget) {
893 napi_complete(napi);
894
895 /*
896 * We've done what we can to clean the buffers. Make sure we
897 * get notified when new packets arrive.
898 */
899 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
900
901 /* Packets received while interrupts were disabled */
902 status = macb_readl(bp, RSR);
903 if (unlikely(status))
904 napi_reschedule(napi);
905 }
906
907 /* TODO: Handle errors */
908
909 return work_done;
910 }
911
912 static irqreturn_t macb_interrupt(int irq, void *dev_id)
913 {
914 struct net_device *dev = dev_id;
915 struct macb *bp = netdev_priv(dev);
916 u32 status;
917
918 status = macb_readl(bp, ISR);
919
920 if (unlikely(!status))
921 return IRQ_NONE;
922
923 spin_lock(&bp->lock);
924
925 while (status) {
926 /* close possible race with dev_close */
927 if (unlikely(!netif_running(dev))) {
928 macb_writel(bp, IDR, -1);
929 break;
930 }
931
932 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
933
934 if (status & MACB_RX_INT_FLAGS) {
935 /*
936 * There's no point taking any more interrupts
937 * until we have processed the buffers. The
938 * scheduling call may fail if the poll routine
939 * is already scheduled, so disable interrupts
940 * now.
941 */
942 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
943 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
944 macb_writel(bp, ISR, MACB_BIT(RCOMP));
945
946 if (napi_schedule_prep(&bp->napi)) {
947 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
948 __napi_schedule(&bp->napi);
949 }
950 }
951
952 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
953 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
954 schedule_work(&bp->tx_error_task);
955 break;
956 }
957
958 if (status & MACB_BIT(TCOMP))
959 macb_tx_interrupt(bp);
960
961 /*
962 * Link change detection isn't possible with RMII, so we'll
963 * add that if/when we get our hands on a full-blown MII PHY.
964 */
965
966 if (status & MACB_BIT(ISR_ROVR)) {
967 /* We missed at least one packet */
968 if (macb_is_gem(bp))
969 bp->hw_stats.gem.rx_overruns++;
970 else
971 bp->hw_stats.macb.rx_overruns++;
972 }
973
974 if (status & MACB_BIT(HRESP)) {
975 /*
976 * TODO: Reset the hardware, and maybe move the
977 * netdev_err to a lower-priority context as well
978 * (work queue?)
979 */
980 netdev_err(dev, "DMA bus error: HRESP not OK\n");
981 }
982
983 status = macb_readl(bp, ISR);
984 }
985
986 spin_unlock(&bp->lock);
987
988 return IRQ_HANDLED;
989 }
990
991 #ifdef CONFIG_NET_POLL_CONTROLLER
992 /*
993 * Polling receive - used by netconsole and other diagnostic tools
994 * to allow network i/o with interrupts disabled.
995 */
996 static void macb_poll_controller(struct net_device *dev)
997 {
998 unsigned long flags;
999
1000 local_irq_save(flags);
1001 macb_interrupt(dev->irq, dev);
1002 local_irq_restore(flags);
1003 }
1004 #endif
1005
1006 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1007 {
1008 struct macb *bp = netdev_priv(dev);
1009 dma_addr_t mapping;
1010 unsigned int len, entry;
1011 struct macb_dma_desc *desc;
1012 struct macb_tx_skb *tx_skb;
1013 u32 ctrl;
1014 unsigned long flags;
1015
1016 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1017 netdev_vdbg(bp->dev,
1018 "start_xmit: len %u head %p data %p tail %p end %p\n",
1019 skb->len, skb->head, skb->data,
1020 skb_tail_pointer(skb), skb_end_pointer(skb));
1021 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1022 skb->data, 16, true);
1023 #endif
1024
1025 len = skb->len;
1026 spin_lock_irqsave(&bp->lock, flags);
1027
1028 /* This is a hard error, log it. */
1029 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
1030 netif_stop_queue(dev);
1031 spin_unlock_irqrestore(&bp->lock, flags);
1032 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
1033 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1034 bp->tx_head, bp->tx_tail);
1035 return NETDEV_TX_BUSY;
1036 }
1037
1038 entry = macb_tx_ring_wrap(bp->tx_head);
1039 bp->tx_head++;
1040 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
1041 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1042 len, DMA_TO_DEVICE);
1043
1044 tx_skb = &bp->tx_skb[entry];
1045 tx_skb->skb = skb;
1046 tx_skb->mapping = mapping;
1047 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
1048 skb->data, (unsigned long)mapping);
1049
1050 ctrl = MACB_BF(TX_FRMLEN, len);
1051 ctrl |= MACB_BIT(TX_LAST);
1052 if (entry == (TX_RING_SIZE - 1))
1053 ctrl |= MACB_BIT(TX_WRAP);
1054
1055 desc = &bp->tx_ring[entry];
1056 desc->addr = mapping;
1057 desc->ctrl = ctrl;
1058
1059 /* Make newly initialized descriptor visible to hardware */
1060 wmb();
1061
1062 skb_tx_timestamp(skb);
1063
1064 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1065
1066 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
1067 netif_stop_queue(dev);
1068
1069 spin_unlock_irqrestore(&bp->lock, flags);
1070
1071 return NETDEV_TX_OK;
1072 }
1073
1074 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1075 {
1076 if (!macb_is_gem(bp)) {
1077 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1078 } else {
1079 bp->rx_buffer_size = size;
1080
1081 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1082 netdev_dbg(bp->dev,
1083 "RX buffer must be multiple of %d bytes, expanding\n",
1084 RX_BUFFER_MULTIPLE);
1085 bp->rx_buffer_size =
1086 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1087 }
1088 }
1089
1090 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1091 bp->dev->mtu, bp->rx_buffer_size);
1092 }
1093
1094 static void gem_free_rx_buffers(struct macb *bp)
1095 {
1096 struct sk_buff *skb;
1097 struct macb_dma_desc *desc;
1098 dma_addr_t addr;
1099 int i;
1100
1101 if (!bp->rx_skbuff)
1102 return;
1103
1104 for (i = 0; i < RX_RING_SIZE; i++) {
1105 skb = bp->rx_skbuff[i];
1106
1107 if (skb == NULL)
1108 continue;
1109
1110 desc = &bp->rx_ring[i];
1111 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1112 dma_unmap_single(&bp->pdev->dev, addr, skb->len,
1113 DMA_FROM_DEVICE);
1114 dev_kfree_skb_any(skb);
1115 skb = NULL;
1116 }
1117
1118 kfree(bp->rx_skbuff);
1119 bp->rx_skbuff = NULL;
1120 }
1121
1122 static void macb_free_rx_buffers(struct macb *bp)
1123 {
1124 if (bp->rx_buffers) {
1125 dma_free_coherent(&bp->pdev->dev,
1126 RX_RING_SIZE * bp->rx_buffer_size,
1127 bp->rx_buffers, bp->rx_buffers_dma);
1128 bp->rx_buffers = NULL;
1129 }
1130 }
1131
1132 static void macb_free_consistent(struct macb *bp)
1133 {
1134 if (bp->tx_skb) {
1135 kfree(bp->tx_skb);
1136 bp->tx_skb = NULL;
1137 }
1138 bp->macbgem_ops.mog_free_rx_buffers(bp);
1139 if (bp->rx_ring) {
1140 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1141 bp->rx_ring, bp->rx_ring_dma);
1142 bp->rx_ring = NULL;
1143 }
1144 if (bp->tx_ring) {
1145 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1146 bp->tx_ring, bp->tx_ring_dma);
1147 bp->tx_ring = NULL;
1148 }
1149 }
1150
1151 static int gem_alloc_rx_buffers(struct macb *bp)
1152 {
1153 int size;
1154
1155 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1156 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1157 if (!bp->rx_skbuff)
1158 return -ENOMEM;
1159 else
1160 netdev_dbg(bp->dev,
1161 "Allocated %d RX struct sk_buff entries at %p\n",
1162 RX_RING_SIZE, bp->rx_skbuff);
1163 return 0;
1164 }
1165
1166 static int macb_alloc_rx_buffers(struct macb *bp)
1167 {
1168 int size;
1169
1170 size = RX_RING_SIZE * bp->rx_buffer_size;
1171 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1172 &bp->rx_buffers_dma, GFP_KERNEL);
1173 if (!bp->rx_buffers)
1174 return -ENOMEM;
1175 else
1176 netdev_dbg(bp->dev,
1177 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1178 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1179 return 0;
1180 }
1181
1182 static int macb_alloc_consistent(struct macb *bp)
1183 {
1184 int size;
1185
1186 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1187 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1188 if (!bp->tx_skb)
1189 goto out_err;
1190
1191 size = RX_RING_BYTES;
1192 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1193 &bp->rx_ring_dma, GFP_KERNEL);
1194 if (!bp->rx_ring)
1195 goto out_err;
1196 netdev_dbg(bp->dev,
1197 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1198 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1199
1200 size = TX_RING_BYTES;
1201 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1202 &bp->tx_ring_dma, GFP_KERNEL);
1203 if (!bp->tx_ring)
1204 goto out_err;
1205 netdev_dbg(bp->dev,
1206 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1207 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
1208
1209 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1210 goto out_err;
1211
1212 return 0;
1213
1214 out_err:
1215 macb_free_consistent(bp);
1216 return -ENOMEM;
1217 }
1218
1219 static void gem_init_rings(struct macb *bp)
1220 {
1221 int i;
1222
1223 for (i = 0; i < TX_RING_SIZE; i++) {
1224 bp->tx_ring[i].addr = 0;
1225 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1226 }
1227 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1228
1229 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1230
1231 gem_rx_refill(bp);
1232 }
1233
1234 static void macb_init_rings(struct macb *bp)
1235 {
1236 int i;
1237 dma_addr_t addr;
1238
1239 addr = bp->rx_buffers_dma;
1240 for (i = 0; i < RX_RING_SIZE; i++) {
1241 bp->rx_ring[i].addr = addr;
1242 bp->rx_ring[i].ctrl = 0;
1243 addr += bp->rx_buffer_size;
1244 }
1245 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1246
1247 for (i = 0; i < TX_RING_SIZE; i++) {
1248 bp->tx_ring[i].addr = 0;
1249 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1250 }
1251 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1252
1253 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1254 }
1255
1256 static void macb_reset_hw(struct macb *bp)
1257 {
1258 /*
1259 * Disable RX and TX (XXX: Should we halt the transmission
1260 * more gracefully?)
1261 */
1262 macb_writel(bp, NCR, 0);
1263
1264 /* Clear the stats registers (XXX: Update stats first?) */
1265 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1266
1267 /* Clear all status flags */
1268 macb_writel(bp, TSR, -1);
1269 macb_writel(bp, RSR, -1);
1270
1271 /* Disable all interrupts */
1272 macb_writel(bp, IDR, -1);
1273 macb_readl(bp, ISR);
1274 }
1275
1276 static u32 gem_mdc_clk_div(struct macb *bp)
1277 {
1278 u32 config;
1279 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1280
1281 if (pclk_hz <= 20000000)
1282 config = GEM_BF(CLK, GEM_CLK_DIV8);
1283 else if (pclk_hz <= 40000000)
1284 config = GEM_BF(CLK, GEM_CLK_DIV16);
1285 else if (pclk_hz <= 80000000)
1286 config = GEM_BF(CLK, GEM_CLK_DIV32);
1287 else if (pclk_hz <= 120000000)
1288 config = GEM_BF(CLK, GEM_CLK_DIV48);
1289 else if (pclk_hz <= 160000000)
1290 config = GEM_BF(CLK, GEM_CLK_DIV64);
1291 else
1292 config = GEM_BF(CLK, GEM_CLK_DIV96);
1293
1294 return config;
1295 }
1296
1297 static u32 macb_mdc_clk_div(struct macb *bp)
1298 {
1299 u32 config;
1300 unsigned long pclk_hz;
1301
1302 if (macb_is_gem(bp))
1303 return gem_mdc_clk_div(bp);
1304
1305 pclk_hz = clk_get_rate(bp->pclk);
1306 if (pclk_hz <= 20000000)
1307 config = MACB_BF(CLK, MACB_CLK_DIV8);
1308 else if (pclk_hz <= 40000000)
1309 config = MACB_BF(CLK, MACB_CLK_DIV16);
1310 else if (pclk_hz <= 80000000)
1311 config = MACB_BF(CLK, MACB_CLK_DIV32);
1312 else
1313 config = MACB_BF(CLK, MACB_CLK_DIV64);
1314
1315 return config;
1316 }
1317
1318 /*
1319 * Get the DMA bus width field of the network configuration register that we
1320 * should program. We find the width from decoding the design configuration
1321 * register to find the maximum supported data bus width.
1322 */
1323 static u32 macb_dbw(struct macb *bp)
1324 {
1325 if (!macb_is_gem(bp))
1326 return 0;
1327
1328 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1329 case 4:
1330 return GEM_BF(DBW, GEM_DBW128);
1331 case 2:
1332 return GEM_BF(DBW, GEM_DBW64);
1333 case 1:
1334 default:
1335 return GEM_BF(DBW, GEM_DBW32);
1336 }
1337 }
1338
1339 /*
1340 * Configure the receive DMA engine
1341 * - use the correct receive buffer size
1342 * - set the possibility to use INCR16 bursts
1343 * (if not supported by FIFO, it will fallback to default)
1344 * - set both rx/tx packet buffers to full memory size
1345 * These are configurable parameters for GEM.
1346 */
1347 static void macb_configure_dma(struct macb *bp)
1348 {
1349 u32 dmacfg;
1350
1351 if (macb_is_gem(bp)) {
1352 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1353 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1354 dmacfg |= GEM_BF(FBLDO, 16);
1355 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1356 dmacfg &= ~GEM_BIT(ENDIA);
1357 gem_writel(bp, DMACFG, dmacfg);
1358 }
1359 }
1360
1361 /*
1362 * Configure peripheral capacities according to integration options used
1363 */
1364 static void macb_configure_caps(struct macb *bp)
1365 {
1366 if (macb_is_gem(bp)) {
1367 if (GEM_BFEXT(IRQCOR, gem_readl(bp, DCFG1)) == 0)
1368 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1369 }
1370 }
1371
1372 static void macb_init_hw(struct macb *bp)
1373 {
1374 u32 config;
1375
1376 macb_reset_hw(bp);
1377 macb_set_hwaddr(bp);
1378
1379 config = macb_mdc_clk_div(bp);
1380 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1381 config |= MACB_BIT(PAE); /* PAuse Enable */
1382 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1383 config |= MACB_BIT(BIG); /* Receive oversized frames */
1384 if (bp->dev->flags & IFF_PROMISC)
1385 config |= MACB_BIT(CAF); /* Copy All Frames */
1386 if (!(bp->dev->flags & IFF_BROADCAST))
1387 config |= MACB_BIT(NBC); /* No BroadCast */
1388 config |= macb_dbw(bp);
1389 macb_writel(bp, NCFGR, config);
1390 bp->speed = SPEED_10;
1391 bp->duplex = DUPLEX_HALF;
1392
1393 macb_configure_dma(bp);
1394 macb_configure_caps(bp);
1395
1396 /* Initialize TX and RX buffers */
1397 macb_writel(bp, RBQP, bp->rx_ring_dma);
1398 macb_writel(bp, TBQP, bp->tx_ring_dma);
1399
1400 /* Enable TX and RX */
1401 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1402
1403 /* Enable interrupts */
1404 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1405 | MACB_TX_INT_FLAGS
1406 | MACB_BIT(HRESP)));
1407
1408 }
1409
1410 /*
1411 * The hash address register is 64 bits long and takes up two
1412 * locations in the memory map. The least significant bits are stored
1413 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1414 *
1415 * The unicast hash enable and the multicast hash enable bits in the
1416 * network configuration register enable the reception of hash matched
1417 * frames. The destination address is reduced to a 6 bit index into
1418 * the 64 bit hash register using the following hash function. The
1419 * hash function is an exclusive or of every sixth bit of the
1420 * destination address.
1421 *
1422 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1423 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1424 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1425 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1426 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1427 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1428 *
1429 * da[0] represents the least significant bit of the first byte
1430 * received, that is, the multicast/unicast indicator, and da[47]
1431 * represents the most significant bit of the last byte received. If
1432 * the hash index, hi[n], points to a bit that is set in the hash
1433 * register then the frame will be matched according to whether the
1434 * frame is multicast or unicast. A multicast match will be signalled
1435 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1436 * index points to a bit set in the hash register. A unicast match
1437 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1438 * and the hash index points to a bit set in the hash register. To
1439 * receive all multicast frames, the hash register should be set with
1440 * all ones and the multicast hash enable bit should be set in the
1441 * network configuration register.
1442 */
1443
1444 static inline int hash_bit_value(int bitnr, __u8 *addr)
1445 {
1446 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1447 return 1;
1448 return 0;
1449 }
1450
1451 /*
1452 * Return the hash index value for the specified address.
1453 */
1454 static int hash_get_index(__u8 *addr)
1455 {
1456 int i, j, bitval;
1457 int hash_index = 0;
1458
1459 for (j = 0; j < 6; j++) {
1460 for (i = 0, bitval = 0; i < 8; i++)
1461 bitval ^= hash_bit_value(i*6 + j, addr);
1462
1463 hash_index |= (bitval << j);
1464 }
1465
1466 return hash_index;
1467 }
1468
1469 /*
1470 * Add multicast addresses to the internal multicast-hash table.
1471 */
1472 static void macb_sethashtable(struct net_device *dev)
1473 {
1474 struct netdev_hw_addr *ha;
1475 unsigned long mc_filter[2];
1476 unsigned int bitnr;
1477 struct macb *bp = netdev_priv(dev);
1478
1479 mc_filter[0] = mc_filter[1] = 0;
1480
1481 netdev_for_each_mc_addr(ha, dev) {
1482 bitnr = hash_get_index(ha->addr);
1483 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1484 }
1485
1486 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1487 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1488 }
1489
1490 /*
1491 * Enable/Disable promiscuous and multicast modes.
1492 */
1493 void macb_set_rx_mode(struct net_device *dev)
1494 {
1495 unsigned long cfg;
1496 struct macb *bp = netdev_priv(dev);
1497
1498 cfg = macb_readl(bp, NCFGR);
1499
1500 if (dev->flags & IFF_PROMISC)
1501 /* Enable promiscuous mode */
1502 cfg |= MACB_BIT(CAF);
1503 else if (dev->flags & (~IFF_PROMISC))
1504 /* Disable promiscuous mode */
1505 cfg &= ~MACB_BIT(CAF);
1506
1507 if (dev->flags & IFF_ALLMULTI) {
1508 /* Enable all multicast mode */
1509 macb_or_gem_writel(bp, HRB, -1);
1510 macb_or_gem_writel(bp, HRT, -1);
1511 cfg |= MACB_BIT(NCFGR_MTI);
1512 } else if (!netdev_mc_empty(dev)) {
1513 /* Enable specific multicasts */
1514 macb_sethashtable(dev);
1515 cfg |= MACB_BIT(NCFGR_MTI);
1516 } else if (dev->flags & (~IFF_ALLMULTI)) {
1517 /* Disable all multicast mode */
1518 macb_or_gem_writel(bp, HRB, 0);
1519 macb_or_gem_writel(bp, HRT, 0);
1520 cfg &= ~MACB_BIT(NCFGR_MTI);
1521 }
1522
1523 macb_writel(bp, NCFGR, cfg);
1524 }
1525 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1526
1527 static int macb_open(struct net_device *dev)
1528 {
1529 struct macb *bp = netdev_priv(dev);
1530 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1531 int err;
1532
1533 netdev_dbg(bp->dev, "open\n");
1534
1535 /* carrier starts down */
1536 netif_carrier_off(dev);
1537
1538 /* if the phy is not yet register, retry later*/
1539 if (!bp->phy_dev)
1540 return -EAGAIN;
1541
1542 /* RX buffers initialization */
1543 macb_init_rx_buffer_size(bp, bufsz);
1544
1545 err = macb_alloc_consistent(bp);
1546 if (err) {
1547 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1548 err);
1549 return err;
1550 }
1551
1552 napi_enable(&bp->napi);
1553
1554 bp->macbgem_ops.mog_init_rings(bp);
1555 macb_init_hw(bp);
1556
1557 /* schedule a link state check */
1558 phy_start(bp->phy_dev);
1559
1560 netif_start_queue(dev);
1561
1562 return 0;
1563 }
1564
1565 static int macb_close(struct net_device *dev)
1566 {
1567 struct macb *bp = netdev_priv(dev);
1568 unsigned long flags;
1569
1570 netif_stop_queue(dev);
1571 napi_disable(&bp->napi);
1572
1573 if (bp->phy_dev)
1574 phy_stop(bp->phy_dev);
1575
1576 spin_lock_irqsave(&bp->lock, flags);
1577 macb_reset_hw(bp);
1578 netif_carrier_off(dev);
1579 spin_unlock_irqrestore(&bp->lock, flags);
1580
1581 macb_free_consistent(bp);
1582
1583 return 0;
1584 }
1585
1586 static void gem_update_stats(struct macb *bp)
1587 {
1588 u32 __iomem *reg = bp->regs + GEM_OTX;
1589 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1590 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1591
1592 for (; p < end; p++, reg++)
1593 *p += __raw_readl(reg);
1594 }
1595
1596 static struct net_device_stats *gem_get_stats(struct macb *bp)
1597 {
1598 struct gem_stats *hwstat = &bp->hw_stats.gem;
1599 struct net_device_stats *nstat = &bp->stats;
1600
1601 gem_update_stats(bp);
1602
1603 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1604 hwstat->rx_alignment_errors +
1605 hwstat->rx_resource_errors +
1606 hwstat->rx_overruns +
1607 hwstat->rx_oversize_frames +
1608 hwstat->rx_jabbers +
1609 hwstat->rx_undersized_frames +
1610 hwstat->rx_length_field_frame_errors);
1611 nstat->tx_errors = (hwstat->tx_late_collisions +
1612 hwstat->tx_excessive_collisions +
1613 hwstat->tx_underrun +
1614 hwstat->tx_carrier_sense_errors);
1615 nstat->multicast = hwstat->rx_multicast_frames;
1616 nstat->collisions = (hwstat->tx_single_collision_frames +
1617 hwstat->tx_multiple_collision_frames +
1618 hwstat->tx_excessive_collisions);
1619 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1620 hwstat->rx_jabbers +
1621 hwstat->rx_undersized_frames +
1622 hwstat->rx_length_field_frame_errors);
1623 nstat->rx_over_errors = hwstat->rx_resource_errors;
1624 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1625 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1626 nstat->rx_fifo_errors = hwstat->rx_overruns;
1627 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1628 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1629 nstat->tx_fifo_errors = hwstat->tx_underrun;
1630
1631 return nstat;
1632 }
1633
1634 struct net_device_stats *macb_get_stats(struct net_device *dev)
1635 {
1636 struct macb *bp = netdev_priv(dev);
1637 struct net_device_stats *nstat = &bp->stats;
1638 struct macb_stats *hwstat = &bp->hw_stats.macb;
1639
1640 if (macb_is_gem(bp))
1641 return gem_get_stats(bp);
1642
1643 /* read stats from hardware */
1644 macb_update_stats(bp);
1645
1646 /* Convert HW stats into netdevice stats */
1647 nstat->rx_errors = (hwstat->rx_fcs_errors +
1648 hwstat->rx_align_errors +
1649 hwstat->rx_resource_errors +
1650 hwstat->rx_overruns +
1651 hwstat->rx_oversize_pkts +
1652 hwstat->rx_jabbers +
1653 hwstat->rx_undersize_pkts +
1654 hwstat->sqe_test_errors +
1655 hwstat->rx_length_mismatch);
1656 nstat->tx_errors = (hwstat->tx_late_cols +
1657 hwstat->tx_excessive_cols +
1658 hwstat->tx_underruns +
1659 hwstat->tx_carrier_errors);
1660 nstat->collisions = (hwstat->tx_single_cols +
1661 hwstat->tx_multiple_cols +
1662 hwstat->tx_excessive_cols);
1663 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1664 hwstat->rx_jabbers +
1665 hwstat->rx_undersize_pkts +
1666 hwstat->rx_length_mismatch);
1667 nstat->rx_over_errors = hwstat->rx_resource_errors +
1668 hwstat->rx_overruns;
1669 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1670 nstat->rx_frame_errors = hwstat->rx_align_errors;
1671 nstat->rx_fifo_errors = hwstat->rx_overruns;
1672 /* XXX: What does "missed" mean? */
1673 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1674 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1675 nstat->tx_fifo_errors = hwstat->tx_underruns;
1676 /* Don't know about heartbeat or window errors... */
1677
1678 return nstat;
1679 }
1680 EXPORT_SYMBOL_GPL(macb_get_stats);
1681
1682 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1683 {
1684 struct macb *bp = netdev_priv(dev);
1685 struct phy_device *phydev = bp->phy_dev;
1686
1687 if (!phydev)
1688 return -ENODEV;
1689
1690 return phy_ethtool_gset(phydev, cmd);
1691 }
1692
1693 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1694 {
1695 struct macb *bp = netdev_priv(dev);
1696 struct phy_device *phydev = bp->phy_dev;
1697
1698 if (!phydev)
1699 return -ENODEV;
1700
1701 return phy_ethtool_sset(phydev, cmd);
1702 }
1703
1704 static int macb_get_regs_len(struct net_device *netdev)
1705 {
1706 return MACB_GREGS_NBR * sizeof(u32);
1707 }
1708
1709 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1710 void *p)
1711 {
1712 struct macb *bp = netdev_priv(dev);
1713 unsigned int tail, head;
1714 u32 *regs_buff = p;
1715
1716 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1717 | MACB_GREGS_VERSION;
1718
1719 tail = macb_tx_ring_wrap(bp->tx_tail);
1720 head = macb_tx_ring_wrap(bp->tx_head);
1721
1722 regs_buff[0] = macb_readl(bp, NCR);
1723 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1724 regs_buff[2] = macb_readl(bp, NSR);
1725 regs_buff[3] = macb_readl(bp, TSR);
1726 regs_buff[4] = macb_readl(bp, RBQP);
1727 regs_buff[5] = macb_readl(bp, TBQP);
1728 regs_buff[6] = macb_readl(bp, RSR);
1729 regs_buff[7] = macb_readl(bp, IMR);
1730
1731 regs_buff[8] = tail;
1732 regs_buff[9] = head;
1733 regs_buff[10] = macb_tx_dma(bp, tail);
1734 regs_buff[11] = macb_tx_dma(bp, head);
1735
1736 if (macb_is_gem(bp)) {
1737 regs_buff[12] = gem_readl(bp, USRIO);
1738 regs_buff[13] = gem_readl(bp, DMACFG);
1739 }
1740 }
1741
1742 const struct ethtool_ops macb_ethtool_ops = {
1743 .get_settings = macb_get_settings,
1744 .set_settings = macb_set_settings,
1745 .get_regs_len = macb_get_regs_len,
1746 .get_regs = macb_get_regs,
1747 .get_link = ethtool_op_get_link,
1748 .get_ts_info = ethtool_op_get_ts_info,
1749 };
1750 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1751
1752 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1753 {
1754 struct macb *bp = netdev_priv(dev);
1755 struct phy_device *phydev = bp->phy_dev;
1756
1757 if (!netif_running(dev))
1758 return -EINVAL;
1759
1760 if (!phydev)
1761 return -ENODEV;
1762
1763 return phy_mii_ioctl(phydev, rq, cmd);
1764 }
1765 EXPORT_SYMBOL_GPL(macb_ioctl);
1766
1767 static const struct net_device_ops macb_netdev_ops = {
1768 .ndo_open = macb_open,
1769 .ndo_stop = macb_close,
1770 .ndo_start_xmit = macb_start_xmit,
1771 .ndo_set_rx_mode = macb_set_rx_mode,
1772 .ndo_get_stats = macb_get_stats,
1773 .ndo_do_ioctl = macb_ioctl,
1774 .ndo_validate_addr = eth_validate_addr,
1775 .ndo_change_mtu = eth_change_mtu,
1776 .ndo_set_mac_address = eth_mac_addr,
1777 #ifdef CONFIG_NET_POLL_CONTROLLER
1778 .ndo_poll_controller = macb_poll_controller,
1779 #endif
1780 };
1781
1782 #if defined(CONFIG_OF)
1783 static const struct of_device_id macb_dt_ids[] = {
1784 { .compatible = "cdns,at32ap7000-macb" },
1785 { .compatible = "cdns,at91sam9260-macb" },
1786 { .compatible = "cdns,macb" },
1787 { .compatible = "cdns,pc302-gem" },
1788 { .compatible = "cdns,gem" },
1789 { /* sentinel */ }
1790 };
1791 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1792 #endif
1793
1794 static int __init macb_probe(struct platform_device *pdev)
1795 {
1796 struct macb_platform_data *pdata;
1797 struct resource *regs;
1798 struct net_device *dev;
1799 struct macb *bp;
1800 struct phy_device *phydev;
1801 u32 config;
1802 int err = -ENXIO;
1803 struct pinctrl *pinctrl;
1804 const char *mac;
1805
1806 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1807 if (!regs) {
1808 dev_err(&pdev->dev, "no mmio resource defined\n");
1809 goto err_out;
1810 }
1811
1812 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1813 if (IS_ERR(pinctrl)) {
1814 err = PTR_ERR(pinctrl);
1815 if (err == -EPROBE_DEFER)
1816 goto err_out;
1817
1818 dev_warn(&pdev->dev, "No pinctrl provided\n");
1819 }
1820
1821 err = -ENOMEM;
1822 dev = alloc_etherdev(sizeof(*bp));
1823 if (!dev)
1824 goto err_out;
1825
1826 SET_NETDEV_DEV(dev, &pdev->dev);
1827
1828 /* TODO: Actually, we have some interesting features... */
1829 dev->features |= 0;
1830
1831 bp = netdev_priv(dev);
1832 bp->pdev = pdev;
1833 bp->dev = dev;
1834
1835 spin_lock_init(&bp->lock);
1836 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1837
1838 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
1839 if (IS_ERR(bp->pclk)) {
1840 err = PTR_ERR(bp->pclk);
1841 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
1842 goto err_out_free_dev;
1843 }
1844
1845 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
1846 if (IS_ERR(bp->hclk)) {
1847 err = PTR_ERR(bp->hclk);
1848 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
1849 goto err_out_free_dev;
1850 }
1851
1852 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
1853
1854 err = clk_prepare_enable(bp->pclk);
1855 if (err) {
1856 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
1857 goto err_out_free_dev;
1858 }
1859
1860 err = clk_prepare_enable(bp->hclk);
1861 if (err) {
1862 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
1863 goto err_out_disable_pclk;
1864 }
1865
1866 if (!IS_ERR(bp->tx_clk)) {
1867 err = clk_prepare_enable(bp->tx_clk);
1868 if (err) {
1869 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n",
1870 err);
1871 goto err_out_disable_hclk;
1872 }
1873 }
1874
1875 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
1876 if (!bp->regs) {
1877 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1878 err = -ENOMEM;
1879 goto err_out_disable_clocks;
1880 }
1881
1882 dev->irq = platform_get_irq(pdev, 0);
1883 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
1884 dev->name, dev);
1885 if (err) {
1886 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1887 dev->irq, err);
1888 goto err_out_disable_clocks;
1889 }
1890
1891 dev->netdev_ops = &macb_netdev_ops;
1892 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1893 dev->ethtool_ops = &macb_ethtool_ops;
1894
1895 dev->base_addr = regs->start;
1896
1897 /* setup appropriated routines according to adapter type */
1898 if (macb_is_gem(bp)) {
1899 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
1900 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
1901 bp->macbgem_ops.mog_init_rings = gem_init_rings;
1902 bp->macbgem_ops.mog_rx = gem_rx;
1903 } else {
1904 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
1905 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
1906 bp->macbgem_ops.mog_init_rings = macb_init_rings;
1907 bp->macbgem_ops.mog_rx = macb_rx;
1908 }
1909
1910 /* Set MII management clock divider */
1911 config = macb_mdc_clk_div(bp);
1912 config |= macb_dbw(bp);
1913 macb_writel(bp, NCFGR, config);
1914
1915 mac = of_get_mac_address(pdev->dev.of_node);
1916 if (mac)
1917 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1918 else
1919 macb_get_hwaddr(bp);
1920
1921 err = of_get_phy_mode(pdev->dev.of_node);
1922 if (err < 0) {
1923 pdata = dev_get_platdata(&pdev->dev);
1924 if (pdata && pdata->is_rmii)
1925 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1926 else
1927 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1928 } else {
1929 bp->phy_interface = err;
1930 }
1931
1932 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1933 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1934 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1935 #if defined(CONFIG_ARCH_AT91)
1936 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1937 MACB_BIT(CLKEN)));
1938 #else
1939 macb_or_gem_writel(bp, USRIO, 0);
1940 #endif
1941 else
1942 #if defined(CONFIG_ARCH_AT91)
1943 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1944 #else
1945 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1946 #endif
1947
1948 err = register_netdev(dev);
1949 if (err) {
1950 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1951 goto err_out_disable_clocks;
1952 }
1953
1954 err = macb_mii_init(bp);
1955 if (err)
1956 goto err_out_unregister_netdev;
1957
1958 platform_set_drvdata(pdev, dev);
1959
1960 netif_carrier_off(dev);
1961
1962 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1963 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1964 dev->irq, dev->dev_addr);
1965
1966 phydev = bp->phy_dev;
1967 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1968 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1969
1970 return 0;
1971
1972 err_out_unregister_netdev:
1973 unregister_netdev(dev);
1974 err_out_disable_clocks:
1975 if (!IS_ERR(bp->tx_clk))
1976 clk_disable_unprepare(bp->tx_clk);
1977 err_out_disable_hclk:
1978 clk_disable_unprepare(bp->hclk);
1979 err_out_disable_pclk:
1980 clk_disable_unprepare(bp->pclk);
1981 err_out_free_dev:
1982 free_netdev(dev);
1983 err_out:
1984 return err;
1985 }
1986
1987 static int __exit macb_remove(struct platform_device *pdev)
1988 {
1989 struct net_device *dev;
1990 struct macb *bp;
1991
1992 dev = platform_get_drvdata(pdev);
1993
1994 if (dev) {
1995 bp = netdev_priv(dev);
1996 if (bp->phy_dev)
1997 phy_disconnect(bp->phy_dev);
1998 mdiobus_unregister(bp->mii_bus);
1999 kfree(bp->mii_bus->irq);
2000 mdiobus_free(bp->mii_bus);
2001 unregister_netdev(dev);
2002 if (!IS_ERR(bp->tx_clk))
2003 clk_disable_unprepare(bp->tx_clk);
2004 clk_disable_unprepare(bp->hclk);
2005 clk_disable_unprepare(bp->pclk);
2006 free_netdev(dev);
2007 }
2008
2009 return 0;
2010 }
2011
2012 #ifdef CONFIG_PM
2013 static int macb_suspend(struct device *dev)
2014 {
2015 struct platform_device *pdev = to_platform_device(dev);
2016 struct net_device *netdev = platform_get_drvdata(pdev);
2017 struct macb *bp = netdev_priv(netdev);
2018
2019 netif_carrier_off(netdev);
2020 netif_device_detach(netdev);
2021
2022 if (!IS_ERR(bp->tx_clk))
2023 clk_disable_unprepare(bp->tx_clk);
2024 clk_disable_unprepare(bp->hclk);
2025 clk_disable_unprepare(bp->pclk);
2026
2027 return 0;
2028 }
2029
2030 static int macb_resume(struct device *dev)
2031 {
2032 struct platform_device *pdev = to_platform_device(dev);
2033 struct net_device *netdev = platform_get_drvdata(pdev);
2034 struct macb *bp = netdev_priv(netdev);
2035
2036 clk_prepare_enable(bp->pclk);
2037 clk_prepare_enable(bp->hclk);
2038 if (!IS_ERR(bp->tx_clk))
2039 clk_prepare_enable(bp->tx_clk);
2040
2041 netif_device_attach(netdev);
2042
2043 return 0;
2044 }
2045 #endif
2046
2047 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2048
2049 static struct platform_driver macb_driver = {
2050 .remove = __exit_p(macb_remove),
2051 .driver = {
2052 .name = "macb",
2053 .owner = THIS_MODULE,
2054 .of_match_table = of_match_ptr(macb_dt_ids),
2055 .pm = &macb_pm_ops,
2056 },
2057 };
2058
2059 module_platform_driver_probe(macb_driver, macb_probe);
2060
2061 MODULE_LICENSE("GPL");
2062 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
2063 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2064 MODULE_ALIAS("platform:macb");
Linux with added FPC-III support